diff --git a/docs/datasheet/Makefile b/docs/datasheet/Makefile new file mode 100644 index 00000000..5c2109b6 --- /dev/null +++ b/docs/datasheet/Makefile @@ -0,0 +1,97 @@ +ROOT_DIR = . +CONTENT_SRC = content +MAIN_SRC = datasheet +FIG_DIR = figures +FIG_RAW_DIR = figures_raw + + +# Get only the path to the Tgif source files. +TGIF_SRCS = $(wildcard $(ROOT_DIR)/$(FIG_RAW_DIR)/*.obj) +TGIF_SRCS_NAMES = $(basename $(TGIF_SRCS)) + +# Get only the path to the Tgif destination files. +TGIF_DEST = $(wildcard $(ROOT_DIR)/$(FIG_DIR)/*.obj) +TGIF_DEST_NAMES = $(basename $(TGIF_SRCS)) + +# Derive the file names for the resulting EPS and PDF file names for +# the TGIF sources. +TGIF_OUTP_NAMES = $(addprefix $(ROOT_DIR)/$(FIG_DIR)/, $(notdir $(TGIF_SRCS_NAMES))) +TGIF_OUTP_EPS_NAMES = $(addsuffix .eps, $(TGIF_OUTP_NAMES)) +TGIF_OUTP_PDF_NAMES = $(addsuffix .pdf, $(TGIF_OUTP_NAMES)) + + + +###################################################################### +##### # +##### Main Targets # +##### # +###################################################################### +do: pdf + +all: figures pdf + make -B pdf + make -B pdf + +pdf: $(MAIN_SRC).pdf + +%.pdf: %.tex $(CONTENT_SRC) preamble/preamble.tex + pdflatex $(MAIN_SRC).tex + +clean: clean-figures + @echo "***** Cleaning the LaTeX directory structure." + @rm -rf $(ROOT_DIR)/*.acr $(ROOT_DIR)/*.alg $(ROOT_DIR)/*.bbl + @rm -rf $(ROOT_DIR)/*.blg $(ROOT_DIR)/*.glg $(ROOT_DIR)/*.gls + @rm -rf $(ROOT_DIR)/*.aux $(ROOT_DIR)/*.glo $(ROOT_DIR)/*.ist + @rm -rf $(ROOT_DIR)/*.lof $(ROOT_DIR)/*.log $(ROOT_DIR)/*.lot + @rm -rf $(ROOT_DIR)/*.toc $(ROOT_DIR)/*.acn $(ROOT_DIR)/*.out + @rm -rf $(ROOT_DIR)/*.tex~ $(ROOT_DIR)/*.tex.backup + @rm -rf $(ROOT_DIR)/*.fdb_latexmk $(ROOT_DIR)/*.fls + @rm -rf $(ROOT_DIR)/Makefile~ $(ROOT_DIR)/pso.conv-* + @rm -rf $(ROOT_DIR)/auto + @rm -rf $(ROOT_DIR)/content/*.tex~ $(ROOT_DIR)/content/*.aux + @rm -rf $(ROOT_DIR)/content/*.log $(ROOT_DIR)/content/auto + @rm -rf $(ROOT_DIR)/content/*.tex.backup + @rm -rf $(ROOT_DIR)/content/*.fdb_latexmk $(ROOT_DIR)/content/*.fls + @rm -rf $(ROOT_DIR)/glossaries/*.tex~ $(ROOT_DIR)/glossaries/auto + @rm -rf $(ROOT_DIR)/preamble/auto $(ROOT_DIR)/preamble/*.tex~ + @rm -rf $(ROOT_DIR)/preamble/*.log + @rm -rf $(ROOT_DIR)/bib/auto $(ROOT_DIR)/bib/*.bib~ + @rm -rf $(ROOT_DIR)/bib/*.bib.backup + @rm -rf $(ROOT_DIR)/*.mtc* $(ROOT_DIR)/*.maf + + +###################################################################### +##### # +##### Sub Targets # +##### # +###################################################################### + +figures: tgif_figures + +tgif_figures: $(TGIF_OUTP_PDF_NAMES) + + +$(TGIF_OUTP_PDF_NAMES): $(ROOT_DIR)/$(FIG_DIR)/%.pdf : $(ROOT_DIR)/$(FIG_RAW_DIR)/%.obj + @echo "*****" + @echo "***** Printing Tgif figure:" + @echo "***************************" + @echo "***** $(ROOT_DIR)/$(FIG_RAW_DIR)/$*.eps" + @tgif -print -epsi -color -quiet $(ROOT_DIR)/$(FIG_RAW_DIR)/$*.obj + @echo "*****" + @echo "***** Converting Tgif EPS to PDF:" + @echo "*********************************" + @echo "***** $(ROOT_DIR)/$(FIG_RAW_DIR)/$*.eps --> $(ROOT_DIR)/$(FIG_RAW_DIR)/$*.pdf" + @epstopdf $(ROOT_DIR)/$(FIG_RAW_DIR)/$*.eps + @echo "*****" + @echo "***** Moving EPS and PDF figures" + @echo "********************************" + @echo "***** $(ROOT_DIR)/$(FIG_RAW_DIR)/$*.eps --> $(ROOT_DIR)/$(FIG_DIR)/$*.eps" + @echo "***** $(ROOT_DIR)/$(FIG_RAW_DIR)/$*.pdf --> $(ROOT_DIR)/$(FIG_DIR)/$*.pdf" + -@mv $(ROOT_DIR)/$(FIG_RAW_DIR)/$*.eps $(ROOT_DIR)/$(FIG_DIR)/ + -@mv $(ROOT_DIR)/$(FIG_RAW_DIR)/$*.pdf $(ROOT_DIR)/$(FIG_DIR)/ + @echo "*****" + +clean-tgif-figures: + -@rm -f $(TGIF_OUTP_EPS_NAMES) $(TGIF_OUTP_PDF_NAMES) + +clean-figures: clean-tgif-figures diff --git a/docs/datasheet/content/csr.tex b/docs/datasheet/content/csr.tex new file mode 100644 index 00000000..8716dafe --- /dev/null +++ b/docs/datasheet/content/csr.tex @@ -0,0 +1,7 @@ +\chapter{Control and Status Registers} + +\rvcore does not implement all control and status registers specified in the +\riscv privileged specifications, but is limited to the registers that were +needed for the PULP system. +The reason for this is that we wanted to keep the footprint of the core as low +as possible and avoid any overhead that we do not explicitely need. diff --git a/docs/datasheet/content/if.tex b/docs/datasheet/content/if.tex new file mode 100644 index 00000000..792e4e1c --- /dev/null +++ b/docs/datasheet/content/if.tex @@ -0,0 +1,37 @@ +\chapter{Instruction Fetch} + +The instruction fetcher of the core is able to supply one instruction to the ID +stage per cycle if the instruction cache or the instruction memory is able to +deliver an instruction after one cycle. +The instruction address must be word-aligned. It is not possible to jump to +misaligned memory addresses. + +Branch prediction is used for branches where the branch decision is not yet +known, i.e. if the \instr{l.sf*} instruction precedes the \instr{l.bf} or +\instr{l.bnf} instruction directly. +Branch prediction assumes that backward branches are never taken and forward +branches are always taken. If the branch predicition guessed wrong, one fetched +instruction is wasted. + +Table~\ref{tab:instr_signals} describes the signals that are used by to fetch +instructions. + + +\begin{table}[H] + \caption{Instruction Fetch Signals} + \label{tab:instr_signals} + \begin{tabularx}{\textwidth}{@{}llX@{}} \toprule + \textbf{Signal} & \textbf{Direction} & \textbf{Description} \\ \toprule + \signal{instr\_req\_o} & \textbf{output} & Request ready, must stay high until \signal{instr\_gnt\_i} is high for one cycle \\ \hline + \signal{instr\_addr\_o[31:0]} & \textbf{output} & Address \\ \hline + \signal{instr\_rdata\_i[31:0]} & \textbf{input} & Data read from memory \\ \hline + \signal{instr\_rvalid\_i} & \textbf{input} & \signal{instr\_rdata\_i} is valid now for this cycle. When \signal{instr\_rvalid\_i} is high, another request can be sent. \\ \hline + \signal{instr\_gnt\_i} & \textbf{input} & The instruction cache accepted the request. The \signal{instr\_addr\_o} may be change in the next cylce. \\ \bottomrule + \end{tabularx} +\end{table} + + +\section{Protocol} +The protocol used to communicate with the instruction cache or the instruction +memory is the same as the protocl used by the LSU. See the description of the +LSU in Section~\ref{sec:lsu_protocol} for details about the protocol. diff --git a/docs/datasheet/content/lsu.tex b/docs/datasheet/content/lsu.tex new file mode 100644 index 00000000..9dc209c0 --- /dev/null +++ b/docs/datasheet/content/lsu.tex @@ -0,0 +1,126 @@ +\chapter{Load-Store-Unit (LSU)} + +The LSU of the core takes care of accessing the data memory. Load and stores on +words (32 bit), half words (16 bit) and bytes (8 bit) are supported. + +Table~\ref{tab:lsu_signals} describes the signals that are used by the LSU. + + +\begin{table}[H] + \caption{LSU Signals} + \label{tab:lsu_signals} + \begin{tabularx}{\textwidth}{@{}llX@{}} \toprule + \textbf{Signal} & \textbf{Direction} & \textbf{Description} \\ \toprule + \signal{data\_req\_o} & \textbf{output} & Request ready, must stay high until \signal{data\_gnt\_i} is high for one cycle \\ \hline + \signal{data\_addr\_o[31:0]} & \textbf{output} & Address \\ \hline + \signal{data\_we\_o} & \textbf{output} & Write Enable, high if we want to write, low if we want to read \\ \hline + \signal{data\_be\_o[3:0]} & \textbf{output} & Byte Enable, is set for the bytes to write/read \\ \hline + \signal{data\_wdata\_o[31:0]} & \textbf{output} & Data to be written to memory \\ \hline + \signal{data\_rdata\_i[31:0]} & \textbf{input} & Data read from memory \\ \hline + \signal{data\_rvalid\_i} & \textbf{input} & \signal{data\_rdata\_i} is valid. This signal must always be identical to \signal{data\_gnt\_i} delayed by one cycle. \\ \hline + \signal{data\_gnt\_i} & \textbf{input} & The memory accepted the request and will answer in the next cycle with valid rdata \\ \bottomrule + \end{tabularx} +\end{table} + +\section{Misaligned Accesses} +The LSU is able to perform misaligned accesses, meaning accesses that are not +aligned on natural word boundaries. However it needs to perform two separate +word-aligned accesses internally. +This means that at least two cycles are needed for misaligned loads and stores. + + +\section{Post-Increment Load and Stores} + +Post-incrementing load and store instructions perform a load/store operation +from/to the data memory while at the same time increasing the base address by +the specified offset. +Post-incrementing load and stores reduce the number of instructions necessary to +execute when running in a loop, i.e. the address increment can be embedded in +the post-increment instructions. + + +\section{Protocol} +\label{sec:lsu_protocol} + +The protocol that is used by the LSU to communicate with a memory works as +follows: +The LSU provides a valid address in \signal{data\_addr\_o} and sets +\signal{data\_req\_o} high. The memory then answers with a \signal{data\_gnt\_i} +set high as soon as it is ready to serve the request. This may happen in the +same cycle as the request was sent or any number of cycles later. After a grant +was received, the address may be changed by the LSU without impact. Also the +\signal{data\_wdata\_o}, \signal{data\_we\_o} and \signal{data\_be\_o} signals +may be changed as it is assumed that the memory has already processed that +information. In the case of a read, the memory answers with a +\signal{data\_rvalid\_i} set high when \signal{data\_rdata\_i} is valid. This +may happen one cycle after the grant was received, but may take any number of +cycles after the grant was received. +Starting from the cycle when \signal{data\_rvalid\_i} was asserted, another +request may be sent. + +Figure~\ref{fig:lsu_trans_basic}, Figure~\ref{fig:lsu_trans_b2b} and +Figure~\ref{fig:lsu_trans_slow} show timing diagrams of the protocol. + +\begin{figure}[H] + \centering + \begin{tikztimingtable} + [timing/d/background/.style={fill=white}, + timing/lslope=0.1, + xscale=3] + + clk & 13{C} \\ + data\_addr\_o & UUU 4D{Address} UU UU UU \\ + data\_wdata\_o & UUU 4D{WData} UU UU UU \\ + data\_req\_o & LLL HH HH LL LL LL \\ + data\_gnt\_i & LLL LL HH LL LL LL \\ + data\_rvalid\_i & LLL LL LL HH LL LL \\ + data\_rdata\_i & UUU UU UU 2D{RData} UU UU \\ + data\_we\_o & UUU 4D{WE} UU UU UU \\ + data\_be\_o & UUU 4D{BE} UU UU UU \\ + \end{tikztimingtable} + \caption{Basic Memory Transaction} + \label{fig:lsu_trans_basic} +\end{figure} + + +\begin{figure}[H] + \centering + \begin{tikztimingtable} + [timing/d/background/.style={fill=white}, + timing/lslope=0.1, + xscale=3] + + clk & 13{C} \\ + data\_addr\_o & U 2D{Addr1} 2D{Addr2} UU UU UU UU \\ + data\_wdata\_o & U 2D{WData1} 2D{Wdata2} UU UU UU UU \\ + data\_req\_o & L HH HH LL LL LL LL \\ + data\_gnt\_i & L HH HH LL LL LL LL \\ + data\_rvalid\_i & L LL HH HH LL LL LL \\ + data\_rdata\_i & U UU 2D{RData1} 2D{RData2} UU UU UU\\ + data\_we\_o & U 2D{WE1} 2D{WE2} UU UU UU UU \\ + data\_be\_o & U 2D{BE1} 2D{BE2} UU UU UU UU \\ + \end{tikztimingtable} + \caption{Back to Back Memory Transaction} + \label{fig:lsu_trans_b2b} +\end{figure} + +\begin{figure}[H] + \centering + \begin{tikztimingtable} + [timing/d/background/.style={fill=white}, + timing/lslope=0.1, + xscale=3] + + clk & 13{C} \\ + data\_addr\_o & U 6D{Address} UU UU UU \\ + data\_wdata\_o & U 6D{WData} UU UU UU \\ + data\_req\_o & L HH HH HH LL LL LL \\ + data\_gnt\_i & LLL LL HH LL LL LL \\ + data\_rvalid\_i & LLL LL LL LL HH UU \\ + data\_rdata\_i & UUU UU UU UU 2D{RData} UU \\ + data\_we\_o & U 6D{WE} UU UU UU \\ + data\_be\_o & U 6D{BE} UU UU UU \\ + \end{tikztimingtable} + \caption{Slow Answer Memory Transaction} + \label{fig:lsu_trans_slow} +\end{figure} diff --git a/docs/datasheet/content/mac.tex b/docs/datasheet/content/mac.tex new file mode 100644 index 00000000..86889b75 --- /dev/null +++ b/docs/datasheet/content/mac.tex @@ -0,0 +1,6 @@ +\chapter{Multiplier} + +\rvcore uses a single-cycle 32 bit lower result multiplier. Only a subset of the +standard M extension is implemented, i.e. the \instr{mul} instruction. +Divisions and multiplications that return the upper half of the result are not +supported. diff --git a/docs/datasheet/content/overview.tex b/docs/datasheet/content/overview.tex new file mode 100644 index 00000000..285dd4b8 --- /dev/null +++ b/docs/datasheet/content/overview.tex @@ -0,0 +1,15 @@ +\chapter{Overview} + +\rvcore is a 4-stage in-order \riscv CPU. The ISA of \rvcore was extended to +also support multiple additional instructions including hardware loops, +post-increment load and store instructions and packed-SIMD instructions that +were not part of the standard \riscv ISA. + +Figure~\ref{fig:ri5cy_overview} shows a block diagram of the core. + +\begin{figure}[H] + \centering + \includegraphics[width=0.9\textwidth]{./figures/ri5cy_overview} + \caption{\rvcore Overview.} + \label{fig:ri5cy_overview} +\end{figure} diff --git a/docs/datasheet/content/perfcounters.tex b/docs/datasheet/content/perfcounters.tex new file mode 100644 index 00000000..b490df53 --- /dev/null +++ b/docs/datasheet/content/perfcounters.tex @@ -0,0 +1,132 @@ +\chapter{Performance Counters} +\label{chap:perf_count} + +Performance Counters in \orion are placed inside the Special-Purpose Registers +and can be accessed with \instr{l.mfspr} and \instr{l.mtspr}. +Figure~\ref{fig:spr_addr} shows the SPR address format and +Table~\ref{tab:pc_spr_addr} shows the respective addresses for configuration and +access to the performance counters. + +\begin{table}[H] + \caption{PC SPR Addresses} + \label{tab:pc_spr_addr} + \centering\begin{tabularx}{\textwidth}{@{}ccccX@{}} \toprule + \textbf{Group \#} & \textbf{Reg \#} & Reg Name & Access & Description\\ \toprule + 7 & 0 - 31 & PCCR0-PCCR31 & R/W & Performance Counters Count Registers \\ \hline + 7 & 32 & PCER & R/W & Performance Counters Event Register \\ \hline + 7 & 33 & PCMR & R/W & Performance Counters Mode Register \\ \bottomrule + \end{tabularx} +\end{table} + + +\section{Performance Counters Mode Register (PCMR)} + +\sprDesc{0x3821}{0x0000\_0003}{PCMR}{ + \begin{bytefield}[endianness=big,bitheight=60pt]{32} + \bitheader{31,1,0} \\ + \bitbox{30}{ Unused } + \bitbox{1}{\rotatebox{90}{\tiny Saturation }} + \bitbox{1}{\rotatebox{90}{\tiny Global Enable }} + \end{bytefield} +} + +The \instr{Global Enable} bit controls all performance counters, i.e. if it is set +to \instr{0}, all performance counters are deactivated. +After reset, the \instr{Global Enable} bit is set. + +The \instr{Saturation} bit controls saturation behaviour of the performance +counters. If it is set, saturating arithmetic is used. +After reset, the \instr{Saturation} bit is set. + +\section{Performance Counters Event Register (PCER)} + +\sprDesc{0x3820}{0x0000\_0000}{PCER}{ + \begin{bytefield}[endianness=big,bitheight=60pt]{32} + \bitheader{31,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0} \\ + \bitbox{1}{\rotatebox{90}{\tiny (ALL) }} + \bitbox{14}{ Unused } + \bitbox{1}{\rotatebox{90}{\tiny TCDM CONT }} + \bitbox{1}{\rotatebox{90}{\tiny ST\_EXT\_CYC }} + \bitbox{1}{\rotatebox{90}{\tiny LD\_EXT\_CYC }} + \bitbox{1}{\rotatebox{90}{\tiny ST\_EXT }} + \bitbox{1}{\rotatebox{90}{\tiny LD\_EXT }} + \bitbox{1}{\rotatebox{90}{\tiny DELAY\_SLOT }} + \bitbox{1}{\rotatebox{90}{\tiny BRANCH }} + \bitbox{1}{\rotatebox{90}{\tiny JUMP }} + \bitbox{1}{\rotatebox{90}{\tiny ST }} + \bitbox{1}{\rotatebox{90}{\tiny LD }} + \bitbox{1}{\rotatebox{90}{\tiny WBRANCH\_CYC }} + \bitbox{1}{\rotatebox{90}{\tiny WBRANCH }} + \bitbox{1}{\rotatebox{90}{\tiny IMISS }} + \bitbox{1}{\rotatebox{90}{\tiny JMP\_STALL }} + \bitbox{1}{\rotatebox{90}{\tiny LD\_STALL }} + \bitbox{1}{\rotatebox{90}{\tiny INSTR }} + \bitbox{1}{\rotatebox{90}{\tiny CYCLES }} + \end{bytefield} +} + +Each bit in the PCER register controls one performance counter. If the bit is +1, the counter is enabled and starts counting events. If it is 0, the counter +is disabled and its value won't change. + +In the ASIC there is only one counter register, thus all counter events are +masked by PCER are ORed together, i.e. if one of the enabled event happens, +the counter will be increased. If multiple non-masked events happen at the same +time, the counter will only be increased by one. + +In the FPGA or Simulation version each event has its own counter and can be +accesses separately. + + +\section{Performance Counters Counter Registers (PCCR0-31)} + +\sprDesc{0x3800 - 0x381F}{0x0000\_0000}{PCCR0-31}{ + \begin{bytefield}[endianness=big]{32} + \bitheader{31,0} \\ + \bitbox{32}{Unsigned integer counter value} + \end{bytefield} +} + +PCCR registers support both saturating and wrap-around arithmetic. This is +controlled by the \instr{saturation} bit in PCMR. + +\begin{table}[H] +\begin{tabularx}{\textwidth}{@{}llX@{}} \toprule + \textbf{Reg Name} & \textbf{Name} & Description \\ \toprule + \textbf{PCCR0} & \textbf{CYCLES} & Count the number of cycles the core was running \\ \hline + \textbf{PCCR1} & \textbf{INSTR} & Count the number of instructions executed \\ \hline + \textbf{PCCR2} & \textbf{LD\_STALL} & Number of load data hazards \\ \hline + \textbf{PCCR3} & \textbf{JMP\_STALL} & Number of jump register data hazards \\ \hline + \textbf{PCCR4} & \textbf{IMISS} & Cycles waiting for instruction fetches. i.e. the number of instructions wasted due to non-ideal caches \\ \hline + \textbf{PCCR5} & \textbf{WBRANCH} & Number of wrong predicted branches \\ \hline + \textbf{PCCR6} & \textbf{WBRANCH\_CYC} & Cycles wasted due to wrong predicted branches \\ \hline + \textbf{PCCR7} & \textbf{LD} & Number of memory loads executed. Misaligned accesses are counted twice \\ \hline + \textbf{PCCR8} & \textbf{ST} & Number of memory stores executed. Misaligned accesses are counted twice \\ \hline + \textbf{PCCR9} & \textbf{JUMP} & Number of jumps (j, jal, jr, jalr)\\ \hline + \textbf{PCCR10} & \textbf{BRANCH} & Number of branches (bf, bnf), counts taken and not taken branches\\ \hline + \textbf{PCCR11} & \textbf{DELAY\_NOP} & Number of empty (l.nop) delay slots \\ \hline + \textbf{PCCR12} & \textbf{LD\_EXT} & Number of memory loads to EXT executed. Misaligned accesses are counted twice. Every non-TCDM access is considered external \\ \hline + \textbf{PCCR13} & \textbf{ST\_EXT} & Number of memory stores to EXT executed. Misaligned accesses are counted twice. Every non-TCDM access is considered external \\ \hline + \textbf{PCCR14} & \textbf{LD\_EXT\_CYC} & Cycles used for memory loads to EXT. Every non-TCDM access is considered external \\ \hline + \textbf{PCCR15} & \textbf{ST\_EXT\_CYC} & Cycles used for memory stores to EXT. Every non-TCDM access is considered external \\ \hline + \textbf{PCCR16} & \textbf{TCDM\_CONT} & Cycles wasted due to TCDM/log-interconnect contention \\ \hline + \textbf{PCCR31} & \textbf{ALL} & Special Register, a write to this register will set all counters to the supplied value\\ \bottomrule +\end{tabularx} +\end{table} + +In the FPGA, RTL simulation and Virtual-Platform there are individual counters +for each event type, i.e. PCCR0-30 each represent a separate register. +To save area in the ASIC, there is only one counter and one counter register. +Accessing PCCR0-30 will access the same counter register in the ASIC. +Reading/writing from/to PCCR31 in the ASIC will access the same register as +PCCR0-30. + +Figure~\ref{fig:events} shows how events are first masked with the PCER register +and then ORed together to increase the one performance counter PCCR. + +\begin{figure}[H] + \centering + \includegraphics[width=0.5\textwidth]{./figures/events} + \caption{Events and PCCR, PCMR and PCER on the ASIC.} + \label{fig:events} +\end{figure} diff --git a/docs/datasheet/datasheet.tex b/docs/datasheet/datasheet.tex new file mode 100644 index 00000000..9fb8fb21 --- /dev/null +++ b/docs/datasheet/datasheet.tex @@ -0,0 +1,41 @@ +\documentclass[% + oneside, % Use the same margins for odd and even pages (cannot + % be used with the 'twoside' option). +% twoside, % Use different margins for odd and even pages (cannot + % be used with the 'oneside' option). + openany, % Open chapters on odd and even pages. + halfparskip, % Create small spaces for new paragraphs but no indents. +]{scrbook} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%% % +%%%%% Preamble % +%%%%% % +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% Load the preamble from another file. +\input{./preamble/preamble} + + +%%%%% Mandatory title page settings. +\title{RI5CY: Datasheet} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%% % +%%%%% Document starts here % +%%%%% % +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\begin{document} + +\maketitle + +\tableofcontents + +\input{./content/overview.tex} +\input{./content/if.tex} +\input{./content/lsu.tex} +\input{./content/mac.tex} +\input{./content/csr.tex} +\input{./content/perfcounters.tex} + + +\end{document} diff --git a/docs/datasheet/figures/.gitignore b/docs/datasheet/figures/.gitignore new file mode 100644 index 00000000..e69de29b diff --git a/docs/datasheet/figures_raw/events.obj b/docs/datasheet/figures_raw/events.obj new file mode 100644 index 00000000..7c0ef9f3 --- /dev/null +++ b/docs/datasheet/figures_raw/events.obj @@ -0,0 +1,477 @@ +%TGIF 4.2.5-QPL +state(0,37,100.000,0,0,0,64,1,0,2,2,0,0,0,0,1,1,'Courier',0,57600,0,0,0,10,0,0,1,1,0,16,0,0,1,1,1,1,1050,1485,1,0,5760,0). +% +% @(#)$Header$ +% %W% +% +unit("1 pixel/pixel"). +color_info(51,65535,0,[ + "black", 0, 0, 0, 0, 0, 0, 1, + "white", 65535, 65535, 65535, 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--------------------------------------------------------------------- + +% Provides the algorithm environment +\usepackage[ruled,% + linesnumbered]{algorithm2e} + +% --------------------------------------------------------------------- + +% Provides simple line spacings. +\usepackage{setspace} + +% --------------------------------------------------------------------- + +% Provides colors in LaTeX. +\usepackage{xcolor} + +% --------------------------------------------------------------------- + +% Provides nicer tables than the standard tables. +\usepackage{booktabs} + +\usepackage{float} +\usepackage{listings} +\usepackage{amsmath} + +%\usepackage{caption} +\usepackage{bytefield} + +\usepackage{fullpage} + +\usepackage{enumitem} + + +\usepackage{tikz-timing}[2009/05/15] + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%% % +%%%%% Custom Macros % +%%%%% % +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% Create an inline command for shell commands. +\newcommand{\shell}[1]{\texttt{#1}} + +% Create an enviroment for a shell commands. +\newenvironment{shellenv}% +{\VerbatimEnvironment% + \begin{Sbox}\begin{minipage}{0.97\textwidth}\begin{Verbatim}% +}% +{\end{Verbatim}\end{minipage}\end{Sbox}% +\setlength{\fboxsep}{6pt}\shadowbox{\TheSbox}}% + +% Create an inline command for files. +\newcommand{\file}[1]{\texttt{#1}} + +% Create a command for command parameters. +\newcommand{\parameter}[1]{$<$#1$>$} + +\newcommand{\instr}[1]{\texttt{#1}} + + +\definecolor{lightGray}{RGB}{240,240,240} + +\lstnewenvironment{instrenv}{\lstset{backgroundcolor=\color{lightGray},frame=single,basicstyle=\ttfamily}}{} + +\newcommand{\orion}{\textsc{Or10n}\xspace} +\newcommand{\riscv}{\mbox{RISC-V}\xspace} +\newcommand{\rvcore}{\textsc{RI5CY}\xspace} +\newcommand{\pulpino}{\textsc{PULPino}\xspace} +\newcommand{\pulp}{\textsc{PULP}\xspace} + +\newcommand\signal[1]{{\ttfamily\bfseries #1}} + +\newcommand\sprDesc[4]{% + \textbf{SPR Address:} \texttt{#1}\\% + \textbf{Reset Value:} \texttt{#2}\\% + \begin{figure}[H] + \centering + #4 + \caption{#3} + \end{figure}} +