diff --git a/controller.sv b/controller.sv index f68b148d..6bea907a 100644 --- a/controller.sv +++ b/controller.sv @@ -117,10 +117,6 @@ module controller output logic dbg_trap_o, // trap hit, inform debug unit // SPR Signals - input logic sr_flag_fw_i, // forwared branch signal - input logic sr_flag_i, // branch signal - input logic set_flag_ex_i, // alu is currently updating the flag if 1 - output logic set_flag_o, // to special purpose registers --> flag output logic set_carry_o, // to special purpose registers --> carry output logic set_overflow_o, // to special purpose registers --> overflow output logic restore_sr_o, // restores status register after interrupt @@ -165,7 +161,6 @@ module controller logic regfile_alu_we; logic data_we; logic data_req; - logic set_flag; logic set_overflow; logic set_carry; logic deassert_we; @@ -248,7 +243,6 @@ module controller data_reg_offset_o = 2'b00; data_req = 1'b0; - set_flag = 1'b0; set_overflow = 1'b0; set_carry = 1'b0; @@ -1164,7 +1158,6 @@ module controller assign regfile_alu_we_o = (deassert_we) ? 1'b0 : regfile_alu_we; assign data_we_o = (deassert_we) ? 1'b0 : data_we; assign data_req_o = (deassert_we) ? 1'b0 : data_req; - assign set_flag_o = (deassert_we) ? 1'b0 : set_flag; assign set_overflow_o = (deassert_we) ? 1'b0 : set_overflow; assign set_carry_o = (deassert_we) ? 1'b0 : set_carry; diff --git a/ex_stage.sv b/ex_stage.sv index 18bc9d65..85d2ccc6 100644 --- a/ex_stage.sv +++ b/ex_stage.sv @@ -49,7 +49,6 @@ module ex_stage input logic [31:0] alu_operand_b_i, input logic [31:0] alu_operand_c_i, input logic alu_carry_i, - input logic alu_flag_i, input logic [1:0] vector_mode_i, input logic [1:0] alu_cmp_mode_i, @@ -93,9 +92,6 @@ module ex_stage // Output of EX stage pipeline - //interface with Special registers - output logic alu_flag_o, - output logic carry_o, output logic overflow_o, @@ -203,7 +199,6 @@ module ex_stage .operand_b_i ( alu_operand_b_i ), .operand_c_i ( alu_operand_c_i ), .carry_i ( alu_carry_i ), - .flag_i ( alu_flag_i ), .vector_mode_i ( vector_mode_i ), .cmp_mode_i ( alu_cmp_mode_i ), @@ -214,7 +209,6 @@ module ex_stage .result_o ( alu_result ), .overflow_o ( alu_overflow_int ), // Internal signal .carry_o ( alu_carry_int ), // Internal signal - .flag_o ( alu_flag_o ) ); diff --git a/id_stage.sv b/id_stage.sv index ac412b08..d06a2f66 100644 --- a/id_stage.sv +++ b/id_stage.sv @@ -68,9 +68,6 @@ module id_stage output logic stall_ex_o, output logic stall_wb_o, - input logic sr_flag_fw_i, - input logic sr_flag_i, - // To the Pipeline ID/EX output logic [31:0] regfile_rb_data_ex_o, output logic [31:0] alu_operand_a_ex_o, @@ -119,7 +116,6 @@ module id_stage input logic data_rvalid_i, // SPR signals - output logic set_flag_ex_o, output logic set_carry_ex_o, output logic set_overflow_ex_o, @@ -267,7 +263,6 @@ module id_stage logic [1:0] csr_op; // Supervision Register - logic set_flag; logic set_carry; logic set_overflow; @@ -638,10 +633,6 @@ module id_stage .dbg_trap_o ( dbg_trap_o ), // SPR Signals - .sr_flag_fw_i ( sr_flag_fw_i ), // Forwarded Branch Signal - .sr_flag_i ( sr_flag_i ), - .set_flag_ex_i ( set_flag_ex_o ), - .set_flag_o ( set_flag ), .set_overflow_o ( set_overflow ), .set_carry_o ( set_carry ), .restore_sr_o ( restore_sr_o ), @@ -812,7 +803,6 @@ module id_stage data_misaligned_ex_o <= 1'b0; - set_flag_ex_o <= 1'b0; set_overflow_ex_o <= 1'b0; set_carry_ex_o <= 1'b0; @@ -885,7 +875,6 @@ module id_stage data_misaligned_ex_o <= 1'b0; - set_flag_ex_o <= set_flag; set_overflow_ex_o <= set_overflow; set_carry_ex_o <= set_carry; diff --git a/riscv_core.sv b/riscv_core.sv index 98f63e1f..27ae98ce 100644 --- a/riscv_core.sv +++ b/riscv_core.sv @@ -116,7 +116,6 @@ module riscv_core logic [31:0] alu_operand_a_ex; logic [31:0] alu_operand_b_ex; logic [31:0] alu_operand_c_ex; - logic alu_flag_ex; logic [1:0] vector_mode_ex; logic [1:0] alu_cmp_mode_ex; @@ -172,15 +171,12 @@ module riscv_core logic data_ack_int; // Supervision Register - logic set_flag_ex; logic set_carry_ex; logic set_overflow_ex; logic set_carry_fw_ex; logic set_overflow_fw_ex; // Direct Supervision-Register access - logic sr_flag; - logic sr_flag_fw; logic carry_sp; // Signals between instruction core interface and pipe (if and id stages) @@ -379,9 +375,6 @@ module riscv_core .compressed_instr_o ( compressed_instr ), - .sr_flag_fw_i ( sr_flag_fw ), - .sr_flag_i ( sr_flag ), - // STALLS .stall_if_o ( stall_if ), .stall_id_o ( stall_id ), @@ -437,7 +430,6 @@ module riscv_core .data_ack_i ( data_ack_int ), // from load store unit .data_rvalid_i ( data_r_valid_i ), - .set_flag_ex_o ( set_flag_ex ), // to ex_stage .set_carry_ex_o ( set_carry_ex ), // to ex_stage .set_overflow_ex_o ( set_overflow_ex ), // to ex_stage @@ -504,8 +496,6 @@ module riscv_core .alu_operand_b_i ( alu_operand_b_ex ), // from ID/EX pipe registers .alu_operand_c_i ( alu_operand_c_ex ), // from ID/EX pipe registers .alu_carry_i ( carry_sp ), // from spr carry - .alu_flag_i ( sr_flag ), // from spr flag - .alu_flag_o ( alu_flag_ex ), // to spr flag .vector_mode_i ( vector_mode_ex ), // from ID/EX pipe registers .alu_cmp_mode_i ( alu_cmp_mode_ex ), // from ID/EX pipe registers