diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 58077c39..b7cb121d 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -1,11 +1,19 @@ # Contributing -Contributors are encouraged to be a [member](https://www.openhwgroup.org/membership/) of the -OpenHW Group. New members are always welcome. +New Contributors and new Members are always welcome! +Although membership is not required, most Contributors are [members](https://openhwfoundation.org/membership/become-a-member/) +of the OpenHW Foundation and participate in one or more of our [Projects](https://openhwfoundation.org/projects/). + +## Contributor Agreement +Contributors **must** be covered by the terms of the [Eclipse Contributor Agreement](https://www.eclipse.org/legal/ECA.php) +(for individuals) **or** the [Eclipse Member Committer and Contributor Agreement](https://www.eclipse.org/legal/committer_process/EclipseMemberCommitterAgreement.pdf) +(for employees of Member companies). The ECA/MCCA provides a legal +framework for a Contributor's technical contributions to the OpenHW Foundation, +including provisions for grant of copyright license and a Developer +Certificate of Origin on contributions merged into OpenHW Foundation repositories. ## Getting Started -The [OpenHW Work Flow](https://github.com/openhwgroup/programs/blob/5fa810bf16d25cf32c7eca58be084975bec38f96/TGs/verification-task-group/documents/presentations/OpenHWGroup_WorkFlow.pdf) document -is required reading. You will find information about the implementation and usage of the CORE-V verification environments -in the [Verification Strategy](https://docs.openhwgroup.org/projects/core-v-verif/en/latest/index.html). +The [OpenHW Work Flow](https://github.com/openhwgroup/programs/blob/5fa810bf16d25cf32c7eca58be084975bec38f96/TGs/verification-task-group/documents/presentations/OpenHWGroup_WorkFlow.pdf) +document is recommended reading. ## The Mechanics 1. From GitHub: [fork](https://help.github.com/articles/fork-a-repo/) the [cve2](https://github.com/openhwgroup/cve2) repository @@ -13,6 +21,6 @@ in the [Verification Strategy](https://docs.openhwgroup.org/projects/core-v-veri 3. Create your feature branch: `git checkout -b .`
Please uniquify your branch name. See the [Git Cheats](https://github.com/openhwgroup/core-v-verif/blob/master/GitCheats.md) for a useful nominclature. 4. Make your edits... -5. Commit your changes: `git commit -m 'Add some feature' -s`
; `-s` or `--sign-off` is engouraged, but not required. +5. Commit your changes: `git commit -m 'Add some feature' -s` 6. Push feature branch: `git push origin ` 7. From GitHub: submit a pull request diff --git a/doc/02_user/integration.rst b/doc/02_user/integration.rst index ce53056f..29534a8a 100644 --- a/doc/02_user/integration.rst +++ b/doc/02_user/integration.rst @@ -63,6 +63,7 @@ Instantiation Template // Debug interface .debug_req_i (), + .debug_halted_o (), .dm_halt_addr_i (), .dm_exception_addr_i (), .crash_dump_o (), diff --git a/doc/03_reference/debug.rst b/doc/03_reference/debug.rst index e8d85d80..87123633 100644 --- a/doc/03_reference/debug.rst +++ b/doc/03_reference/debug.rst @@ -23,6 +23,8 @@ Interface +==================================+=====================+======================================================================================+ | ``debug_req_i`` | input | Request to enter Debug Mode | +----------------------------------+---------------------+--------------------------------------------------------------------------------------+ +| ``debug_halted_o`` | output | Asserted if core enters Debug Mode | ++----------------------------------+---------------------+--------------------------------------------------------------------------------------+ | ``dm_halt_addr_i`` | input | Address to jump to when entering Debug Mode (default 0x1A110800) | +----------------------------------+---------------------+--------------------------------------------------------------------------------------+ | ``dm_exception_addr_i`` | input | Address to jump to when an exception occurs while in Debug Mode (default 0x1A110808) | diff --git a/dv/riscv_compliance/rtl/cve2_riscv_compliance.sv b/dv/riscv_compliance/rtl/cve2_riscv_compliance.sv index 79b1e89e..2ff1f7f3 100644 --- a/dv/riscv_compliance/rtl/cve2_riscv_compliance.sv +++ b/dv/riscv_compliance/rtl/cve2_riscv_compliance.sv @@ -167,6 +167,7 @@ module cve2_riscv_compliance ( .scramble_req_o ( ), .debug_req_i ('b0 ), + .debug_halted_o ( ), .dm_halt_addr_i (32'h00000000 ), .dm_exception_addr_i (32'h00000000 ), .crash_dump_o ( ), diff --git a/rtl/cve2_core.sv b/rtl/cve2_core.sv index 3eaefafd..440cc368 100644 --- a/rtl/cve2_core.sv +++ b/rtl/cve2_core.sv @@ -62,6 +62,7 @@ module cve2_core import cve2_pkg::*; #( // Debug Interface input logic debug_req_i, + output logic debug_halted_o, input logic [31:0] dm_halt_addr_i, input logic [31:0] dm_exception_addr_i, output crash_dump_t crash_dump_o, @@ -611,6 +612,11 @@ module cve2_core import cve2_pkg::*; #( assign crash_dump_o.last_data_addr = lsu_addr_last; assign crash_dump_o.exception_addr = csr_mepc; + /////////////////////// + // Debug output // + /////////////////////// + + assign debug_halted_o = debug_mode; // Explict INC_ASSERT block to avoid unused signal lint warnings were asserts are not included `ifdef INC_ASSERT diff --git a/rtl/cve2_top.sv b/rtl/cve2_top.sv index 3c8c02be..d8c9b598 100644 --- a/rtl/cve2_top.sv +++ b/rtl/cve2_top.sv @@ -57,6 +57,7 @@ module cve2_top import cve2_pkg::*; #( // Debug Interface input logic debug_req_i, + output logic debug_halted_o, input logic [31:0] dm_halt_addr_i, input logic [31:0] dm_exception_addr_i, output crash_dump_t crash_dump_o, @@ -194,6 +195,7 @@ module cve2_top import cve2_pkg::*; #( .irq_pending_o(irq_pending), .debug_req_i, + .debug_halted_o, .dm_halt_addr_i, .dm_exception_addr_i, .crash_dump_o, diff --git a/rtl/cve2_top_tracing.sv b/rtl/cve2_top_tracing.sv index 56c330f3..1f7ca6de 100644 --- a/rtl/cve2_top_tracing.sv +++ b/rtl/cve2_top_tracing.sv @@ -52,6 +52,7 @@ module cve2_top_tracing import cve2_pkg::*; #( // Debug Interface input logic debug_req_i, + output logic debug_halted_o, input logic [31:0] dm_halt_addr_i, input logic [31:0] dm_exception_addr_i, output crash_dump_t crash_dump_o, @@ -146,6 +147,7 @@ module cve2_top_tracing import cve2_pkg::*; #( .irq_nm_i, .debug_req_i, + .debug_halted_o, .dm_halt_addr_i, .dm_exception_addr_i, .crash_dump_o,