diff --git a/dv/uvm/Makefile b/dv/uvm/Makefile
index 1d581fe4..1aaa314b 100644
--- a/dv/uvm/Makefile
+++ b/dv/uvm/Makefile
@@ -146,6 +146,7 @@ fcov:
           --core ibex \
           --dir ${OUT}/rtl_sim \
           -o ${OUT}/fcov \
+          --isa rv32imc \
           --custom_target ${DV_DIR}/riscv_dv_extension \
 
 # Load verdi to review coverage
diff --git a/dv/uvm/riscv_dv_extension/ibex_log_to_trace_csv.py b/dv/uvm/riscv_dv_extension/ibex_log_to_trace_csv.py
index 54fa136e..46bb9ae6 100644
--- a/dv/uvm/riscv_dv_extension/ibex_log_to_trace_csv.py
+++ b/dv/uvm/riscv_dv_extension/ibex_log_to_trace_csv.py
@@ -64,6 +64,7 @@ def process_ibex_sim_log(ibex_log, csv, full_trace = 1):
 
                 # Extract all missing operand values
                 if full_trace:
+                  gpr[rv_instr_trace.rd] = rv_instr_trace.rd_val
                   o = re.search(r"(?P<instr_name>[a-z.]*)\s+(?P<operands>.*)", rv_instr_trace.instr_str)
                   if o:
                     operands = o.group("operands").split(",")
@@ -85,7 +86,6 @@ def process_ibex_sim_log(ibex_log, csv, full_trace = 1):
                     else:
                       assign_operand(rv_instr_trace, operands, gpr)
 
-                gpr[rv_instr_trace.rd] = rv_instr_trace.rd_val
                 trace_csv.write_trace_entry(rv_instr_trace)
 
     logging.info("Processed instruction count : %d" % instr_cnt)