diff --git a/decoder.sv b/decoder.sv
index 2affd691..b7bafdb3 100644
--- a/decoder.sv
+++ b/decoder.sv
@@ -969,6 +969,8 @@ module riscv_decoder
       // if post increments are used, we must make sure that for
       // the second memory access we do use the adder
       prepost_useincr_o = 1'b1;
+      // we do not want to replicate operand_b
+      scalar_replication_o = 1'b0;
     end else if (mult_multicycle_i) begin
       alu_op_c_mux_sel_o = OP_C_REGC_OR_FWD;
     end