diff --git a/controller.sv b/controller.sv index b29cb0f7..c5cafe9f 100644 --- a/controller.sv +++ b/controller.sv @@ -64,7 +64,7 @@ module controller output logic mult_mac_en_o, // Use the accumulator after multiplication output logic regfile_we_o, // Write Enable to regfile - output logic [1:0] regfile_alu_waddr_mux_sel_o, // Select register write address for ALU/MUL operations + output logic regfile_alu_waddr_mux_sel_o, // Select register write address for ALU/MUL operations output logic regfile_alu_we_o, // Write Enable to regfile 2nd port @@ -163,23 +163,21 @@ module controller logic trap_insn; logic deassert_we; - logic lsu_stall; - logic misalign_stall; - logic instr_ack_stall; - logic load_stall; - logic jr_stall; - logic trap_stall; + logic lsu_stall; + logic misalign_stall; + logic instr_ack_stall; + logic load_stall; + logic jr_stall; + logic trap_stall; -`ifdef BRANCH_PREDICTION - logic wrong_branch_taken; -`endif - logic rega_used; - logic regb_used; - logic regc_used; + logic rega_used; + logic regb_used; + logic regc_used; + + logic halt_if; + logic halt_id; + logic illegal_insn_int; - logic halt_if; - logic halt_id; - logic illegal_insn_int; ///////////////////////////////////////////// // ____ _ // @@ -189,9 +187,9 @@ module controller // |____/ \___|\___\___/ \__,_|\___|_| // // // ///////////////////////////////////////////// + always_comb begin - // Default values jump_in_id = `BRANCH_NONE; alu_operator = `ALU_NOP; @@ -210,7 +208,7 @@ module controller regfile_we = 1'b0; regfile_alu_we = 1'b0; - regfile_alu_waddr_mux_sel_o = 2'b01; + regfile_alu_waddr_mux_sel_o = 1'b1; prepost_useincr_o = 1'b1; @@ -238,10 +236,6 @@ module controller regb_used = 1'b0; regc_used = 1'b0; -`ifdef BRANCH_PREDICTION - wrong_branch_taken_o = 1'b0; - take_branch_o = 1'b0; -`endif unique case (instr_rdata_i[6:0]) @@ -256,7 +250,6 @@ module controller `OPCODE_JAL: begin // Jump and Link if (instr_rdata_i ==? `INSTR_JAL) begin - // Insert bubbles jump_in_id = `BRANCH_JAL; // Calculate and store PC+4 alu_op_a_mux_sel_o = `OP_A_CURRPC; @@ -273,7 +266,6 @@ module controller `OPCODE_JALR: begin // Jump and Link Register if (instr_rdata_i ==? `INSTR_JALR) begin - // Insert bubbles jump_in_id = `BRANCH_JALR; // Calculate and store PC+4 alu_op_a_mux_sel_o = `OP_A_CURRPC; @@ -306,7 +298,7 @@ module controller default: begin illegal_insn_int = 1'b1; end - endcase // case (instr_rdata_i) + endcase end @@ -321,16 +313,16 @@ module controller `OPCODE_STORE, `OPCODE_STORE_POST: begin - data_req = 1'b1; - data_we = 1'b1; - rega_used = 1'b1; - regb_used = 1'b1; - alu_operator = `ALU_ADD; + data_req = 1'b1; + data_we = 1'b1; + rega_used = 1'b1; + regb_used = 1'b1; + alu_operator = `ALU_ADD; // post-increment setup if (instr_rdata_i[6:0] == `OPCODE_STORE_POST) begin prepost_useincr_o = 1'b0; - regfile_alu_waddr_mux_sel_o = 2'b00; + regfile_alu_waddr_mux_sel_o = 1'b0; regfile_alu_we = 1'b1; end @@ -359,20 +351,20 @@ module controller `OPCODE_LOAD, `OPCODE_LOAD_POST: begin - data_req = 1'b1; - regfile_we = 1'b1; - rega_used = 1'b1; - data_type_o = 2'b00; + data_req = 1'b1; + regfile_we = 1'b1; + rega_used = 1'b1; + data_type_o = 2'b00; // offset from immediate - alu_operator = `ALU_ADD; - alu_op_b_mux_sel_o = `OP_B_IMM; - immediate_mux_sel_o = `IMM_I; + alu_operator = `ALU_ADD; + alu_op_b_mux_sel_o = `OP_B_IMM; + immediate_mux_sel_o = `IMM_I; // post-increment setup if (instr_rdata_i[6:0] == `OPCODE_LOAD_POST) begin prepost_useincr_o = 1'b0; - regfile_alu_waddr_mux_sel_o = 2'b00; + regfile_alu_waddr_mux_sel_o = 1'b0; regfile_alu_we = 1'b1; end @@ -509,7 +501,7 @@ module controller regfile_alu_we = 1'b0; illegal_insn_int = 1'b1; end - endcase // unique case (instr_rdata_i) + endcase end /* @@ -523,34 +515,13 @@ module controller regfile_alu_we = 1'b1; casex (instr_rdata_i[3:0]) - 4'b0XXX: begin // Standard Operation - alu_operator = {3'b000, instr_rdata_i[2:0]}; - - if ((instr_rdata_i[2:0] ==? 3'b00X) || (instr_rdata_i[2:0] == 3'b010)) begin // l.add, l.addc & l.sub - set_overflow = 1'b1; - set_carry = 1'b1; - end - end - 4'b1000: begin // Shift Operation - alu_operator = {4'b0010, instr_rdata_i[7:6]}; - end 4'b110X: begin // l.ext{b,h,w}{s,z} alu_operator = {3'b010, instr_rdata_i[7:6], instr_rdata_i[0]}; regb_used = 1'b0; // register b is not used end - 4'b1110: begin // l.cmov - alu_operator = `ALU_CMOV; - end 4'b1111: begin // l.ff1 alu_operator = `ALU_FF1; end - default: begin - // synopsys translate_off - $display("%t: Illegal ALU instruction received.", $time); - // synopsys translate_on - regfile_alu_we = 1'b0; // disable Write Enable for illegal instruction - illegal_insn_int = 1'b1; - end endcase // casex (instr_rdata_i[3:2]) end @@ -598,26 +569,6 @@ module controller end endcase //~case(instr_rdata_i[3:0]) end - - 2'b11: begin // Multiplication - if ((instr_rdata_i[3:0] == 4'b0110) || (instr_rdata_i[3:0] == 4'b1011)) - begin // Is multiplication and no division - mult_is_running = 1'b1; - - if ((instr_rdata_i[3:0] == 4'b0110) || (instr_rdata_i[3:0] == 4'b1011)) // l.mul & l.mulu - begin - regfile_alu_we = 1'b1; - regfile_alu_waddr_mux_sel_o = 2'b01; - end - end - else - begin - // synopsys translate_off - $display("%t: Division instruction received, this is not supported.", $time); - // synopsys translate_on - illegal_insn_int = 1'b1; - end - end endcase; // case (instr_rdata_i[9:8]) end diff --git a/hwloop_regs.sv b/hwloop_regs.sv index 264a7e56..31c09359 100644 --- a/hwloop_regs.sv +++ b/hwloop_regs.sv @@ -10,7 +10,7 @@ // Create Date: 08/08/2014 // // Design Name: hwloop regs // // Module Name: hwloop_regs.sv // -// Project Name: OR10N // +// Project Name: RI5CY // // Language: SystemVerilog // // // // Description: Hardware loop registers // @@ -23,8 +23,6 @@ // // // // // // -// // -// // //////////////////////////////////////////////////////////////////////////////// @@ -55,9 +53,9 @@ module hwloop_regs ); - logic [`HWLOOP_REGS-1:0] [31:0] hwloop_start_regs_q; - logic [`HWLOOP_REGS-1:0] [31:0] hwloop_end_regs_q; - logic [`HWLOOP_REGS-1:0] [31:0] hwloop_counter_regs_q; + logic [`HWLOOP_REGS-1:0] [31:0] hwloop_start_regs_q; + logic [`HWLOOP_REGS-1:0] [31:0] hwloop_end_regs_q; + logic [`HWLOOP_REGS-1:0] [31:0] hwloop_counter_regs_q; int unsigned i; diff --git a/id_stage.sv b/id_stage.sv index 7ca27531..91c64030 100644 --- a/id_stage.sv +++ b/id_stage.sv @@ -149,8 +149,8 @@ module id_stage input logic [31:0] regfile_alu_wdata_fw_i, // Performance Counters - output logic perf_jump_o, // we are executing a jump instruction (j, jr, jal, jalr) - output logic perf_branch_o, // we are executing a branch instruction (bf, bnf) + output logic perf_jump_o, // we are executing a jump instruction + output logic perf_branch_o, // we are executing a branch instruction output logic perf_jr_stall_o, // jump-register-hazard output logic perf_ld_stall_o // load-use-hazard ); @@ -181,9 +181,6 @@ module id_stage logic irq_present; // Signals running between controller and exception controller - logic [1:0] jump_in_ex; // registered copy of jump_in_id - assign jump_in_ex_o = jump_in_ex; - logic illegal_insn; logic illegal_c_insn; logic trap_insn; @@ -192,7 +189,7 @@ module id_stage logic clear_isr_running; logic exc_pipe_flush; - + // Register file interface logic [4:0] regfile_addr_ra_id; logic [4:0] regfile_addr_rb_id; logic [4:0] regfile_addr_rc_id; @@ -226,7 +223,7 @@ module id_stage // Register Write Control logic regfile_we_id; - logic [1:0] regfile_alu_waddr_mux_sel; // TODO: FixMe -> 1bit + logic regfile_alu_waddr_mux_sel; // Data Memory Control logic data_we_id; @@ -302,14 +299,8 @@ module id_stage // Second Register Write Adress Selection // Used for prepost load/store and multiplier - always_comb - begin : alu_waddr_mux - case (regfile_alu_waddr_mux_sel) - default: regfile_alu_waddr_id = regfile_addr_ra_id; - 2'b00: regfile_alu_waddr_id = regfile_addr_ra_id; - 2'b01: regfile_alu_waddr_id = regfile_waddr_id; - endcase - end + assign regfile_alu_waddr_id = regfile_alu_waddr_mux_sel ? + regfile_waddr_id : regfile_addr_ra_id; /////////////////////////////////////////////////////////////////////////////////////// @@ -682,7 +673,7 @@ module id_stage // Controller .core_busy_i ( core_busy_o ), .jump_in_id_i ( jump_in_id_o ), - .jump_in_ex_i ( jump_in_ex ), + .jump_in_ex_i ( jump_in_ex_o ), .stall_id_i ( stall_id_o ), .illegal_insn_i ( illegal_insn ), .trap_insn_i ( trap_insn ), @@ -781,7 +772,7 @@ module id_stage hwloop_wb_mux_sel_ex_o <= 1'b0; hwloop_cnt_o <= 32'b0; - jump_in_ex <= 2'b0; + jump_in_ex_o <= 2'b0; end else if ((stall_ex_o == 1'b0) && (data_misaligned_i == 1'b1)) @@ -844,7 +835,7 @@ module id_stage hwloop_wb_mux_sel_ex_o <= hwloop_wb_mux_sel; hwloop_cnt_o <= hwloop_cnt; - jump_in_ex <= jump_in_id_o; + jump_in_ex_o <= jump_in_id_o; end end