diff --git a/dv/uvm/riscv_dv_extension/riscv_core_setting.sv b/dv/uvm/riscv_dv_extension/riscv_core_setting.sv
index 8a12f88e..b9787c36 100644
--- a/dv/uvm/riscv_dv_extension/riscv_core_setting.sv
+++ b/dv/uvm/riscv_dv_extension/riscv_core_setting.sv
@@ -31,6 +31,9 @@ privileged_mode_t supported_privileged_mode[] = {MACHINE_MODE, USER_MODE};
 // FENCE.I is intentionally treated as illegal instruction by ibex core
 riscv_instr_name_t unsupported_instr[] = {FENCE_I};
 
+// Specify whether processor supports unaligned loads and stores
+bit support_unaligned_load_store = 1'b1;
+
 // ISA supported by the processor
 riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV32C};