diff --git a/rtl/cve2_core.sv b/rtl/cve2_core.sv index 7c3e3196..63ab86ea 100644 --- a/rtl/cve2_core.sv +++ b/rtl/cve2_core.sv @@ -61,15 +61,15 @@ module cve2_core import cve2_pkg::*; #( input logic x_issue_ready_i, output x_issue_req_t x_issue_req_o, input x_issue_resp_t x_issue_resp_i, - - // Register Interface + + // Register Interface output x_register_t x_register_o, - - // Commit Interface + + // Commit Interface output logic x_commit_valid_o, output x_commit_t x_commit_o, - - // Result Interface + + // Result Interface input logic x_result_valid_i, output logic x_result_ready_o, input x_result_t x_result_i, diff --git a/rtl/cve2_decoder.sv b/rtl/cve2_decoder.sv index 13a70f9e..6ce18bb3 100644 --- a/rtl/cve2_decoder.sv +++ b/rtl/cve2_decoder.sv @@ -17,8 +17,7 @@ module cve2_decoder #( parameter bit RV32E = 0, parameter cve2_pkg::rv32m_e RV32M = cve2_pkg::RV32MFast, parameter cve2_pkg::rv32b_e RV32B = cve2_pkg::RV32BNone, - parameter bit XInterface = 1'b0, - parameter [31:0] CoprocOpcodes = '0 + parameter bit XInterface = 1'b0 ) ( input logic clk_i, input logic rst_ni, @@ -59,29 +58,29 @@ module cve2_decoder #( output logic [4:0] rf_waddr_o, output logic rf_ren_a_o, // Instruction reads from RF addr A output logic rf_ren_b_o, // Instruction reads from RF addr B - - // ALU + + // ALU output cve2_pkg::alu_op_e alu_operator_o, // ALU operation selection output cve2_pkg::op_a_sel_e alu_op_a_mux_sel_o, // operand a selection: reg value, PC, // immediate or zero output cve2_pkg::op_b_sel_e alu_op_b_mux_sel_o, // operand b selection: reg value or // immediate output logic alu_multicycle_o, // ternary bitmanip instruction - - // MULT & DIV + + // MULT & DIV output logic mult_en_o, // perform integer multiplication output logic div_en_o, // perform integer division or remainder output logic mult_sel_o, // as above but static, for data muxes output logic div_sel_o, // as above but static, for data muxes - + output cve2_pkg::md_op_e multdiv_operator_o, output logic [1:0] multdiv_signed_mode_o, - - // CSRs + + // CSRs output logic csr_access_o, // access to CSR output cve2_pkg::csr_op_e csr_op_o, // operation to perform on CSR - - // LSU + + // LSU output logic data_req_o, // start transaction to data memory output logic data_we_o, // write enable output logic [1:0] data_type_o, // size of transaction: byte, half @@ -206,7 +205,7 @@ module cve2_decoder #( always_comb begin jump_in_dec_o = 1'b0; jump_set_o = 1'b0; - branch_in_dec_o = 1'b0; + branch_in_dec_o = 1'b0; multdiv_operator_o = MD_OP_MULL; multdiv_signed_mode_o = 2'b00; @@ -641,9 +640,9 @@ module cve2_decoder #( // CV-X-IF if(XInterface) begin - rf_ren_a_o = x_issue_resp_register_read_i[0]; - rf_ren_b_o = x_issue_resp_register_read_i[1]; - rf_we = x_issue_resp_writeback_i; + rf_ren_a_o = x_issue_resp_register_read_i[0]; + rf_ren_b_o = x_issue_resp_register_read_i[1]; + rf_we = x_issue_resp_writeback_i; rf_wdata_sel_o = RF_WD_COPROC; end diff --git a/rtl/cve2_id_stage.sv b/rtl/cve2_id_stage.sv index 87c7c0df..cdda5de5 100644 --- a/rtl/cve2_id_stage.sv +++ b/rtl/cve2_id_stage.sv @@ -286,7 +286,7 @@ module cve2_id_stage #( // CV-X-IF if (XInterface) begin: gen_xif assign coproc_done = (x_issue_valid_o & x_issue_ready_i & ~x_issue_resp_i.writeback) | (x_result_valid_i & x_result_i.we); - + // Issue Interface assign x_issue_valid_o = instr_executing & illegal_insn_dec & (id_fsm_q == FIRST_CYCLE); assign x_issue_req_o.instr = instr_rdata_i; @@ -300,11 +300,11 @@ module cve2_id_stage #( assign x_commit_valid_o = 1'b1; assign x_commit_o.commit_kill = 1'b0; - // Result Interface + // Result Interface assign x_result_ready_o = 1'b1; assign illegal_insn_o = instr_valid_i & (illegal_csr_insn_i | (x_issue_valid_o & x_issue_ready_i & ~x_issue_resp_i.accept)); - end + end else begin: no_gen_xif logic unused_x_issue_ready; @@ -312,6 +312,8 @@ module cve2_id_stage #( logic unused_x_result_valid; x_result_t unused_x_result; + assign coproc_done = 1'b0; + // Issue Interface assign x_issue_valid_o = 1'b0; assign unused_x_issue_ready = x_issue_ready_i; @@ -497,7 +499,7 @@ module cve2_id_stage #( // Core-V eXtension Interface (CV-X-IF) .x_issue_resp_register_read_i(x_issue_resp_i.register_read), .x_issue_resp_writeback_i(x_issue_resp_i.writeback), - + // jump/branches .jump_in_dec_o (jump_in_dec), .branch_in_dec_o(branch_in_dec) @@ -755,7 +757,7 @@ module cve2_id_stage #( rf_we_raw = 1'b0; end illegal_insn_dec: begin - + // CV-X-IF if(XInterface) begin if(x_issue_valid_o && x_issue_ready_i) begin @@ -832,34 +834,34 @@ module cve2_id_stage #( // Used by ALU to access RS3 if ternary instruction. assign instr_first_cycle_id_o = instr_first_cycle; - assign multicycle_done = lsu_req_dec ? lsu_resp_valid_i : (illegal_insn_dec ? coproc_done : ex_valid_i); + assign multicycle_done = lsu_req_dec ? lsu_resp_valid_i : (illegal_insn_dec ? coproc_done : ex_valid_i); - assign data_req_allowed = instr_first_cycle; + assign data_req_allowed = instr_first_cycle; - // Without Writeback Stage always stall the first cycle of a load/store. - // Then stall until it is complete - assign stall_mem = instr_valid_i & (lsu_req_dec & (~lsu_resp_valid_i | instr_first_cycle)); + // Without Writeback Stage always stall the first cycle of a load/store. + // Then stall until it is complete + assign stall_mem = instr_valid_i & (lsu_req_dec & (~lsu_resp_valid_i | instr_first_cycle)); - // Without writeback stage any valid instruction that hasn't seen an error will execute - assign instr_executing_spec = instr_valid_i & ~instr_fetch_err_i & controller_run; - assign instr_executing = instr_executing_spec; + // Without writeback stage any valid instruction that hasn't seen an error will execute + assign instr_executing_spec = instr_valid_i & ~instr_fetch_err_i & controller_run; + assign instr_executing = instr_executing_spec; - `ASSERT(IbexStallIfValidInstrNotExecuting, - instr_valid_i & ~instr_fetch_err_i & ~instr_executing & controller_run |-> stall_id) + `ASSERT(IbexStallIfValidInstrNotExecuting, + instr_valid_i & ~instr_fetch_err_i & ~instr_executing & controller_run |-> stall_id) - // No data forwarding without writeback stage so always take source register data direct from - // register file - assign rf_rdata_a_fwd = rf_rdata_a_i; - assign rf_rdata_b_fwd = rf_rdata_b_i; + // No data forwarding without writeback stage so always take source register data direct from + // register file + assign rf_rdata_a_fwd = rf_rdata_a_i; + assign rf_rdata_b_fwd = rf_rdata_b_i; - // Unused Writeback stage only IO & wiring - // Assign inputs and internal wiring to unused signals to satisfy lint checks - // Tie-off outputs to constant values - logic unused_data_req_done_ex; + // Unused Writeback stage only IO & wiring + // Assign inputs and internal wiring to unused signals to satisfy lint checks + // Tie-off outputs to constant values + logic unused_data_req_done_ex; - assign perf_dside_wait_o = instr_executing & lsu_req_dec & ~lsu_resp_valid_i; + assign perf_dside_wait_o = instr_executing & lsu_req_dec & ~lsu_resp_valid_i; - assign instr_id_done_o = instr_done; + assign instr_id_done_o = instr_done; // Signal which instructions to count as retired in minstret, all traps along with ebrk and // ecall instructions are not counted. diff --git a/rtl/cve2_pkg.sv b/rtl/cve2_pkg.sv index 4fb29705..769eeae1 100644 --- a/rtl/cve2_pkg.sv +++ b/rtl/cve2_pkg.sv @@ -692,7 +692,7 @@ package cve2_pkg; // Commit Interface typedef struct packed { - hartid_t hartid; + hartid_t hartid; id_t id; logic commit_kill; } x_commit_t; diff --git a/rtl/cve2_top.sv b/rtl/cve2_top.sv index 12c0baf2..c41d1d9b 100644 --- a/rtl/cve2_top.sv +++ b/rtl/cve2_top.sv @@ -18,7 +18,8 @@ module cve2_top import cve2_pkg::*; #( parameter bit RV32E = 1'b0, parameter rv32m_e RV32M = RV32MFast, parameter int unsigned DmHaltAddr = 32'h1A110800, - parameter int unsigned DmExceptionAddr = 32'h1A110808 + parameter int unsigned DmExceptionAddr = 32'h1A110808, + parameter bit XInterface = 1'b0 ) ( // Clock and Reset input logic clk_i, @@ -55,15 +56,15 @@ module cve2_top import cve2_pkg::*; #( input logic x_issue_ready_i, output x_issue_req_t x_issue_req_o, input x_issue_resp_t x_issue_resp_i, - - // Register Interface + + // Register Interface output x_register_t x_register_o, - - // Commit Interface + + // Commit Interface output logic x_commit_valid_o, output x_commit_t x_commit_o, - - // Result Interface + + // Result Interface input logic x_result_valid_i, output logic x_result_ready_o, input x_result_t x_result_i, @@ -132,9 +133,6 @@ module cve2_top import cve2_pkg::*; #( // Bit manipulation extension localparam rv32b_e RV32B = RV32BNone; - // CV-X-IF - localparam int unsigned XInterface = 0; - // Clock signals logic clk; logic core_busy_d, core_busy_q; @@ -307,7 +305,6 @@ module cve2_top import cve2_pkg::*; #( `ASSERT_KNOWN(IbexDataGntX, data_gnt_i) `ASSERT_KNOWN(IbexDataRValidX, data_rvalid_i) - `ASSERT_KNOWN_IF(IbexDataRPayloadX, {data_rdata_i, data_err_i}, data_rvalid_i) `ASSERT_KNOWN(IbexIrqX, {irq_software_i, irq_timer_i, irq_external_i, irq_fast_i, irq_nm_i}) diff --git a/rtl/cve2_top_tracing.sv b/rtl/cve2_top_tracing.sv index 1a3aca25..f3a72876 100644 --- a/rtl/cve2_top_tracing.sv +++ b/rtl/cve2_top_tracing.sv @@ -50,15 +50,15 @@ module cve2_top_tracing import cve2_pkg::*; #( input logic x_issue_ready_i, output x_issue_req_t x_issue_req_o, input x_issue_resp_t x_issue_resp_i, - - // Register Interface + + // Register Interface output x_register_t x_register_o, - - // Commit Interface + + // Commit Interface output logic x_commit_valid_o, output x_commit_t x_commit_o, - - // Result Interface + + // Result Interface input logic x_result_valid_i, output logic x_result_ready_o, input x_result_t x_result_i, @@ -177,7 +177,7 @@ module cve2_top_tracing import cve2_pkg::*; #( .x_result_valid_i, .x_result_ready_o, .x_result_i, - + .irq_software_i, .irq_timer_i, .irq_external_i,