diff --git a/dv/uvm/Makefile b/dv/uvm/Makefile
index 0de602d3..aaba01b5 100644
--- a/dv/uvm/Makefile
+++ b/dv/uvm/Makefile
@@ -72,7 +72,7 @@ compile:
       -Mdir=${OUT}/rtl_sim/vcs_simv.csrc \
       -o ${OUT}/rtl_sim/vcs_simv \
       +define+BOOT_ADDR=32\'h8000_0000 \
-      +define+TRACE_EXECUTION \
+      +define+TRACE_EXECUTION +define+RVFI\
       -debug_access+pp \
       ${WAVE_CMP_OPTS} ${COV_CMP_OPTS}\
       -lca -kdb
diff --git a/dv/uvm/ibex_dv.f b/dv/uvm/ibex_dv.f
index 7c55d045..030e6f17 100644
--- a/dv/uvm/ibex_dv.f
+++ b/dv/uvm/ibex_dv.f
@@ -25,6 +25,7 @@ ${PRJ_DIR}/ibex/rtl/ibex_prefetch_buffer.sv
 ${PRJ_DIR}/ibex/rtl/ibex_fetch_fifo.sv
 ${PRJ_DIR}/ibex/rtl/ibex_register_file_ff.sv
 ${PRJ_DIR}/ibex/rtl/ibex_core.sv
+${PRJ_DIR}/ibex/rtl/ibex_core_tracer.sv
 
 // Core DV files
 +incdir+${PRJ_DIR}/ibex/dv/uvm/env
diff --git a/dv/uvm/sim b/dv/uvm/sim
index 73034e5a..5d10bc59 100755
--- a/dv/uvm/sim
+++ b/dv/uvm/sim
@@ -90,7 +90,7 @@ while read asm_test; do
   fi
   CMD="$OUT/vcs_simv +UVM_TESTNAME=core_ibex_base_test \
        ${WAVES_OPTS} +ntb_random_seed=${SEED} +vcs+lic+wait ${COV_OPTS}\
-       +bin=$BINFILE -l sim.log"
+       +UVM_MAX_QUIT_COUNT=5 +bin=$BINFILE -l sim.log"
   echo "Running simulation for : $CMD"
   $CMD
 done <"$RUN_DIR/asm_test_list"
diff --git a/dv/uvm/tb/core_ibex_tb_top.sv b/dv/uvm/tb/core_ibex_tb_top.sv
index 58762b71..535c3f33 100644
--- a/dv/uvm/tb/core_ibex_tb_top.sv
+++ b/dv/uvm/tb/core_ibex_tb_top.sv
@@ -13,7 +13,7 @@ module core_ibex_tb_top;
   clk_if ibex_clk_if(.clk(clk));
 
   // TODO(taliu) Resolve the tied-off ports
-  ibex_core dut(
+  ibex_core_tracer dut(
     .clk_i(clk),
     .rst_ni(rst_n),
     .test_en_i(1'b1),
@@ -63,7 +63,7 @@ module core_ibex_tb_top;
 
   // DUT probe interface
   core_ibex_dut_probe_if dut_if(.clk(clk));
-  assign dut_if.ecall = dut.id_stage_i.ecall_insn_dec;
+  assign dut_if.ecall = dut.u_ibex_core.id_stage_i.ecall_insn_dec;
   assign fetch_enable = dut_if.fetch_enable;
   assign dut_if.debug_req = dut.debug_req_i;