diff --git a/dv/cs_registers/tb/tb_cs_registers.sv b/dv/cs_registers/tb/tb_cs_registers.sv
index ef4dd7d4..9a9fd2a3 100644
--- a/dv/cs_registers/tb/tb_cs_registers.sv
+++ b/dv/cs_registers/tb/tb_cs_registers.sv
@@ -14,9 +14,9 @@ module tb_cs_registers #(
     parameter ibex_pkg::rv32m_e RV32M            = ibex_pkg::RV32MFast
 ) (
     // Clock and Reset
-    inout  wire                 clk_i,
-    inout  wire                 in_rst_ni,
-    output wire                 test_passed_o
+    inout  logic                clk_i,
+    inout  logic                in_rst_ni,
+    output logic                test_passed_o
 );
 
   logic                 dpi_rst_ni;
diff --git a/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv b/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv
index b5fcfc2d..44d1044a 100644
--- a/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv
+++ b/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv
@@ -34,13 +34,13 @@ module ibex_riscv_compliance (
   assign rst_sys_n = IO_RST_N;
 
   // Bus hosts, ordered in decreasing priority
-  typedef enum {
+  typedef enum logic[1:0] {
     TestUtilHost,
     CoreD,
     CoreI
   } bus_host_e;
 
-  typedef enum {
+  typedef enum logic {
     Ram,
     TestUtilDevice
   } bus_device_e;
diff --git a/dv/riscv_compliance/rtl/riscv_testutil.sv b/dv/riscv_compliance/rtl/riscv_testutil.sv
index f2cbc6fc..ce043c60 100644
--- a/dv/riscv_compliance/rtl/riscv_testutil.sv
+++ b/dv/riscv_compliance/rtl/riscv_testutil.sv
@@ -72,6 +72,7 @@ module riscv_testutil (
         ADDR_SET_END_SIGNATURE: begin
           end_signature_addr_d = dev_wdata_i;
         end
+        default: ;
       endcase
     end
   end
@@ -144,6 +145,8 @@ module riscv_testutil (
         $display("Terminating simulation by software request.");
         $finish;
       end
+
+      default: ;
     endcase
   end
 
diff --git a/dv/uvm/icache/dv/ibex_icache_core_agent/ibex_icache_core_if.sv b/dv/uvm/icache/dv/ibex_icache_core_agent/ibex_icache_core_if.sv
index 3bf8a625..d41e0faa 100644
--- a/dv/uvm/icache/dv/ibex_icache_core_agent/ibex_icache_core_if.sv
+++ b/dv/uvm/icache/dv/ibex_icache_core_agent/ibex_icache_core_if.sv
@@ -148,7 +148,7 @@ interface ibex_icache_core_if (input clk, input rst_n);
   cover property (cancelled_valid);
 
   bit cancelled_valid_trig = 0;
-  function void cover_cancelled_valid();
+  function automatic void cover_cancelled_valid();
     cancelled_valid_trig = ~cancelled_valid_trig;
   endfunction
 
diff --git a/examples/simple_system/rtl/ibex_simple_system.sv b/examples/simple_system/rtl/ibex_simple_system.sv
index abe37791..3d48a08f 100644
--- a/examples/simple_system/rtl/ibex_simple_system.sv
+++ b/examples/simple_system/rtl/ibex_simple_system.sv
@@ -50,11 +50,11 @@ module ibex_simple_system (
 
   logic clk_sys = 1'b0, rst_sys_n;
 
-  typedef enum {
+  typedef enum logic {
     CoreD
   } bus_host_e;
 
-  typedef enum {
+  typedef enum logic[1:0] {
     Ram,
     SimCtrl,
     Timer
@@ -117,7 +117,7 @@ module ibex_simple_system (
       #8
       rst_sys_n = 1'b1;
     end
-    always begin
+    always_comb begin
       #1 clk_sys = 1'b0;
       #1 clk_sys = 1'b1;
     end