diff --git a/lint/verilator_waiver.vlt b/lint/verilator_waiver.vlt
index 3ff0b2bd..7dd76ebe 100644
--- a/lint/verilator_waiver.vlt
+++ b/lint/verilator_waiver.vlt
@@ -25,7 +25,7 @@ lint_off -msg UNUSED -file "*/rtl/ibex_if_stage.sv" -lines 40
 
 // Bits of signal are not used: fetch_addr_n[0]
 // cleaner to write all bits even if not all are used
-lint_off -msg UNUSED -file "*/rtl/ibex_if_stage.sv" -lines 80
+lint_off -msg UNUSED -file "*/rtl/ibex_if_stage.sv" -lines 83
 
 // Bits of signal are not used: shift_right_result_ext[32]
 // cleaner to write all bits even if not all are used
@@ -33,15 +33,15 @@ lint_off -msg UNUSED -file "*/rtl/ibex_alu.sv" -lines 104
 
 // Bits of signal are not used: alu_adder_ext_i[0]
 // Bottom bit is round, not needed
-lint_off -msg UNUSED -file "*/rtl/ibex_multdiv_fast.sv" -lines 23
+lint_off -msg UNUSED -file "*/rtl/ibex_multdiv_fast.sv" -lines 26
 
 // Bits of signal are not used: mac_res_ext[34]
 // cleaner to write all bits even if not all are used
-lint_off -msg UNUSED -file "*/rtl/ibex_multdiv_fast.sv" -lines 48
+lint_off -msg UNUSED -file "*/rtl/ibex_multdiv_fast.sv" -lines 51
 
 // Bits of signal are not used: res_adder_h[32]
 // cleaner to write all bits even if not all are used
-lint_off -msg UNUSED -file "*/rtl/ibex_multdiv_fast.sv" -lines 68
+lint_off -msg UNUSED -file "*/rtl/ibex_multdiv_fast.sv" -lines 71
 
 // Signal is not used: test_en_i
 // testability signal
@@ -51,17 +51,17 @@ lint_off -msg UNUSED -file "*/rtl/ibex_register_file_fpga.sv" -lines 22
 // Signal is not used: clk_i
 // leaving clk and reset connected in-case we want to add assertions
 lint_off -msg UNUSED -file "*/rtl/ibex_pmp.sv" -lines 15
-lint_off -msg UNUSED -file "*/rtl/ibex_compressed_decoder.sv" -lines 14
-lint_off -msg UNUSED -file "*/rtl/ibex_decoder.sv" -lines 21
+lint_off -msg UNUSED -file "*/rtl/ibex_compressed_decoder.sv" -lines 17
+lint_off -msg UNUSED -file "*/rtl/ibex_decoder.sv" -lines 24
 
 // Signal is not used: rst_ni
 // leaving clk and reset connected in-case we want to add assertions
-lint_off -msg UNUSED -file "*/rtl/ibex_pmp.sv" -lines 16
-lint_off -msg UNUSED -file "*/rtl/ibex_compressed_decoder.sv" -lines 15
-lint_off -msg UNUSED -file "*/rtl/ibex_decoder.sv" -lines 22
+lint_off -msg UNUSED -file "*/rtl/ibex_pmp.sv" -lines 19
+lint_off -msg UNUSED -file "*/rtl/ibex_compressed_decoder.sv" -lines 18
+lint_off -msg UNUSED -file "*/rtl/ibex_decoder.sv" -lines 25
 lint_off -msg UNUSED -file "*/rtl/ibex_register_file_fpga.sv" -lines 20
 
 // Signal unoptimizable: Feedback to clock or circular logic:
 // ibex_core.cs_registers_i.mie_q
 // Issue lowrisc/ibex#212
-lint_off -msg UNOPTFLAT -file "*/rtl/ibex_cs_registers.sv" -lines 167
+lint_off -msg UNOPTFLAT -file "*/rtl/ibex_cs_registers.sv" -lines 170
diff --git a/rtl/ibex_compressed_decoder.sv b/rtl/ibex_compressed_decoder.sv
index 52c3a54b..442b5791 100644
--- a/rtl/ibex_compressed_decoder.sv
+++ b/rtl/ibex_compressed_decoder.sv
@@ -10,6 +10,9 @@
  * This module is fully combinatorial, clock and reset are used for
  * assertions only.
  */
+
+`include "prim_assert.sv"
+
 module ibex_compressed_decoder (
     input  logic        clk_i,
     input  logic        rst_ni,
diff --git a/rtl/ibex_controller.sv b/rtl/ibex_controller.sv
index e1172c65..74e4cf2e 100644
--- a/rtl/ibex_controller.sv
+++ b/rtl/ibex_controller.sv
@@ -6,6 +6,9 @@
 /**
  * Main controller of the processor
  */
+
+`include "prim_assert.sv"
+
 module ibex_controller (
     input  logic                  clk_i,
     input  logic                  rst_ni,
diff --git a/rtl/ibex_cs_registers.sv b/rtl/ibex_cs_registers.sv
index 2f6f4761..c7e074d2 100644
--- a/rtl/ibex_cs_registers.sv
+++ b/rtl/ibex_cs_registers.sv
@@ -9,6 +9,9 @@
  * Control and Status Registers (CSRs) following the RISC-V Privileged
  * Specification, draft version 1.11
  */
+
+`include "prim_assert.sv"
+
 module ibex_cs_registers #(
     parameter bit          DbgTriggerEn     = 0,
     parameter int unsigned MHPMCounterNum   = 8,
diff --git a/rtl/ibex_decoder.sv b/rtl/ibex_decoder.sv
index f28017c3..18e45e45 100644
--- a/rtl/ibex_decoder.sv
+++ b/rtl/ibex_decoder.sv
@@ -14,6 +14,9 @@
  * This module is fully combinatorial, clock and reset are used for
  * assertions only.
  */
+
+`include "prim_assert.sv"
+
 module ibex_decoder #(
     parameter bit RV32E = 0,
     parameter bit RV32M = 1
diff --git a/rtl/ibex_fetch_fifo.sv b/rtl/ibex_fetch_fifo.sv
index dacfe059..1839d599 100644
--- a/rtl/ibex_fetch_fifo.sv
+++ b/rtl/ibex_fetch_fifo.sv
@@ -9,6 +9,9 @@
  * input port: send address and data to the FIFO
  * clear_i clears the FIFO for the following cycle, including any new request
  */
+
+`include "prim_assert.sv"
+
 module ibex_fetch_fifo #(
   parameter int unsigned NUM_REQS = 2
 ) (
diff --git a/rtl/ibex_id_stage.sv b/rtl/ibex_id_stage.sv
index c06028fb..e6b67ab9 100644
--- a/rtl/ibex_id_stage.sv
+++ b/rtl/ibex_id_stage.sv
@@ -13,6 +13,9 @@
  * Decode stage of the core. It decodes the instructions and hosts the register
  * file.
  */
+
+`include "prim_assert.sv"
+
 module ibex_id_stage #(
     parameter bit RV32E = 0,
     parameter bit RV32M = 1
diff --git a/rtl/ibex_if_stage.sv b/rtl/ibex_if_stage.sv
index 07c5f928..ff811758 100644
--- a/rtl/ibex_if_stage.sv
+++ b/rtl/ibex_if_stage.sv
@@ -9,6 +9,9 @@
  * Instruction fetch unit: Selection of the next PC, and buffering (sampling) of
  * the read instruction.
  */
+
+`include "prim_assert.sv"
+
 module ibex_if_stage #(
     parameter int unsigned DmHaltAddr      = 32'h1A110800,
     parameter int unsigned DmExceptionAddr = 32'h1A110808
diff --git a/rtl/ibex_load_store_unit.sv b/rtl/ibex_load_store_unit.sv
index a1f2e44d..e9fd74bc 100644
--- a/rtl/ibex_load_store_unit.sv
+++ b/rtl/ibex_load_store_unit.sv
@@ -9,6 +9,9 @@
  * Load Store Unit, used to eliminate multiple access during processor stalls,
  * and to align bytes and halfwords.
  */
+
+`include "prim_assert.sv"
+
 module ibex_load_store_unit (
     input  logic         clk_i,
     input  logic         rst_ni,
diff --git a/rtl/ibex_multdiv_fast.sv b/rtl/ibex_multdiv_fast.sv
index 6f18d124..5fbbf09f 100644
--- a/rtl/ibex_multdiv_fast.sv
+++ b/rtl/ibex_multdiv_fast.sv
@@ -11,6 +11,9 @@
  *
  * 16x16 kernel multiplier and Long Division
  */
+
+`include "prim_assert.sv"
+
 module ibex_multdiv_fast (
     input  logic             clk_i,
     input  logic             rst_ni,
diff --git a/rtl/ibex_multdiv_slow.sv b/rtl/ibex_multdiv_slow.sv
index e5cf71cd..95f17e46 100644
--- a/rtl/ibex_multdiv_slow.sv
+++ b/rtl/ibex_multdiv_slow.sv
@@ -8,6 +8,9 @@
  *
  * Baugh-Wooley multiplier and Long Division
  */
+
+`include "prim_assert.sv"
+
 module ibex_multdiv_slow (
     input  logic             clk_i,
     input  logic             rst_ni,
diff --git a/shared/prim_assert.core b/shared/prim_assert.core
index 5ded010f..b5ba5c40 100644
--- a/shared/prim_assert.core
+++ b/shared/prim_assert.core
@@ -8,7 +8,7 @@ description: "Assertion primitives"
 filesets:
   files_rtl:
     files:
-      - rtl/prim_assert.sv
+      - rtl/prim_assert.sv : {is_include_file : true}
     file_type: systemVerilogSource
 
 targets:
diff --git a/shared/rtl/prim_assert.sv b/shared/rtl/prim_assert.sv
index 8234d61f..588a4321 100644
--- a/shared/rtl/prim_assert.sv
+++ b/shared/rtl/prim_assert.sv
@@ -6,6 +6,9 @@
 //  - Provides default clk and rst options to simplify code
 //  - Provides boiler plate template for common assertions
 
+`ifndef PRIM_ASSERT_SV
+`define PRIM_ASSERT_SV
+
 `ifdef UVM
   // report assertion error with UVM if compiled
   package assert_rpt_pkg;
@@ -172,3 +175,5 @@
 `ifdef FPV_ON                                    \
    `COVER(__name, __prop, __clk, __rst)          \
 `endif
+
+`endif // PRIM_ASSERT_SV
diff --git a/shared/rtl/timer.sv b/shared/rtl/timer.sv
index c4f9fcaf..f6b754f3 100644
--- a/shared/rtl/timer.sv
+++ b/shared/rtl/timer.sv
@@ -3,6 +3,9 @@
 // SPDX-License-Identifier: Apache-2.0
 
 // Example memory mapped timer
+
+`include "prim_assert.sv"
+
 module timer #(
   // Bus data width (must be 32)
   parameter int unsigned DataWidth    = 32,