diff --git a/doc/01_specification/index.rst b/doc/01_specification/index.rst
index 4c113a5a..3c1ebe40 100644
--- a/doc/01_specification/index.rst
+++ b/doc/01_specification/index.rst
@@ -247,8 +247,8 @@ Operating modes (Privilege Levels)
 +--------+--------------------------------------------------------------+
 | PVL-30 | CV32E20 shall export the CPU's operating mode as an address  |
 |        | phase attribute output signals on the Harvard memory         |
-|        | interfaces (instruction fetch, data load/store) with machine |
-|        | mode defined as 1'b1 and user mode as 1'b0.                  |
+|        | interfaces (instruction fetch, data load/store) with mode    |
+|        | encoded as per specification in [RVpriv]_.                   |
 +--------+--------------------------------------------------------------+
 | PVL-40 | CV32E20 shall support the **bare** (addressing) mode, that   |
 |        | is, no support for address translation or protection.        |
diff --git a/rtl/cve2_core.sv b/rtl/cve2_core.sv
index c62eb448..95b55899 100644
--- a/rtl/cve2_core.sv
+++ b/rtl/cve2_core.sv
@@ -124,7 +124,9 @@ module cve2_core import cve2_pkg::*; #(
 
   // CPU Control Signals
   input  logic                         fetch_enable_i,
-  output logic                         core_busy_o
+  output logic                         core_busy_o,
+  priv_lvl_e                           priv_mode_o,
+  priv_lvl_e                           priv_eff_mode_o
 );
 
   localparam int unsigned PMP_NUM_CHAN      = 3;
@@ -301,6 +303,9 @@ module cve2_core import cve2_pkg::*; #(
   // interfaces to finish ongoing operations.
   assign core_busy_o = ctrl_busy | if_busy | lsu_busy;
 
+  assign priv_mode_o = priv_mode_id;
+  assign priv_eff_mode_o = priv_mode_lsu;
+
   //////////////
   // IF stage //
   //////////////
diff --git a/rtl/cve2_top.sv b/rtl/cve2_top.sv
index 5f240695..e44c6a36 100644
--- a/rtl/cve2_top.sv
+++ b/rtl/cve2_top.sv
@@ -117,7 +117,9 @@ module cve2_top import cve2_pkg::*; #(
 
   // CPU Control Signals
   input  logic                         fetch_enable_i,
-  output logic                         core_sleep_o
+  output logic                         core_sleep_o,
+  priv_lvl_e                           priv_mode_o,
+  priv_lvl_e                           priv_eff_mode_o
 );
 
   // Scrambling Parameter
@@ -271,7 +273,9 @@ module cve2_top import cve2_pkg::*; #(
 `endif
 
     .fetch_enable_i (fetch_enable_q),
-    .core_busy_o    (core_busy_d)
+    .core_busy_o    (core_busy_d),
+    .priv_mode_o,
+    .priv_eff_mode_o
   );
 
   ////////////////////////