diff --git a/examples/fpga/artya7/top_artya7.core b/examples/fpga/artya7/top_artya7.core
index cfa1a330..811fb93c 100644
--- a/examples/fpga/artya7/top_artya7.core
+++ b/examples/fpga/artya7/top_artya7.core
@@ -31,12 +31,6 @@ parameters:
     default: "../../../../../examples/sw/led/led.vmem"
     paramtype: vlogparam
 
-  FPGA_XILINX:
-    datatype: str
-    description: Identifies Xilinx FPGA targets to set DSP pragmas for performance counters.
-    default: 1
-    paramtype: vlogdefine
-
   # For value definition, please see ip/prim/rtl/prim_pkg.sv
   PRIM_DEFAULT_IMPL:
     datatype: str
@@ -52,7 +46,6 @@ targets:
     toplevel: top_artya7
     parameters:
       - SRAMInitFile
-      - FPGA_XILINX
       - PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx
     tools:
       vivado:
diff --git a/ibex_core.core b/ibex_core.core
index dce96f4b..836b2744 100644
--- a/ibex_core.core
+++ b/ibex_core.core
@@ -60,6 +60,12 @@ parameters:
     datatype: bool
     paramtype: vlogdefine
 
+  FPGA_XILINX:
+    datatype: bool
+    description: Identifies Xilinx FPGA targets to set DSP pragmas for performance counters.
+    default: false
+    paramtype: vlogdefine
+
   RV32E:
     datatype: int
     default: 0
@@ -138,6 +144,8 @@ targets:
       - files_rtl
       - files_check_tool_requirements
     toplevel: ibex_core
+    parameters:
+      - tool_vivado ? (FPGA_XILINX=true)
   lint:
     <<: *default_target
     parameters: