diff --git a/if_stage.sv b/if_stage.sv
index f36b45a3..fb19bff4 100644
--- a/if_stage.sv
+++ b/if_stage.sv
@@ -378,7 +378,7 @@ module if_stage
   always_comb
   begin
     unique case (pc_mux_sel_i)
-      `PC_NO_INCR:   next_pc = current_pc_if_o;    // PC is not incremented
+      `PC_JUMP:      next_pc = (branch_decision_i? jump_target_i : incr_pc);
       `PC_INCR:      next_pc = incr_pc;            // incremented PC
       `PC_EXCEPTION: next_pc = exc_pc;             // set PC to exception handler
       `PC_ERET:      next_pc = exception_pc_reg_i; // PC is restored when returning from IRQ/exception
@@ -415,9 +415,10 @@ module if_stage
     .rst_n          ( rst_n          ),
 
     .req_i          ( req_int        ),
-    .ack_o          ( fetch_ack      ),
+    .valid_o        ( fetch_ack      ),
     .addr_i         ( fetch_addr     ),
     .rdata_o        ( rdata_int      ),
+    .last_addr_o    ( last_fetch_addr ),
 
     .instr_req_o    ( instr_req_o    ),
     .instr_addr_o   ( instr_addr_o   ),
@@ -425,13 +426,15 @@ module if_stage
     .instr_rvalid_i ( instr_rvalid_i ),
     .instr_rdata_i  ( instr_rdata_i  ),
 
-    .last_addr_o    ( last_fetch_addr ),
-
-    .stall_if_i     ( stall_if_i     ),
-
-    .drop_request_i ( drop_request_i )
+    .stall_if_i     ( 1'b0 ),
+    .drop_request_i ( 1'b0 )   // TODO: Remove?
   );
 
+  always_comb
+  begin
+    
+  end
+
 
   // IF PC register
   always_ff @(posedge clk, negedge rst_n)
diff --git a/instr_core_interface.sv b/instr_core_interface.sv
index c68bfaaf..3daa5035 100644
--- a/instr_core_interface.sv
+++ b/instr_core_interface.sv
@@ -31,8 +31,9 @@ module instr_core_interface
 
   input  logic        req_i,
   input  logic [31:0] addr_i,
-  output logic        ack_o,
+  output logic        valid_o,
   output logic [31:0] rdata_o,
+  output logic [31:0] last_addr_o,
 
   output logic        instr_req_o,
   output logic [31:0] instr_addr_o,
@@ -40,8 +41,6 @@ module instr_core_interface
   input  logic        instr_rvalid_i,
   input  logic [31:0] instr_rdata_i,
 
-  output logic [31:0] last_addr_o,
-
   input  logic        stall_if_i,
 
   input  logic        drop_request_i
@@ -85,7 +84,7 @@ module instr_core_interface
   always_comb
   begin
     instr_req_o   = 1'b0;
-    ack_o         = 1'b0;
+    valid_o         = 1'b0;
     save_rdata    = 1'b0;
     rdata_o       = instr_rdata_i;
     instr_addr_o  = addr_i;
@@ -95,7 +94,7 @@ module instr_core_interface
       IDLE:
       begin
         instr_req_o = req_i;
-        ack_o       = 1'b0;
+        valid_o       = 1'b0;
         rdata_o     = rdata_Q;
 
         if(req_i)
@@ -133,7 +132,7 @@ module instr_core_interface
       begin
         if (instr_rvalid_i) begin
           save_rdata = 1'b1;
-          ack_o = 1'b1;
+          valid_o = 1'b1;
 
           if (stall_if_i) begin
             NS          = WAIT_IF_STALL;
@@ -154,18 +153,18 @@ module instr_core_interface
         end else begin
           NS          = WAIT_RVALID;
           instr_req_o = 1'b0;
-          ack_o       = 1'b0;
+          valid_o       = 1'b0;
         end
       end // case: PENDING
 
       WAIT_RVALID :
       begin
         NS          = WAIT_RVALID;
-        ack_o       = 1'b0;
+        valid_o       = 1'b0;
         instr_req_o = 1'b0;
 
         if (instr_rvalid_i) begin
-          ack_o       = 1'b1;
+          valid_o       = 1'b1;
           save_rdata  = 1'b1;
 
           if (stall_if_i) begin
@@ -188,7 +187,7 @@ module instr_core_interface
 
       WAIT_IF_STALL:
       begin
-        ack_o   = 1'b1;
+        valid_o   = 1'b1;
         rdata_o = rdata_Q;
 
         if (stall_if_i) begin
@@ -214,7 +213,7 @@ module instr_core_interface
       ABORT:
       begin
         NS = IDLE;
-        ack_o = 1'b1;
+        valid_o = 1'b1;
         instr_req_o  = 1'b1;
 
         if (req_i) begin