diff --git a/dv/uvm/riscv_dv_extension/testlist.yaml b/dv/uvm/riscv_dv_extension/testlist.yaml
index 311844ed..fd13143f 100644
--- a/dv/uvm/riscv_dv_extension/testlist.yaml
+++ b/dv/uvm/riscv_dv_extension/testlist.yaml
@@ -48,6 +48,28 @@
     +directed_instr_0=riscv_load_store_rand_instr_stream,8
   rtl_test: core_ibex_base_test
 
+- test: riscv_jump_stress_test
+  description: >
+    Stress back to back jump instruction
+  iterations: 10
+  gen_test: riscv_instr_base_test
+  gen_opts: >
+    +instr_cnt=5000
+    +num_of_sub_program=5
+    +directed_instr_1=riscv_jal_instr,20
+  rtl_test: core_ibex_base_test
+
+- test: riscv_loop_test
+  description: >
+    Loop test
+  iterations: 10
+  gen_test: riscv_instr_base_test
+  gen_opts: >
+    +instr_cnt=10000
+    +num_of_sub_program=5
+    +directed_instr_1=riscv_loop_instr,20
+  rtl_test: core_ibex_base_test
+
 - test: riscv_mmu_stress_test
   description: >
     Test with different patterns of load/store instructions, stress test MMU
@@ -98,7 +120,7 @@
 - test: riscv_debug_basic_test
   description: >
     Randomly assert debug_req_i, random instruction sequence in debug_rom section
-  iterations: 5
+  iterations: 10
   gen_test: riscv_instr_base_test
   gen_opts: >
     +require_signature_addr=1
@@ -113,7 +135,7 @@
   rtl_test: core_ibex_debug_intr_basic_test
   sim_opts: >
     +require_signature_addr=1
-    +max_interval=1000
+    +max_interval=500
     +enable_debug_stress_seq=1
   compare_opts:
     compare_final_value_only: 1
@@ -130,7 +152,7 @@
     +no_csr_instr=1
     +no_fence=1
   rtl_test: core_ibex_debug_intr_basic_test
-  iterations: 10
+  iterations: 15
   sim_opts: >
     +max_interval=250
     +enable_debug_stress_seq=1
@@ -142,7 +164,7 @@
   description: >
     Randomly assert debug_req_i, insert branch instructions and subprograms into debug_rom to make core
     jump around within the debug_rom
-  iterations: 5
+  iterations: 10
   gen_test: riscv_rand_instr_test
   gen_opts: >
     +require_signature_addr=1
@@ -205,7 +227,7 @@
     A directed ebreak sequence will be inserted into the debug rom, upon encountering it,
     ibex should jump back to the beginning of debug mode. The sequence is designed to avoid an
     infinite loop.
-  iterations: 10
+  iterations: 15
   gen_test: riscv_rand_instr_test
   gen_opts: >
     +require_signature_addr=1
@@ -251,7 +273,7 @@
 - test: riscv_interrupt_test
   description: >
     Random instruction test with complete interrupt handling
-  iterations: 10
+  iterations: 15
   gen_test: riscv_rand_instr_test
   gen_opts: >
     +instr_cnt=6000
@@ -265,6 +287,24 @@
   compare_opts:
     compare_final_value_only: 1
 
+- test: riscv_interrupt_wfi_test
+  description: >
+    Inject interrupts after a encountering wfi instructions.
+  iterations: 15
+  gen_test: riscv_rand_instr_test
+  gen_opts: >
+    +instr_cnt=6000
+    +require_signature_addr=1
+    +enable_interrupt=1
+    +randomize_csr=1
+    +no_wfi=0
+  rtl_test: core_ibex_irq_wfi_test
+  sim_opts: >
+    +require_signature_addr=1
+    +enable_irq_seq=1
+  compare_opts:
+    compare_final_value_only: 1
+
 - test: riscv_csr_test
   description: >
     Test all CSR instructions on all implemented CSR registers
@@ -290,7 +330,7 @@
 - test: riscv_mem_error_test
   description: >
     Normal random instruction test, but randomly insert instruction fetch or memory load/store errors
-  iterations: 10
+  iterations: 15
   gen_test: riscv_rand_instr_test
   gen_opts: >
     +require_signature_addr=1
@@ -319,7 +359,7 @@
 - test: riscv_debug_single_step_test
   description: >
     Randomly assert debug_req_i, and set dcsr.step to make ibex execute one isntruction and then re-enter debug mode
-  iterations: 10
+  iterations: 15
   gen_test: riscv_instr_base_test
   gen_opts: >
     +require_signature_addr=1
@@ -344,7 +384,7 @@
 - test: riscv_reset_test
   description: >
     Randomly reset the core once in the middle of program execution
-  iterations: 10
+  iterations: 15
   gen_test: riscv_rand_instr_test
   gen_opts: >
     +instr_cnt=10000
diff --git a/dv/uvm/tests/core_ibex_base_test.sv b/dv/uvm/tests/core_ibex_base_test.sv
index 80f9d133..2539285c 100644
--- a/dv/uvm/tests/core_ibex_base_test.sv
+++ b/dv/uvm/tests/core_ibex_base_test.sv
@@ -10,7 +10,7 @@ class core_ibex_base_test extends uvm_test;
   virtual core_ibex_dut_probe_if                  dut_vif;
   mem_model_pkg::mem_model                        mem;
   core_ibex_vseq                                  vseq;
-  int unsigned                                    timeout_in_cycles = 5000000;
+  int unsigned                                    timeout_in_cycles = 10000000;
   // If no signature_addr handshake functionality is desired between the testbench and the generated
   // code, the test will wait for the specifield number of cycles before starting stimulus
   // sequences (irq and debug)
diff --git a/dv/uvm/tests/core_ibex_test_lib.sv b/dv/uvm/tests/core_ibex_test_lib.sv
index 9b6c1b2d..b1d705da 100644
--- a/dv/uvm/tests/core_ibex_test_lib.sv
+++ b/dv/uvm/tests/core_ibex_test_lib.sv
@@ -394,6 +394,22 @@ class core_ibex_directed_test extends core_ibex_debug_intr_basic_test;
 
 endclass
 
+// Interrupt WFI test class
+class core_ibex_irq_wfi_test extends core_ibex_directed_test;
+
+  `uvm_component_utils(core_ibex_irq_wfi_test)
+  `uvm_component_new
+
+  virtual task check_stimulus();
+    forever begin
+      wait (dut_vif.wfi === 1'b1);
+      wait(dut_vif.core_sleep === 1'b1);
+      send_irq_stimulus();
+    end
+  endtask
+
+endclass
+
 // Debug WFI test class
 class core_ibex_debug_wfi_test extends core_ibex_directed_test;