From c862f104afbc31f28dccff6210abe94df7e1a2bc Mon Sep 17 00:00:00 2001 From: Tom Roberts Date: Wed, 29 Apr 2020 16:19:35 +0100 Subject: [PATCH] [rtl] icache error signalling fix - Data valid should only be signalled when the current beat is signalling an error - PMP errors for future beats can sneak in while waiting for the current beat Signed-off-by: Tom Roberts --- rtl/ibex_icache.sv | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/rtl/ibex_icache.sv b/rtl/ibex_icache.sv index b1939e47..e1d4bfc6 100644 --- a/rtl/ibex_icache.sv +++ b/rtl/ibex_icache.sv @@ -600,11 +600,12 @@ module ibex_icache #( // data output, and have data available to send. // Data is available if: // - The request hit in the cache - // - The request received an error (since a PMP error might not actually receive any data) + // - The current beat is an error (since a PMP error might not actually receive any data) // - Buffered data is available (fill_rvd_cnt_q is ahead of fill_out_cnt_q) // - Data is available from the bus this cycle (fill_rvd_arb) assign fill_out_req[fb] = fill_busy_q[fb] & ~fill_stale_q[fb] & ~fill_out_done[fb] & - (fill_hit_ic1[fb] | fill_hit_q[fb] | (|fill_err_q[fb]) | + (fill_hit_ic1[fb] | fill_hit_q[fb] | + (fill_err_q[fb][fill_out_cnt_q[fb][LINE_BEATS_W-1:0]]) | (fill_rvd_beat[fb] > fill_out_cnt_q[fb]) | fill_rvd_arb[fb]); // Calculate when a beat of data is output. Any ECC error squashes the output that cycle.