diff --git a/vendor/google_riscv-dv.vendor.hjson b/vendor/google_riscv-dv.vendor.hjson
new file mode 100644
index 00000000..ffe91b82
--- /dev/null
+++ b/vendor/google_riscv-dv.vendor.hjson
@@ -0,0 +1,14 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+  name: "google_riscv-dv",
+  target_dir: "google_riscv-dv",
+  patch_dir: "patches/google_riscv-dv",
+
+  upstream: {
+    url: "https://github.com/google/riscv-dv",
+    rev: "master",
+  },
+
+}
diff --git a/vendor/patches/google_riscv-dv/0000-ibex-customization.patch b/vendor/patches/google_riscv-dv/0000-ibex-customization.patch
new file mode 100644
index 00000000..6b85024c
--- /dev/null
+++ b/vendor/patches/google_riscv-dv/0000-ibex-customization.patch
@@ -0,0 +1,183 @@
+diff --git a/scripts/ibex_log_to_trace_csv.py b/scripts/ibex_log_to_trace_csv.py
+new file mode 100644
+index 0000000..34036bb
+--- /dev/null
++++ b/scripts/ibex_log_to_trace_csv.py
+@@ -0,0 +1,53 @@
++"""
++Copyright lowRISC contributors.
++Licensed under the Apache License, Version 2.0, see LICENSE for details.
++SPDX-License-Identifier: Apache-2.0
++
++Convert ibex log to the standard trace CSV format
++"""
++
++import re
++import argparse
++
++from riscv_trace_csv import *
++
++def process_ibex_sim_log(ibex_log, csv):
++  """Process ibex simulation log.
++
++  Extract instruction and affected register information from ibex simulation
++  log and save to a standard CSV format.
++  """
++  print("Processing ibex log : %s" % ibex_log)
++  instr_cnt = 0
++  ibex_instr = ""
++
++  with open(ibex_log, "r") as f, open(csv, "w") as csv_fd:
++    trace_csv = RiscvInstructiontTraceCsv(csv_fd)
++    trace_csv.start_new_trace()
++    for line in f:
++      # Extract instruction infromation
++      m = re.search(r"^\s*(?P<time>\d+)\s+(?P<cycle>\d+) " \
++                    "(?P<pc>[0-9a-f]+) (?P<bin>[0-9a-f]+) (?P<instr>.*)" \
++                    "x(?P<rd>\d+)=(?P<val>[0-9a-f]+)", line)
++      if m:
++        # Write the extracted instruction to a csvcol buffer file
++        rv_instr_trace = RiscvInstructiontTraceEntry()
++        rv_instr_trace.rd = gpr_to_abi("x%0s" % m.group("rd"))
++        rv_instr_trace.rd_val = m.group("val")
++        rv_instr_trace.addr = m.group("pc")
++        rv_instr_trace.binary = m.group("bin")
++        rv_instr_trace.instr_str = m.group("instr")
++        trace_csv.write_trace_entry(rv_instr_trace)
++        #print("Processed instruction[%d] : %0s" % (instr_cnt, m.group("instr")))
++        instr_cnt += 1
++
++  print("Processed instruction count : %d" % instr_cnt)
++
++instr_trace = []
++# Parse input arguments
++parser = argparse.ArgumentParser()
++parser.add_argument("--log", type=str, help="Input ibex simulation log")
++parser.add_argument("--csv", type=str, help="Output trace csv_buf file")
++args = parser.parse_args()
++# Process ibex log
++process_ibex_sim_log(args.log, args.csv)
+diff --git a/src/riscv_asm_program_gen.sv b/src/riscv_asm_program_gen.sv
+index b538b72..78ab6ed 100644
+--- a/src/riscv_asm_program_gen.sv
++++ b/src/riscv_asm_program_gen.sv
+@@ -244,11 +244,19 @@ class riscv_asm_program_gen extends uvm_object;
+   //---------------------------------------------------------------------------------------
+ 
+   virtual function void gen_program_header();
++    // ------------- IBEX modification start --------------------
++    // The ibex core load the program from 0x80
++    // Some address is reserved for hardware interrupt handling, need to decide if we need to copy
++    // the init program from crt0.S later.
+     instr_stream.push_back(".macro init");
+     instr_stream.push_back(".endm");
+     instr_stream.push_back(".section .text.init");
+     instr_stream.push_back(".globl _start");
++    instr_stream.push_back("j _start");
++    // Align the start section to 0x80
++    instr_stream.push_back(".align 7");
+     instr_stream.push_back("_start:");
++    // ------------- IBEX modification end --------------------
+   endfunction
+ 
+   virtual function void gen_program_end();
+diff --git a/src/riscv_core_setting.sv b/src/riscv_core_setting.sv
+index 5cb3d76..c523573 100644
+--- a/src/riscv_core_setting.sv
++++ b/src/riscv_core_setting.sv
+@@ -18,25 +18,27 @@
+ // Processor feature configuration
+ //-----------------------------------------------------------------------------
+ // XLEN
+-parameter int XLEN = 64;
++parameter int XLEN = 32;
+ 
+ // Parameter for SATP mode, set to BARE if address translation is not supported
+-parameter satp_mode_t SATP_MODE = SV39;
++parameter satp_mode_t SATP_MODE = BARE;
+ 
+ // Supported Privileged mode
+-privileged_mode_t supported_privileged_mode[] = {USER_MODE, SUPERVISOR_MODE, MACHINE_MODE};
++privileged_mode_t supported_privileged_mode[] = {MACHINE_MODE};
+ 
+ // Unsupported instructions
+-riscv_instr_name_t unsupported_instr[];
++// Avoid generating these instructions in regular regression
++// FENCE.I is intentionally treated as illegal instruction by ibex core
++riscv_instr_name_t unsupported_instr[] = {FENCEI};
+ 
+ // ISA supported by the processor
+-riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV64I, RV64M, RV32C, RV64C};
++riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV32C};
+ 
+ // Support delegate trap to user mode
+ bit support_umode_trap = 0;
+ 
+ // Support sfence.vma instruction
+-bit support_sfence = 1;
++bit support_sfence = 0;
+ 
+ // Cache line size (in bytes)
+ // If processor does not support caches, set to XLEN/8
+@@ -46,7 +48,7 @@ int dcache_line_size_in_bytes = 128;
+ // For processor that doesn't have data TLB, this can be set to 1
+ // For processor that supports data TLB, this should be set to be larger than the number
+ // of entries of dTLB to cover dTLB hit/miss scenario
+-int num_of_data_pages = 40;
++int num_of_data_pages = 4;
+ 
+ // Data section byte size
+ // For processor with no dTLB and data cache, keep the value below 10K
+@@ -55,12 +57,6 @@ int num_of_data_pages = 40;
+ int data_page_size = 4096;
+ int data_page_alignment = $clog2(data_page_size);
+ 
+-// The maximum data section byte size actually used by load/store instruction
+-// Set to this value to be smaller than data_page_size. If there's data cache in the system,
+-// this value should be set large enough to be able to hit cache hit/miss scenario within a data
+-// section. Don't set this to too big as it will introduce a very large binary.
+-int max_used_data_page_size = 512;
+-
+ // Stack section word length
+ int stack_len = 5000;
+ 
+@@ -69,7 +65,7 @@ int stack_len = 5000;
+ //-----------------------------------------------------------------------------
+ 
+ // Number of kernel data pages
+-int num_of_kernel_data_pages = 5;
++int num_of_kernel_data_pages = 2;
+ 
+ // Byte size of kernel data pages
+ int kernel_data_page_size = 4096;
+diff --git a/testlist b/testlist
+index 123951e..0fd4e31 100644
+--- a/testlist
++++ b/testlist
+@@ -15,15 +15,15 @@
+ //================================================
+ // Test name                    : iteration count
+ //------------------------------------------------
+-riscv_arithmetic_basic_test     : 2
+-riscv_machine_mode_rand_test    : 2
+-riscv_privileged_mode_rand_test : 2
+-riscv_rand_instr_test           : 2
+-riscv_rand_jump_test            : 2
+-riscv_mmu_stress_test           : 2
+-riscv_page_table_exception_test : 2
+-riscv_no_fence_test             : 2
+-riscv_sfence_exception_test     : 2
+-riscv_illegal_instr_test        : 1
+-riscv_hint_instr_test           : 1
++riscv_arithmetic_basic_test     : 10
++riscv_machine_mode_rand_test    : 10
++riscv_privileged_mode_rand_test : 0
++riscv_rand_instr_test           : 10
++riscv_rand_jump_test            : 10
++riscv_mmu_stress_test           : 10
++riscv_page_table_exception_test : 0
++riscv_no_fence_test             : 10
++riscv_sfence_exception_test     : 0
++riscv_illegal_instr_test        : 10
++riscv_hint_instr_test           : 10
+ //------------------------------------------------