diff --git a/doc/02_user/integration.rst b/doc/02_user/integration.rst
index 0d42fe10..294b8664 100644
--- a/doc/02_user/integration.rst
+++ b/doc/02_user/integration.rst
@@ -133,7 +133,7 @@ Interfaces
 |                            |                         |     | from :ref:`csr-mhartid` CSR            |
 +----------------------------+-------------------------+-----+----------------------------------------+
 | ``boot_addr_i``            | 32                      | in  | First program counter after reset      |
-|                            |                         |     | = ``boot_addr_i`` + 0x80,              |
+|                            |                         |     | = ``boot_addr_i``,                     |
 |                            |                         |     | see :ref:`exceptions-interrupts`       |
 +----------------------------+-------------------------+-----+----------------------------------------+
 | ``instr_*``                | Instruction fetch interface, see :ref:`instruction-fetch`              |
diff --git a/doc/03_reference/exception_interrupts.rst b/doc/03_reference/exception_interrupts.rst
index 3a010e78..4d1d0618 100644
--- a/doc/03_reference/exception_interrupts.rst
+++ b/doc/03_reference/exception_interrupts.rst
@@ -14,7 +14,7 @@ The base address of the vector table is initialized to the boot address (must be
 The base address can be changed after bootup by writing to the ``mtvec`` CSR.
 For more information, see the :ref:`cs-registers` documentation.
 
-The core starts fetching at the address made by concatenating the most significant 3 bytes of the boot address and the reset value (0x80) as the least significant byte.
+The core starts fetching at the address made by the most significant 3 bytes of the boot address.
 It is assumed that the boot address is supplied via a register to avoid long paths to the instruction fetch unit.
 
 Privilege Modes