diff --git a/controller.sv b/controller.sv index 9677a120..46763066 100644 --- a/controller.sv +++ b/controller.sv @@ -303,13 +303,6 @@ module controller DECODE: begin - // synopsys translate_off - $display("%t: Decoding Instruction", $time); - $display("%t: | fct7 | rs2 | rs1 | | rd | opc. |", $time); - $display("%t: 0b %b %b %b %b %b %b", $time, instr_rdata_i[31:25], instr_rdata_i[`REG_RS2], - instr_rdata_i[`REG_RS1], instr_rdata_i[14:12], instr_rdata_i[`REG_RD], - instr_rdata_i[6:0]); - // synopsys translate_on unique case (instr_rdata_i[6:0]) ////////////////////////////////////// @@ -321,36 +314,30 @@ module controller ////////////////////////////////////// `OPCODE_JAL: begin // Jump and Link - if (instr_rdata_i inside `INSTR_JAL) begin - pc_mux_sel_o = `PC_FROM_IMM; - alu_pc_mux_sel_o = 1'b1; - alu_op_a_mux_sel_o = `OP_A_CURRPC; - alu_op_b_mux_sel_o = `OP_B_IMM; - immediate_mux_sel_o = `IMM_C4; - alu_operator = `ALU_ADD; - regfile_alu_we = 1'b1; + if (instr_rdata_i ==? `INSTR_JAL) begin + pc_mux_sel_o = `PC_FROM_IMM; + alu_pc_mux_sel_o = 1'b1; + alu_op_a_mux_sel_o = `OP_A_CURRPC; + alu_op_b_mux_sel_o = `OP_B_IMM; + immediate_mux_sel_o = `IMM_C4; + alu_operator = `ALU_ADD; + regfile_alu_we = 1'b1; end else begin - // synopsys translate_off - $display("%t: Illegal JAL instruction: %b", $time, instr_rdata_i); - // synopsys translate_on - illegal_insn_o = 1'b1; + illegal_insn_o = 1'b1; end end `OPCODE_JALR: begin // Jump and Link Register - if (instr_rdata_i inside `INSTR_JALR) begin - pc_mux_sel_o = `PC_FROM_REGFILE; - alu_op_a_mux_sel_o = `OP_A_CURRPC; - alu_op_b_mux_sel_o = `OP_B_IMM; - immediate_mux_sel_o = `IMM_C4; - alu_operator = `ALU_ADD; - regfile_alu_we = 1'b1; - rega_used = 1'b1; + if (instr_rdata_i ==? `INSTR_JALR) begin + pc_mux_sel_o = `PC_FROM_REGFILE; + alu_op_a_mux_sel_o = `OP_A_CURRPC; + alu_op_b_mux_sel_o = `OP_B_IMM; + immediate_mux_sel_o = `IMM_C4; + alu_operator = `ALU_ADD; + regfile_alu_we = 1'b1; + rega_used = 1'b1; end else begin - // synopsys translate_off - $display("%t: Illegal JALR instruction: %b", $time, instr_rdata_i); - // synopsys translate_on - illegal_insn_o = 1'b1; + illegal_insn_o = 1'b1; end end @@ -464,9 +451,6 @@ module controller `INSTR_SH: data_type_o = 2'b01; `INSTR_SB: data_type_o = 2'b10; default: begin - // synopsys translate_off - $display("%t: Illegal STORE instruction: %b", $time, instr_rdata_i); - // synopsys translate_on data_req = 1'b0; data_we = 1'b0; rega_used = 1'b0; @@ -503,9 +487,6 @@ module controller end default: begin - // synopsys translate_off - $display("%t: Illegal LOAD instruction: %b", $time, instr_rdata_i); - // synopsys translate_on data_req = 1'b0; regfile_we = 1'b0; rega_used = 1'b0; @@ -652,9 +633,6 @@ module controller `INSTR_SRLI: alu_operator = `ALU_SRL; // Shift Right Logical by Immediate `INSTR_SRAI: alu_operator = `ALU_SRA; // Shift Right Arithmetically by Immediate default: begin - // synopsys translate_off - $display("%t: Illegal OP-IMM instruction: %b", $time, instr_rdata_i); - // synopsys translate_on regfile_alu_we = 1'b0; illegal_insn_o = 1'b1; end @@ -1158,9 +1136,6 @@ module controller */ default: begin - // synopsys translate_off - $display("%t: Unknown Instruction 0x%h.", $time, instr_rdata_i[31:0]); - // synopsys translate_on illegal_insn_o = 1'b1; // TODO: Replace with exception pc_mux_sel_o = `NO_INCR; @@ -1168,8 +1143,12 @@ module controller endcase; // case (instr_rdata_i[6:0]) - if (illegal_insn_o = 1'b1) begin - + if (illegal_insn_o == 1'b1) begin + // synopsys translate_off + $display("%t: Illegal instruction:", $time, instr_rdata_i); + prettyPrintInstruction(instr_rdata_i); + $stop; + // synopsys translate_on end // misaligned access was detected by the LSU diff --git a/include/defines.sv b/include/defines.sv index f1633073..5662584f 100644 --- a/include/defines.sv +++ b/include/defines.sv @@ -84,9 +84,6 @@ `define OPCODE_SF 6'h39 */ - - - `define OPCODE_SYSTEM 7'h73 `define OPCODE_FENCE 7'h0f `define OPCODE_OP 7'h33 @@ -147,12 +144,12 @@ // SYSTEM `define INSTR_SCALL { {11 {1'b0}}, 1'b0, {13 {1'b0}}, `OPCODE_SYSTEM } `define INSTR_SBREAK { {11 {1'b0}}, 1'b1, {13 {1'b0}}, `OPCODE_SYSTEM } -`define INSTR_RDCYCLE { 5'b11000, {5 {5'b0}}, 2'b00, {5 {1'b0}}, 3'b010, {5 {1'b?}}, `OPCODE_SYSTEM } -`define INSTR_RDCYCLEH { 5'b11001, {5 {5'b0}}, 2'b00, {5 {1'b0}}, 3'b010, {5 {1'b?}}, `OPCODE_SYSTEM } -`define INSTR_RDTIME { 5'b11000, {5 {5'b0}}, 2'b01, {5 {1'b0}}, 3'b010, {5 {1'b?}}, `OPCODE_SYSTEM } -`define INSTR_RDTIMEH { 5'b11001, {5 {5'b0}}, 2'b01, {5 {1'b0}}, 3'b010, {5 {1'b?}}, `OPCODE_SYSTEM } -`define INSTR_RDINSTRET { 5'b11000, {5 {5'b0}}, 2'b10, {5 {1'b0}}, 3'b010, {5 {1'b?}}, `OPCODE_SYSTEM } -`define INSTR_RDINSTRETH { 5'b11001, {5 {5'b0}}, 2'b10, {5 {1'b0}}, 3'b010, {5 {1'b?}}, `OPCODE_SYSTEM } +`define INSTR_RDCYCLE { 5'b11000, {5 {1'b0}}, 2'b00, {5 {1'b0}}, 3'b010, {5 {1'b?}}, `OPCODE_SYSTEM } +`define INSTR_RDCYCLEH { 5'b11001, {5 {1'b0}}, 2'b00, {5 {1'b0}}, 3'b010, {5 {1'b?}}, `OPCODE_SYSTEM } +`define INSTR_RDTIME { 5'b11000, {5 {1'b0}}, 2'b01, {5 {1'b0}}, 3'b010, {5 {1'b?}}, `OPCODE_SYSTEM } +`define INSTR_RDTIMEH { 5'b11001, {5 {1'b0}}, 2'b01, {5 {1'b0}}, 3'b010, {5 {1'b?}}, `OPCODE_SYSTEM } +`define INSTR_RDINSTRET { 5'b11000, {5 {1'b0}}, 2'b10, {5 {1'b0}}, 3'b010, {5 {1'b?}}, `OPCODE_SYSTEM } +`define INSTR_RDINSTRETH { 5'b11001, {5 {1'b0}}, 2'b10, {5 {1'b0}}, 3'b010, {5 {1'b?}}, `OPCODE_SYSTEM } // RV32M `define INSTR_MUL { 7'b0000001, {10 {1'b?}}, 3'b000, {5 {1'b?}}, `OPCODE_OP } @@ -172,6 +169,36 @@ `define REG_RD 11:07 +// synopsis translate off +function void prettyPrintInstruction(input [31:0] instr); + string opcode; + begin + unique case (instr[6:0]) + `OPCODE_SYSTEM: opcode = "SYSTEM"; + `OPCODE_FENCE: opcode = "FENCE"; + `OPCODE_OP: opcode = "OP"; + `OPCODE_OPIMM: opcode = "OPIMM"; + `OPCODE_STORE: opcode = "STORE"; + `OPCODE_LOAD: opcode = "LOAD"; + `OPCODE_BRANCH: opcode = "BRANCH"; + `OPCODE_JALR: opcode = "JALR"; + `OPCODE_JAL: opcode = "JAL"; + `OPCODE_AUIPC: opcode = "AUIPC"; + `OPCODE_LUI: opcode = "LUI"; + default: opcode = "Unknown"; + endcase // unique case (instr[6:0]) + + $display("%t: %s Instruction 0x%h.", $time, opcode, instr[31:0]); + $display("%t: | fct7 | rs2 | rs1 | | rd | opc. |", $time); + $display("%t: 0b %b %b %b %b %b %b", $time, instr[31:25], instr[`REG_RS2], + instr[`REG_RS1], instr[14:12], instr[`REG_RD], instr[6:0]); + $display(); + end +endfunction // prettyPrintInstruction +// synopsis translate on + + + ////////////////////////////////////////////////////////////////////////////// // _ _ _ _ ___ _ _ // // / \ | | | | | | / _ \ _ __ ___ _ __ __ _| |_(_) ___ _ __ ___ //