diff --git a/vendor/google_riscv-dv.lock.hjson b/vendor/google_riscv-dv.lock.hjson index 0434c796..64e4d305 100644 --- a/vendor/google_riscv-dv.lock.hjson +++ b/vendor/google_riscv-dv.lock.hjson @@ -9,6 +9,6 @@ upstream: { url: https://github.com/google/riscv-dv - rev: 5baf82a24347dae3cb71c8ab66a66494666d2291 + rev: 76753158d940fffc53fbb92942ae5d1d768a7cdc } } diff --git a/vendor/google_riscv-dv/src/isa/riscv_b_instr.sv b/vendor/google_riscv-dv/src/isa/riscv_b_instr.sv index e9f7605b..48e2415f 100755 --- a/vendor/google_riscv-dv/src/isa/riscv_b_instr.sv +++ b/vendor/google_riscv-dv/src/isa/riscv_b_instr.sv @@ -20,6 +20,27 @@ class riscv_b_instr extends riscv_instr; rand riscv_reg_t rs3; bit has_rs3 = 1'b0; + constraint single_bit_shift_c { + if (category == SHIFT) { + imm inside {[0:31]}; + } + } + + constraint shuffle_c { + if (instr_name inside {SHFLI, UNSHFLI}) { + imm inside {[0:15]}; + } + } + + constraint or_combine_c { + if (instr_name inside {GORCI}) { + imm inside {[0:31]}; + } + if (instr_name inside {GORCIW}) { + imm inside {[0:63]}; + } + } + `uvm_object_utils(riscv_b_instr) function new(string name = ""); @@ -82,42 +103,38 @@ class riscv_b_instr extends riscv_instr; // Convert the instruction to assembly code virtual function string convert2asm(string prefix = ""); - string asm_str_super, asm_str; - asm_str_super = super.convert2asm(prefix); + string asm_str_final, asm_str; asm_str = format_string(get_instr_name(), MAX_INSTR_STR_LEN); case (format) I_FORMAT: begin if (instr_name inside {FSRI, FSRIW}) begin // instr rd,rs1,rs3,imm - asm_str_super = $sformatf("%0s%0s, %0s, %0s, %0s", asm_str, rd.name(), rs1.name(), + asm_str_final = $sformatf("%0s%0s, %0s, %0s, %0s", asm_str, rd.name(), rs1.name(), rs3.name(), get_imm()); end end R_FORMAT: begin //instr rd rs1 - if (instr_name inside {CLZW, CTZW, PCNTW, SEXT_B, SEXT_H, CLZ, CTZ, PCNT, BMATFLIP}) begin - asm_str_super = $sformatf("%0s%0s, %0s", asm_str, rd.name(), rs1.name()); - end - - if (instr_name inside {CRC32_B, CRC32_H, CRC32_W, CRC32C_B, CRC32C_H, CRC32C_W, CRC32_D, + if (instr_name inside {CLZW, CTZW, PCNTW, SEXT_B, SEXT_H, CLZ, CTZ, PCNT, BMATFLIP, + CRC32_B, CRC32_H, CRC32_W, CRC32C_B, CRC32C_H, CRC32C_W, CRC32_D, CRC32C_D}) begin - asm_str_super = $sformatf("%0s%0s, %0s", asm_str, rd.name(), rs1.name()); + asm_str_final = $sformatf("%0s%0s, %0s", asm_str, rd.name(), rs1.name()); end end R4_FORMAT: begin // instr rd,rs1,rs2,rs3 - asm_str_super = $sformatf("%0s%0s, %0s, %0s, %0s", asm_str, rd.name(), rs1.name(), + asm_str_final = $sformatf("%0s%0s, %0s, %0s, %0s", asm_str, rd.name(), rs1.name(), rs2.name(), rs3.name()); end default: `uvm_info(`gfn, $sformatf("Unsupported format %0s", format.name()), UVM_LOW) endcase - if (comment != "") begin - asm_str = {asm_str, " #", comment}; - return asm_str.tolower(); + if (asm_str_final == "") begin + return super.convert2asm(prefix); end - return asm_str_super.tolower(); + if (comment != "") asm_str_final = {asm_str, " #", comment}; + return asm_str_final.tolower(); endfunction function bit [6:0] get_opcode(); diff --git a/vendor/google_riscv-dv/src/isa/rv32b_instr.sv b/vendor/google_riscv-dv/src/isa/rv32b_instr.sv index a50bb57c..984a1d4b 100755 --- a/vendor/google_riscv-dv/src/isa/rv32b_instr.sv +++ b/vendor/google_riscv-dv/src/isa/rv32b_instr.sv @@ -70,8 +70,6 @@ `DEFINE_B_INSTR(UNSHFL, R_FORMAT, ARITHMETIC, RV32B) `DEFINE_B_INSTR(BDEP, R_FORMAT, ARITHMETIC, RV32B) `DEFINE_B_INSTR(BEXT, R_FORMAT, ARITHMETIC, RV32B) -`DEFINE_B_INSTR(BMATOR, R_FORMAT, ARITHMETIC, RV32B) -`DEFINE_B_INSTR(BMATXOR, R_FORMAT, ARITHMETIC, RV32B) `DEFINE_B_INSTR(BFP, R_FORMAT, ARITHMETIC, RV32B) `DEFINE_B_INSTR(SHFLI, I_FORMAT, ARITHMETIC, RV32B, UIMM) `DEFINE_B_INSTR(UNSHFLI, I_FORMAT, ARITHMETIC, RV32B, UIMM) diff --git a/vendor/google_riscv-dv/src/isa/rv64b_instr.sv b/vendor/google_riscv-dv/src/isa/rv64b_instr.sv index 93c61f45..9c681c40 100755 --- a/vendor/google_riscv-dv/src/isa/rv64b_instr.sv +++ b/vendor/google_riscv-dv/src/isa/rv64b_instr.sv @@ -16,6 +16,8 @@ */ // ARITHMETIC intructions +`DEFINE_B_INSTR(BMATOR, R_FORMAT, ARITHMETIC, RV64B) +`DEFINE_B_INSTR(BMATXOR, R_FORMAT, ARITHMETIC, RV64B) `DEFINE_B_INSTR(BMATFLIP, R_FORMAT, ARITHMETIC, RV64B) `DEFINE_B_INSTR(CRC32_D, R_FORMAT, ARITHMETIC, RV64B) `DEFINE_B_INSTR(CRC32C_D, R_FORMAT, ARITHMETIC, RV64B) diff --git a/vendor/google_riscv-dv/src/riscv_asm_program_gen.sv b/vendor/google_riscv-dv/src/riscv_asm_program_gen.sv index a13bd2b1..f664be48 100644 --- a/vendor/google_riscv-dv/src/riscv_asm_program_gen.sv +++ b/vendor/google_riscv-dv/src/riscv_asm_program_gen.sv @@ -877,7 +877,7 @@ class riscv_asm_program_gen extends uvm_object; if (SATP_MODE != BARE) begin instr_stream.push_back(".align 12"); end else begin - instr_stream.push_back(".align 2"); + instr_stream.push_back($sformatf(".align %d", cfg.tvec_alignment)); end tvec_name = tvec.name(); gen_section(get_label($sformatf("%0s_handler", tvec_name.tolower()), hart), instr); diff --git a/vendor/google_riscv-dv/src/riscv_instr_gen_config.sv b/vendor/google_riscv-dv/src/riscv_instr_gen_config.sv index 0cb610ab..dc921ef6 100644 --- a/vendor/google_riscv-dv/src/riscv_instr_gen_config.sv +++ b/vendor/google_riscv-dv/src/riscv_instr_gen_config.sv @@ -63,6 +63,11 @@ class riscv_instr_gen_config extends uvm_object; rand bit [1:0] mstatus_vs; rand mtvec_mode_t mtvec_mode; + // TVEC alignment + // This value is the log_2 of the byte-alignment of TVEC.BASE field + // As per RISC-V privileged spec, default will be set to 2 (4-byte aligned) + int tvec_alignment = 2; + // Floating point rounding mode rand f_rounding_mode_t fcsr_rm; @@ -433,6 +438,7 @@ class riscv_instr_gen_config extends uvm_object; `uvm_field_enum(riscv_reg_t, ra, UVM_DEFAULT) `uvm_field_enum(riscv_reg_t, sp, UVM_DEFAULT) `uvm_field_enum(riscv_reg_t, tp, UVM_DEFAULT) + `uvm_field_int(tvec_alignment, UVM_DEFAULT) `uvm_field_int(no_data_page, UVM_DEFAULT) `uvm_field_int(no_branch_jump, UVM_DEFAULT) `uvm_field_int(no_load_store, UVM_DEFAULT) @@ -492,6 +498,7 @@ class riscv_instr_gen_config extends uvm_object; get_bool_arg_value("+enable_timer_irq=", enable_timer_irq); get_int_arg_value("+num_of_sub_program=", num_of_sub_program); get_int_arg_value("+instr_cnt=", instr_cnt); + get_int_arg_value("+tvec_alignment=", tvec_alignment); get_bool_arg_value("+no_ebreak=", no_ebreak); get_bool_arg_value("+no_dret=", no_dret); get_bool_arg_value("+no_wfi=", no_wfi); diff --git a/vendor/google_riscv-dv/target/rv32imcb/testlist.yaml b/vendor/google_riscv-dv/target/rv32imcb/testlist.yaml index 231710af..bbede2b1 100644 --- a/vendor/google_riscv-dv/target/rv32imcb/testlist.yaml +++ b/vendor/google_riscv-dv/target/rv32imcb/testlist.yaml @@ -30,37 +30,14 @@ # gcc_opts : gcc compile options # -------------------------------------------------------------------------------- -- import: /yaml/base_testlist.yaml +- import: /target/rv32imc/testlist.yaml -- test: riscv_non_compressed_instr_test +- test: riscv_b_ext_test description: > - Random instruction test without compressed instructions + Random instruction test with b extension iterations: 1 gen_test: riscv_rand_instr_test gen_opts: > - +disable_compressed_instr=1 - rtl_test: core_base_test - - -- test: riscv_hint_instr_test - description: > - HINT instruction test, verify the processor can detect HINT instruction - treat it as NOP. No illegal instruction exception is expected - iterations: 2 - gen_test: riscv_rand_instr_test - gen_opts: > - +hint_instr_ratio=5 - rtl_test: core_base_test - -- test: riscv_pmp_test - description: > - Provide some PMP configuration parameters, and setup PMP CSRs appropriately - iterations: 2 - gen_test: riscv_rand_instr_test - gen_opts: > - +pmp_randomize=0 - +pmp_num_regions=1 - +pmp_granularity=1 - +pmp_region_0=L:0,A:NAPOT,X:1,W:1,R:1,ADDR:FFFFFFFF + +enable_b_extension=1 rtl_test: core_base_test