diff --git a/formal/Makefile b/formal/riscv-formal/Makefile
similarity index 100%
rename from formal/Makefile
rename to formal/riscv-formal/Makefile
diff --git a/formal/README.md b/formal/riscv-formal/README.md
similarity index 81%
rename from formal/README.md
rename to formal/riscv-formal/README.md
index b19988e4..b1007b5b 100644
--- a/formal/README.md
+++ b/formal/riscv-formal/README.md
@@ -29,8 +29,8 @@ It should not be necessary to create the Verilog source manually as it is used b
 Run the following command from the top level directory of Ibex to create the Verilog source.
 
 ```console
-make -C formal
+make -C formal/riscv-formal
 ```
 
-This will create a directory *formal/build* which contains an equivalent Verilog file for each SystemVerilog source.
-The single output file *formal/ibex.v* contains the complete Ibex source, which can then be imported by riscv-formal.
+This will create a directory *formal/riscv-formal/build* which contains an equivalent Verilog file for each SystemVerilog source.
+The single output file *formal/riscv-formal/ibex.v* contains the complete Ibex source, which can then be imported by riscv-formal.