diff --git a/rtl/ibex_alu.sv b/rtl/ibex_alu.sv index 6ed85edf..18b49d40 100644 --- a/rtl/ibex_alu.sv +++ b/rtl/ibex_alu.sv @@ -227,12 +227,12 @@ module ibex_alu #( // ======================= // Single bit instructions operate on bit operand_b_i[4:0] of operand_a_i. - // The operations sbset, sbclr and sbinv are implemented by generation of a bit-mask using the + // The operations bset, bclr and binv are implemented by generation of a bit-mask using the // shifter structure. This is done by left-shifting the operand 32'h1 by the required amount. // The signal shift_sbmode multiplexes the shifter input and sets the signal shift_left. // Further processing is taken care of by a separate structure. // - // For sbext, the bit defined by operand_b_i[4:0] is to be returned. This is done by simply + // For bext, the bit defined by operand_b_i[4:0] is to be returned. This is done by simply // shifting operand_a_i to the right by the required amount and returning bit [0] of the result. // // Bit-Field Place @@ -291,7 +291,7 @@ module ibex_alu #( // single-bit mode: shift assign shift_sbmode = (RV32B != RV32BNone) ? - (operator_i == ALU_SBSET) | (operator_i == ALU_SBCLR) | (operator_i == ALU_SBINV) : 1'b0; + (operator_i == ALU_BSET) | (operator_i == ALU_BCLR) | (operator_i == ALU_BINV) : 1'b0; // left shift if this is: // * a standard left shift (slo, sll) @@ -299,7 +299,7 @@ module ibex_alu #( // * a ror in the second cycle // * fsl: without word-swap bit: first cycle, else: second cycle // * fsr: without word-swap bit: second cycle, else: first cycle - // * a single-bit instruction: sbclr, sbset, sbinv (excluding sbext) + // * a single-bit instruction: bclr, bset, binv (excluding bext) // * bfp: bfp_mask << bfp_off always_comb begin unique case (operator_i) @@ -580,10 +580,10 @@ module ibex_alu #( always_comb begin unique case (operator_i) - ALU_SBSET: singlebit_result = operand_a_i | shift_result; - ALU_SBCLR: singlebit_result = operand_a_i & ~shift_result; - ALU_SBINV: singlebit_result = operand_a_i ^ shift_result; - default: singlebit_result = {31'h0, shift_result[0]}; // ALU_SBEXT + ALU_BSET: singlebit_result = operand_a_i | shift_result; + ALU_BCLR: singlebit_result = operand_a_i & ~shift_result; + ALU_BINV: singlebit_result = operand_a_i ^ shift_result; + default: singlebit_result = {31'h0, shift_result[0]}; // ALU_BEXT endcase end @@ -1272,8 +1272,8 @@ module ibex_alu #( ALU_BCOMPRESS, ALU_BDECOMPRESS: result_o = multicycle_result; // Single-Bit Bitmanip Operations (RV32B) - ALU_SBSET, ALU_SBCLR, - ALU_SBINV, ALU_SBEXT: result_o = singlebit_result; + ALU_BSET, ALU_BCLR, + ALU_BINV, ALU_BEXT: result_o = singlebit_result; // General Reverse / Or-combine (RV32B) ALU_GREV, ALU_GORC: result_o = rev_result; diff --git a/rtl/ibex_decoder.sv b/rtl/ibex_decoder.sv index 4d743bc1..4a254c73 100644 --- a/rtl/ibex_decoder.sv +++ b/rtl/ibex_decoder.sv @@ -363,9 +363,9 @@ module ibex_decoder #( unique case (instr[31:27]) 5'b0_0000: illegal_insn = (instr[26:25] == 2'b00) ? 1'b0 : 1'b1; // slli 5'b0_0100, // sloi - 5'b0_1001, // sbclri - 5'b0_0101, // sbseti - 5'b0_1101: illegal_insn = (RV32B != RV32BNone) ? 1'b0 : 1'b1; // sbinvi + 5'b0_1001, // bclri + 5'b0_0101, // bseti + 5'b0_1101: illegal_insn = (RV32B != RV32BNone) ? 1'b0 : 1'b1; // binvi 5'b0_0001: if (instr[26] == 1'b0) begin illegal_insn = (RV32B == RV32BFull) ? 1'b0 : 1'b1; // shfl end else begin @@ -402,7 +402,7 @@ module ibex_decoder #( 5'b0_0100, // sroi 5'b0_1100, // rori - 5'b0_1001: illegal_insn = (RV32B != RV32BNone) ? 1'b0 : 1'b1; // sbexti + 5'b0_1001: illegal_insn = (RV32B != RV32BNone) ? 1'b0 : 1'b1; // bexti 5'b0_1101: begin if ((RV32B == RV32BFull)) begin @@ -482,10 +482,10 @@ module ibex_decoder #( {7'b010_0100, 3'b100}, // packu {7'b000_0100, 3'b111}, // packh // RV32B zbs - {7'b010_0100, 3'b001}, // sbclr - {7'b001_0100, 3'b001}, // sbset - {7'b011_0100, 3'b001}, // sbinv - {7'b010_0100, 3'b101}, // sbext + {7'b010_0100, 3'b001}, // bclr + {7'b001_0100, 3'b001}, // bset + {7'b011_0100, 3'b001}, // binv + {7'b010_0100, 3'b101}, // bext // RV32B zbf {7'b010_0100, 3'b111}: illegal_insn = (RV32B != RV32BNone) ? 1'b0 : 1'b1; // bfp // RV32B zbe @@ -824,9 +824,9 @@ module ibex_decoder #( unique case (instr_alu[31:27]) 5'b0_0000: alu_operator_o = ALU_SLL; // Shift Left Logical by Immediate 5'b0_0100: alu_operator_o = ALU_SLO; // Shift Left Ones by Immediate - 5'b0_1001: alu_operator_o = ALU_SBCLR; // Clear bit specified by immediate - 5'b0_0101: alu_operator_o = ALU_SBSET; // Set bit specified by immediate - 5'b0_1101: alu_operator_o = ALU_SBINV; // Invert bit specified by immediate. + 5'b0_1001: alu_operator_o = ALU_BCLR; // Clear bit specified by immediate + 5'b0_0101: alu_operator_o = ALU_BSET; // Set bit specified by immediate + 5'b0_1101: alu_operator_o = ALU_BINV; // Invert bit specified by immediate. // Shuffle with Immediate Control Value 5'b0_0001: if (instr_alu[26] == 0) alu_operator_o = ALU_SHFL; 5'b0_1100: begin @@ -898,7 +898,7 @@ module ibex_decoder #( 5'b0_0000: alu_operator_o = ALU_SRL; // Shift Right Logical by Immediate 5'b0_1000: alu_operator_o = ALU_SRA; // Shift Right Arithmetically by Immediate 5'b0_0100: alu_operator_o = ALU_SRO; // Shift Right Ones by Immediate - 5'b0_1001: alu_operator_o = ALU_SBEXT; // Extract bit specified by immediate. + 5'b0_1001: alu_operator_o = ALU_BEXT; // Extract bit specified by immediate. 5'b0_1100: begin alu_operator_o = ALU_ROR; // Rotate Right by Immediate alu_multicycle_o = 1'b1; @@ -1023,10 +1023,10 @@ module ibex_decoder #( {7'b001_0000, 3'b110}: if (RV32B != RV32BNone) alu_operator_o = ALU_SH3ADD; // sh3add // RV32B zbs - {7'b010_0100, 3'b001}: if (RV32B != RV32BNone) alu_operator_o = ALU_SBCLR; // sbclr - {7'b001_0100, 3'b001}: if (RV32B != RV32BNone) alu_operator_o = ALU_SBSET; // sbset - {7'b011_0100, 3'b001}: if (RV32B != RV32BNone) alu_operator_o = ALU_SBINV; // sbinv - {7'b010_0100, 3'b101}: if (RV32B != RV32BNone) alu_operator_o = ALU_SBEXT; // sbext + {7'b010_0100, 3'b001}: if (RV32B != RV32BNone) alu_operator_o = ALU_BCLR; // bclr + {7'b001_0100, 3'b001}: if (RV32B != RV32BNone) alu_operator_o = ALU_BSET; // bset + {7'b011_0100, 3'b001}: if (RV32B != RV32BNone) alu_operator_o = ALU_BINV; // binv + {7'b010_0100, 3'b101}: if (RV32B != RV32BNone) alu_operator_o = ALU_BEXT; // bext // RV32B zbf {7'b010_0100, 3'b111}: if (RV32B != RV32BNone) alu_operator_o = ALU_BFP; // bfp diff --git a/rtl/ibex_pkg.sv b/rtl/ibex_pkg.sv index 2f5de106..59255861 100644 --- a/rtl/ibex_pkg.sv +++ b/rtl/ibex_pkg.sv @@ -150,10 +150,10 @@ package ibex_pkg; // Single-Bit Operations // RV32B - ALU_SBSET, - ALU_SBCLR, - ALU_SBINV, - ALU_SBEXT, + ALU_BSET, + ALU_BCLR, + ALU_BINV, + ALU_BEXT, // Bit Compress / Decompress // RV32B diff --git a/rtl/ibex_tracer.sv b/rtl/ibex_tracer.sv index a184af70..bfe228ba 100644 --- a/rtl/ibex_tracer.sv +++ b/rtl/ibex_tracer.sv @@ -944,14 +944,14 @@ module ibex_tracer ( INSN_SEXTB: decode_r1_insn("sext.b"); INSN_SEXTH: decode_r1_insn("sext.h"); // RV32B - ZBS - INSN_SBCLRI: decode_i_insn("sbclri"); - INSN_SBSETI: decode_i_insn("sbseti"); - INSN_SBINVI: decode_i_insn("sbinvi"); - INSN_SBEXTI: decode_i_insn("sbexti"); - INSN_SBCLR: decode_r_insn("sbclr"); - INSN_SBSET: decode_r_insn("sbset"); - INSN_SBINV: decode_r_insn("sbinv"); - INSN_SBEXT: decode_r_insn("sbext"); + INSN_BCLRI: decode_i_insn("bclri"); + INSN_BSETI: decode_i_insn("bseti"); + INSN_BINVI: decode_i_insn("binvi"); + INSN_BEXTI: decode_i_insn("bexti"); + INSN_BCLR: decode_r_insn("bclr"); + INSN_BSET: decode_r_insn("bset"); + INSN_BINV: decode_r_insn("binv"); + INSN_BEXT: decode_r_insn("bext"); // RV32B - ZBE INSN_BDECOMPRESS: decode_r_insn("bdecompress"); INSN_BCOMPRESS: decode_r_insn("bcompress"); diff --git a/rtl/ibex_tracer_pkg.sv b/rtl/ibex_tracer_pkg.sv index a5e791bc..9ee48324 100644 --- a/rtl/ibex_tracer_pkg.sv +++ b/rtl/ibex_tracer_pkg.sv @@ -112,17 +112,17 @@ package ibex_tracer_pkg; parameter logic [31:0] INSN_PACKH = { 7'b0000100, 10'h?, 3'b111, 5'h?, {OPCODE_OP} }; // ZBS - parameter logic [31:0] INSN_SBCLRI = { 5'b01001, 12'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; - parameter logic [31:0] INSN_SBSETI = { 5'b00101, 12'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; - parameter logic [31:0] INSN_SBINVI = { 5'b01101, 12'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_BCLRI = { 5'b01001, 12'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_BSETI = { 5'b00101, 12'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_BINVI = { 5'b01101, 12'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; // Only log2(XLEN) bits of the immediate are used. For RV32, this means only the bits in - // instr[24:20] are effectively used. Whenever instr[26] is set, sbexti is instead decoded as fsri. - parameter logic [31:0] INSN_SBEXTI = { 5'b01001, 1'b0, 11'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + // instr[24:20] are effectively used. Whenever instr[26] is set, bexti is instead decoded as fsri. + parameter logic [31:0] INSN_BEXTI = { 5'b01001, 1'b0, 11'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; - parameter logic [31:0] INSN_SBCLR = { 7'b0100100, 10'h?, 3'b001, 5'h?, {OPCODE_OP} }; - parameter logic [31:0] INSN_SBSET = { 7'b0010100, 10'h?, 3'b001, 5'h?, {OPCODE_OP} }; - parameter logic [31:0] INSN_SBINV = { 7'b0110100, 10'h?, 3'b001, 5'h?, {OPCODE_OP} }; - parameter logic [31:0] INSN_SBEXT = { 7'b0100100, 10'h?, 3'b101, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_BCLR = { 7'b0100100, 10'h?, 3'b001, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_BSET = { 7'b0010100, 10'h?, 3'b001, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_BINV = { 7'b0110100, 10'h?, 3'b001, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_BEXT = { 7'b0100100, 10'h?, 3'b101, 5'h?, {OPCODE_OP} }; // ZBP // grevi