diff --git a/vendor/google_riscv-dv.lock.hjson b/vendor/google_riscv-dv.lock.hjson index 1c8649e9..8510c21c 100644 --- a/vendor/google_riscv-dv.lock.hjson +++ b/vendor/google_riscv-dv.lock.hjson @@ -9,6 +9,6 @@ upstream: { url: https://github.com/google/riscv-dv - rev: 00739df0ec744986934097bebcde3ebf5a4fdf81 + rev: 949552f964eec9d058c7c90889bdd5b80d1e60ad } } diff --git a/vendor/google_riscv-dv/scripts/instr_trace_compare.py b/vendor/google_riscv-dv/scripts/instr_trace_compare.py index 22c33d50..77a3f503 100644 --- a/vendor/google_riscv-dv/scripts/instr_trace_compare.py +++ b/vendor/google_riscv-dv/scripts/instr_trace_compare.py @@ -67,7 +67,7 @@ def compare_trace_csv(csv1, csv2, name1, name2, mismatch_cnt += 1 # print first few mismatches if mismatch_cnt <= mismatch_print_limit: - print("Mismatch:\n%s[%d] : %s" % + print("Mismatch[%d]:\n%s[%d] : %s" % (mismatch_cnt, name1, trace_2_index - 1, trace.get_trace_string())) print("%s[%d] : %s" % @@ -195,7 +195,7 @@ parser.add_argument("csv_file_2", type=str, help="Instruction trace 2 CSV") parser.add_argument("csv_name_1", type=str, help="Instruction trace 1 name") parser.add_argument("csv_name_2", type=str, help="Instruction trace 2 name") # optional arguments -parser.add_argument("--in_order_mode", type=int, default=0, +parser.add_argument("--in_order_mode", type=int, default=1, help="In order comparison mode") parser.add_argument("--gpr_update_coalescing_limit", type=int, default=1, help="Allow the core to merge multiple updates to the \ diff --git a/vendor/google_riscv-dv/src/riscv_asm_program_gen.sv b/vendor/google_riscv-dv/src/riscv_asm_program_gen.sv index b678e35c..bf118b07 100644 --- a/vendor/google_riscv-dv/src/riscv_asm_program_gen.sv +++ b/vendor/google_riscv-dv/src/riscv_asm_program_gen.sv @@ -311,6 +311,7 @@ class riscv_asm_program_gen extends uvm_object; instr_stream.push_back(str); // Init stack pointer to point to the end of the user stack str = {indent, "la sp, _user_stack_end"}; + setup_misa(); instr_stream.push_back(str); // Copy the instruction from data section to instruction section if (instr_binary.size() > 0) begin @@ -325,6 +326,30 @@ class riscv_asm_program_gen extends uvm_object; end endfunction + // Setup MISA based on supported extensions + virtual function setup_misa(); + bit [XLEN-1:0] misa; + misa[XLEN-1:XLEN-3] = (XLEN == 32) ? 1 : + (XLEN == 64) ? 2 : 3; + if (cfg.check_misa_init_val) begin + instr_stream.push_back({indent, "csrr x15, misa"}); + end + foreach (supported_isa[i]) begin + case (supported_isa[i]) inside + RV32C, RV64C, RV128C : misa[MISA_EXT_C] = 1'b1; + RV32I, RV64I, RV128I : misa[MISA_EXT_I] = 1'b1; + RV32M, RV64M : misa[MISA_EXT_M] = 1'b1; + default : `uvm_fatal(`gfn, $sformatf("%0s is not yet supported", supported_isa[i].name())) + endcase + end + if (SUPERVISOR_MODE inside {supported_privileged_mode}) begin + misa[MISA_EXT_S] = 1'b1; + end + instr_stream.push_back({indent, $sformatf("li x15, 0x%0x", misa)}); + instr_stream.push_back({indent, "csrw misa, x15"}); + endfunction + + // Initialize general purpose registers with random value virtual function void init_gpr(); string str; bit [DATA_WIDTH-1:0] reg_val; @@ -559,6 +584,11 @@ class riscv_asm_program_gen extends uvm_object; // Push user mode GPR to kernel stack before executing exception handling, this is to avoid // exception handling routine modify user program state unexpectedly push_gpr_to_kernel_stack(status, scratch, cfg.mstatus_mprv, instr); + // Checking xStatus can be optional if ISS (like spike) has different implementation of certain + // fields compared with the RTL processor. + if (cfg.check_xstatus) begin + instr = {instr, $sformatf("csrr x15, 0x%0x # %0s", status, status.name())}; + end instr = {instr, // Use scratch CSR to save a GPR value // Check if the exception is caused by an interrupt, if yes, jump to interrupt handler @@ -566,12 +596,11 @@ class riscv_asm_program_gen extends uvm_object; $sformatf("csrr a1, 0x%0x # %0s", cause, cause.name()), $sformatf("srli a1, a1, %0d", XLEN-1), $sformatf("bne a1, x0, %0smode_intr_handler", mode), - // The trap is caused by an exception, read back xCAUSE, xEPC, xSTATUS to see if these + // The trap is caused by an exception, read back xCAUSE, xEPC to see if these // CSR values are set properly. The checking is done by comparing against the log // generated by ISA simulator (spike). $sformatf("csrr a1, 0x%0x # %0s", cause, cause.name()), $sformatf("csrr x31, 0x%0x # %0s", epc, epc.name()), - $sformatf("csrr x29, 0x%0x # %0s", status, status.name()), // Breakpoint $sformatf("li a2, 0x%0x # BREAKPOINT", BREAKPOINT), "beq a1, a2, ebreak_handler", diff --git a/vendor/google_riscv-dv/src/riscv_instr_gen_config.sv b/vendor/google_riscv-dv/src/riscv_instr_gen_config.sv index 2993543d..8661a225 100644 --- a/vendor/google_riscv-dv/src/riscv_instr_gen_config.sv +++ b/vendor/google_riscv-dv/src/riscv_instr_gen_config.sv @@ -56,6 +56,12 @@ class riscv_instr_gen_config extends uvm_object; // Enable sfence.vma instruction rand bit enable_sfence; + // Options for privileged mode CSR checking + // Below checking can be made optional as the ISS implementation could be different with the + // processor. + bit check_misa_init_val = 1'b1; + bit check_xstatus = 1'b1; + //----------------------------------------------------------------------------- // Command line options or control knobs //----------------------------------------------------------------------------- diff --git a/vendor/google_riscv-dv/src/riscv_instr_pkg.sv b/vendor/google_riscv-dv/src/riscv_instr_pkg.sv index 40a47927..8b7eb504 100644 --- a/vendor/google_riscv-dv/src/riscv_instr_pkg.sv +++ b/vendor/google_riscv-dv/src/riscv_instr_pkg.sv @@ -615,6 +615,35 @@ package riscv_instr_pkg; STORE_AMO_PAGE_FAULT = 4'hF } exception_cause_t; + typedef enum int { + MISA_EXT_A = 0, + MISA_EXT_B, + MISA_EXT_C, + MISA_EXT_D, + MISA_EXT_E, + MISA_EXT_F, + MISA_EXT_G, + MISA_EXT_H, + MISA_EXT_I, + MISA_EXT_J, + MISA_EXT_K, + MISA_EXT_L, + MISA_EXT_M, + MISA_EXT_N, + MISA_EXT_O, + MISA_EXT_P, + MISA_EXT_Q, + MISA_EXT_R, + MISA_EXT_S, + MISA_EXT_T, + MISA_EXT_U, + MISA_EXT_V, + MISA_EXT_W, + MISA_EXT_X, + MISA_EXT_Y, + MISA_EXT_Z + } misa_ext_t; + `ifndef RISCV_CORE_SETTING `define RISCV_CORE_SETTING ../setting/riscv_core_setting.sv `endif