diff --git a/dv/uvm/riscv_dv_extension/riscvOVPsim.ic b/dv/uvm/riscv_dv_extension/riscvOVPsim.ic
index 6331d3dc..c74305e8 100644
--- a/dv/uvm/riscv_dv_extension/riscvOVPsim.ic
+++ b/dv/uvm/riscv_dv_extension/riscvOVPsim.ic
@@ -19,3 +19,4 @@
 --override riscvOVPsim/cpu/reset_address=0x80000080
 --override riscvOVPsim/cpu/simulateexceptions=T
 --override riscvOVPsim/cpu/wfi_is_nop=T
+--override riscvOVPsim/cpu/tval_ii_code=T
diff --git a/dv/uvm/riscv_dv_extension/testlist.yaml b/dv/uvm/riscv_dv_extension/testlist.yaml
index 1595ae48..f1377c11 100644
--- a/dv/uvm/riscv_dv_extension/testlist.yaml
+++ b/dv/uvm/riscv_dv_extension/testlist.yaml
@@ -237,7 +237,7 @@
     +no_fence=1
     +no_wfi=1
     +no_ebreak=1
-    +instr_cnt=6000
+    +instr_cnt=10000
     +randomize_csr=1
   rtl_test: core_ibex_debug_ebreak_test
   sim_opts: >
@@ -276,7 +276,7 @@
   iterations: 15
   gen_test: riscv_rand_instr_test
   gen_opts: >
-    +instr_cnt=6000
+    +instr_cnt=10000
     +require_signature_addr=1
     +enable_interrupt=1
     +randomize_csr=1
@@ -366,7 +366,7 @@
     +gen_debug_section=1
     +no_ebreak=1
     +no_branch_jump=1
-    +instr_cnt=6000
+    +instr_cnt=10000
     +no_csr_instr=1
     +no_fence=1
     +num_of_sub_program=0
@@ -387,8 +387,9 @@
   iterations: 15
   gen_test: riscv_rand_instr_test
   gen_opts: >
-    +instr_cnt=10000
     +num_of_sub_program=5
+    +enable_unaligned_load_store=1
+    +directed_instr_0=riscv_load_store_rand_instr_stream,10
   rtl_test: core_ibex_reset_test
   compare_opts:
     compare_final_value_only: 1
diff --git a/dv/uvm/tests/core_ibex_test_lib.sv b/dv/uvm/tests/core_ibex_test_lib.sv
index b1d705da..26ee8667 100644
--- a/dv/uvm/tests/core_ibex_test_lib.sv
+++ b/dv/uvm/tests/core_ibex_test_lib.sv
@@ -37,27 +37,32 @@ class core_ibex_reset_test extends core_ibex_base_test;
   `uvm_component_utils(core_ibex_reset_test)
   `uvm_component_new
 
+  bit [5:0] num_reset;
+
   virtual task send_stimulus();
     vseq.start(env.vseqr);
-    // Mid-test reset is possible in a wide range of times
-    clk_vif.wait_clks($urandom_range(20000, 200000));
-    fork
-      begin
-        dut_vif.fetch_enable = 1'b0;
-        clk_vif.reset();
-      end
-      begin
-        clk_vif.wait_clks(1);
-        // Flush FIFOs
-        item_collected_port.flush();
-        irq_collected_port.flush();
-        // Reset testbench state
-        env.reset();
-        load_binary_to_mem();
-      end
-    join
-    // Assert fetch_enable to have the core start executing from boot address
-    dut_vif.fetch_enable = 1'b1;
+    `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(num_reset, num_reset > 20;)
+    for (int i = 0; i < num_reset; i = i + 1) begin
+      // Mid-test reset is possible in a wide range of times
+      clk_vif.wait_clks($urandom_range(0, 50000));
+      fork
+        begin
+          dut_vif.fetch_enable = 1'b0;
+          clk_vif.reset();
+        end
+        begin
+          clk_vif.wait_clks(1);
+          // Flush FIFOs
+          item_collected_port.flush();
+          irq_collected_port.flush();
+          // Reset testbench state
+          env.reset();
+          load_binary_to_mem();
+        end
+      join
+      // Assert fetch_enable to have the core start executing from boot address
+      dut_vif.fetch_enable = 1'b1;
+    end
   endtask
 
 endclass