diff --git a/if_stage.sv b/if_stage.sv
index ed6ed21b..1c00ddf7 100644
--- a/if_stage.sv
+++ b/if_stage.sv
@@ -49,7 +49,6 @@ module if_stage
     output logic [31:0] instr_addr_o,          // address for instruction fetch
 
     // Forwarding ports - control signals
-    input  logic        compressed_instr_i,    // ID decoded a compressed instruction
     input  logic        force_nop_i,           // insert a NOP in the pipe
     input  logic [31:0] exception_pc_reg_i,    // address used to restore the program counter when the interrupt/exception is served
     input  logic [31:0] pc_from_hwloop_i,      // pc from hwloop start addr
diff --git a/riscv_core.sv b/riscv_core.sv
index 772b2e4d..5caffcb1 100644
--- a/riscv_core.sv
+++ b/riscv_core.sv
@@ -287,8 +287,6 @@ module riscv_core
       .branch_decision_i   ( branch_decision      ),
       .jump_target_i       ( jump_target          ),
 
-      .compressed_instr_i  ( compressed_instr     ),
-
       // pipeline stalls
       .stall_if_i          ( stall_if             ),
       .stall_id_i          ( stall_id             )
diff --git a/wb_stage.sv b/wb_stage.sv
index b10c5063..7a1220a5 100644
--- a/wb_stage.sv
+++ b/wb_stage.sv
@@ -56,9 +56,9 @@ module wb_stage
    always_comb
    begin : REGFILE_WDATA_MUX
       case (regfile_wdata_mux_sel_i)
-        //1'b0:  regfile_wdata_o <= sp_rdata_i;
-        1'b1:    regfile_wdata_o <= data_rdata_i;
-        default: regfile_wdata_o <= data_rdata_i;
+        //1'b0:  regfile_wdata_o = sp_rdata_i;
+        1'b1:    regfile_wdata_o = data_rdata_i;
+        default: regfile_wdata_o = data_rdata_i;
       endcase; // case (regfile_wdata_mux_sel_i)
    end