From fdfca50e168e142e5256969a1dd324e83f2b69a9 Mon Sep 17 00:00:00 2001
From: Markus Wegmann <atokulus@gmail.com>
Date: Thu, 12 Jan 2017 19:31:49 +0100
Subject: [PATCH] Begin tapeout of littleRISCV (misaligned RV32IC)

---
 THIS_CORE_IS_AUTOMATICALLY_GENERATATED!!!.txt | 3 +++
 1 file changed, 3 insertions(+)
 create mode 100644 THIS_CORE_IS_AUTOMATICALLY_GENERATATED!!!.txt

diff --git a/THIS_CORE_IS_AUTOMATICALLY_GENERATATED!!!.txt b/THIS_CORE_IS_AUTOMATICALLY_GENERATATED!!!.txt
new file mode 100644
index 00000000..5dba6af5
--- /dev/null
+++ b/THIS_CORE_IS_AUTOMATICALLY_GENERATATED!!!.txt
@@ -0,0 +1,3 @@
+This core export was automatically generated by ri5cly-manage.py
+
+Following settings were enabled: ['JUMP_IN_ID', 'SIMPLE_ALU', 'MERGE_ID_EX', 'NO_JUMP_ADDER']
\ No newline at end of file