FFFFFFFF # stimecmp readback
80000000 # menvcfg readback
00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts # skipping instruction address fault since they're impossible with compressed instrs enabled
00000001 # mcause from an instruction access fault
00000000 # mtval of faulting instruction address (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000002 # mcause from an Illegal instruction
00000000 # mtval of faulting instruction (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000003 # mcause from Breakpoint
80000168 # mtval of breakpoint instruction adress
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000004 # mcause from load address misaligned
80000171 # mtval of misaligned address
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000005 # mcause from load access
00000000 # mtval of accessed adress (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000006 # mcause from store misaligned
80000189 # mtval of address with misaligned store instr
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000007 # mcause from store access
00000000 # mtval of accessed address (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
0000000b # mcause from M mode ecall
00000000 # mtval of ecall (*** defined to be zero for now)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000008 # mcause from U mode ecall 
00000000 # mtval of ecall (*** defined to be zero for now)
00000080 # masked out mstatus.MPP = 00 (from U mode), mstatus.MPIE = 1, and mstatus.MIE = 0
00000009 # mcause from S mode ecall 
00000000 # mtval of ecall (*** defined to be zero for now)
00000880 # masked out mstatus.MPP = 01 (from S mode), mstatus.MPIE = 1, and mstatus.MIE = 0
0007ec01 # value to indicate successful vectoring on s soft interrupt 
80000001 # mcause value from s soft interrupt
00000000 # mtval for ssoft interrupt (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
0007ec03 # value to indicate successful vectoring on m soft interrupt 
80000003 # mcause value from m soft interrupt
00000000 # mtval for msoft interrupt (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
0007ec05 # value to indicate successful vectoring on s time interrupt 
80000005 # mcause value from s time interrupt
00000000 # mtval for stime interrupt (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
0007ec07 # value to indicate successful vectoring on m time interrupt 
80000007 # mcause value from m time interrupt
00000000 # mtval for mtime interrupt (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
0007ec09 # value to indicate successful vectoring on s ext interrupt 
80000009 # mcause value from s ext interrupt
00000000 # mtval for sext interrupt (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
0007ec0b # value to indicate successful vectoring on m ext interrupt 
8000000b # mcause value from m ext interrupt
00000000 # mtval for mext interrupt (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
0000b3fe # medeleg after attempted write of all 1's (only some bits are writeable)
00000222 # mideleg after attempted write of all 1's (only some bits are writeable) # skipping instruction address fault since they're impossible with compressed instrs enabled
00000001 # mcause from an instruction access fault
00000000 # mtval of faulting instruction address (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000002 # mcause from an Illegal instruction
00000000 # mtval of faulting instruction (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000003 # mcause from Breakpoint
80000168 # mtval of breakpoint instruction adress
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000004 # mcause from load address misaligned
80000171 # mtval of misaligned address
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000005 # mcause from load access
00000000 # mtval of accessed adress (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000006 # mcause from store misaligned
80000189 # mtval of address with misaligned store instr
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000007 # mcause from store access
00000000 # mtval of accessed address (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
0000000b # mcause from M mode ecall
00000000 # mtval of ecall (*** defined to be zero for now)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
0007ec03 # value to indicate successful vectoring on m soft interrupt 
80000003 # mcause value from m soft interrupt
00000000 # mtval for msoft interrupt (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
0007ec07 # value to indicate successful vectoring on m time interrupt 
80000007 # mcause value from m time interrupt
00000000 # mtval for mtime interrupt (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
0007ec0b # value to indicate successful vectoring on m ext interrupt 
8000000b # mcause value from m ext interrupt
00000000 # mtval for mext interrupt (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
0000000b # mcause from M mode ecall from test termination
00000000 # mtval of ecall (*** defined to be zero for now)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
