# See LICENSE.incore for details
metadata:
  all_regs: &all_regs "['x'+str(x) for x in range(0,32 if 'e' not in base_isa else 16)]"
  all_fregs: &all_fregs "['f'+str(x) for x in range(0,32 if 'e' not in base_isa else 16)]"
  all_regs_mx0: &all_regs_mx0 "['x'+str(x) for x in range(1,32 if 'e' not in base_isa else 16)]"
  c_regs: &c_regs "['x'+str(x) for x in range(8,16)]"
  pair_regs: &pair_regs "['x'+str(x) for x in range(2,32 if 'e' not in base_isa else 16, 2 if xlen == 32 else 1)]"
  rv32rv64pair_regs: &rv32rv64pair_regs "['x'+str(x) for x in range(2,30 if 'e' not in base_isa else 16, 2)]"

aes32dsi:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))'
  xlen: [32]
  std_op:
  isa: 
    - IZk
    - IZkn
    - IZknd
  formattype: 'bsformat'
  template: |-

    // $comment
    // opcode: $inst; rd:$rd; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; immval:$imm_val
    TEST_RRI_OP($inst, $rd, $rs1, $rs2, $imm_val, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
    
aes32dsmi:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))'
  xlen: [32]
  std_op:
  isa: 
    - IZk
    - IZkn
    - IZknd
  formattype: 'bsformat'
  template: |-

    // $comment
    // opcode: $inst; rd:$rd; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; immval:$imm_val
    TEST_RRI_OP($inst, $rd, $rs1, $rs2, $imm_val, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
    
aes32esi:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))'
  xlen: [32]
  std_op:
  isa: 
    - IZk
    - IZkn
    - IZkne
  formattype: 'bsformat'
  template: |-

    // $comment
    // opcode: $inst; rd:$rd; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; immval:$imm_val
    TEST_RRI_OP($inst, $rd, $rs1, $rs2, $imm_val, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
    
aes32esmi:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))'
  xlen: [32]
  std_op:
  isa: 
    - IZk
    - IZkn
    - IZkne
  formattype: 'bsformat'
  template: |-

    // $comment
    // opcode: $inst; rd:$rd; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; immval:$imm_val
    TEST_RRI_OP($inst, $rd, $rs1, $rs2, $imm_val, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
    
sm4ed:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))'
  xlen: [32,64]
  std_op:
  isa: 
    - IZks
    - IZksed
  formattype: 'bsformat'
  template: |-

    // $comment
    // opcode: $inst; rd:$rd; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; immval:$imm_val
    TEST_RRI_OP($inst, $rd, $rs1, $rs2, $imm_val, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
    
sm4ks:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))'
  xlen: [32,64]
  std_op:
  isa: 
    - IZks
    - IZksed
  formattype: 'bsformat'
  template: |-

    // $comment
    // opcode: $inst; rd:$rd; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; immval:$imm_val
    TEST_RRI_OP($inst, $rd, $rs1, $rs2, $imm_val, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

sha256sig0:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZk
    - IZkn
    - IZknh
  formattype: 'kformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    LI($rs1,$rs1_val)
    sha256sig0 $rd, $rs1
    SREG $rd, $offset($swreg)
    RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)
    
sha256sig1:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZk
    - IZkn
    - IZknh
  formattype: 'kformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    LI($rs1,$rs1_val)
    sha256sig1 $rd, $rs1
    SREG $rd, $offset($swreg)
    RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)
    
sha256sum0:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZk
    - IZkn
    - IZknh
  formattype: 'kformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    LI($rs1,$rs1_val)
    sha256sum0 $rd, $rs1
    SREG $rd, $offset($swreg)
    RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)

sha256sum1:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZk
    - IZkn
    - IZknh
  formattype: 'kformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    LI($rs1,$rs1_val)
    sha256sum1 $rd, $rs1
    SREG $rd, $offset($swreg)
    RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)

sm3p0:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZks
    - IZksh
  formattype: 'kformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    LI($rs1,$rs1_val)
    sm3p0 $rd, $rs1
    SREG $rd, $offset($swreg)
    RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)

sm3p1:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZks
    - IZksh
  formattype: 'kformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    LI($rs1,$rs1_val)
    sm3p1 $rd, $rs1
    SREG $rd, $offset($swreg)
    RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)

sha512sig0h:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32]
  std_op:
  isa: 
    - IZk
    - IZkn
    - IZknh
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

sha512sig0l:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32]
  std_op:
  isa: 
    - IZk
    - IZkn
    - IZknh
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)    
    
sha512sig1h:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32]
  std_op:
  isa: 
    - IZk
    - IZkn
    - IZknh
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)    

sha512sig1l:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32]
  std_op:
  isa: 
    - IZk
    - IZkn
    - IZknh
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
    
sha512sum0r:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32]
  std_op:
  isa: 
    - IZk
    - IZkn
    - IZknh
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
    
sha512sum1r:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32]
  std_op:
  isa: 
    - IZk
    - IZkn
    - IZknh
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

rol:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  operation: 'hex((rs1_val << (rs2_val%xlen)) & (2**(xlen)-1))'
  isa: 
    - IZbb
    - IZbkb
    - IZk
    - IZkn
    - IZks
    - IB
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
    
rev.b:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op: grevi
  isa: 
    - I
  formattype: 'kformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    LI($rs1,$rs1_val)
    grevi $rd, $rs1, 7
    SREG $rd, $offset($swreg)
    RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)
    
zip:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32]
  std_op: shfli
  isa: 
    - IZk
    - IZbkb
    - IZkn
    - IZks
  formattype: 'kformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    LI($rs1,$rs1_val)
    zip $rd, $rs1
    SREG $rd, $offset($swreg)
    RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)

unzip:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32]
  std_op: unshfli
  isa: 
    - IZk
    - IZbkb
    - IZkn
    - IZks
  formattype: 'kformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    LI($rs1,$rs1_val)
    unzip $rd, $rs1
    SREG $rd, $offset($swreg)
    RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)

pack:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZk
    - IZbkb
    - IZkn
    - IZks
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

packu:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - I
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

packh:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZk
    - IZbkb
    - IZkn
    - IZks
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

xperm.n:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - I
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

xperm.b:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - I
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

aes64ds:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - IZk
    - IZkn
    - IZknd
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
    
aes64dsm:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - IZk
    - IZkn
    - IZknd
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
    
aes64es:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - IZk
    - IZkn
    - IZkne
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
    
aes64esm:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - IZk
    - IZkn
    - IZkne
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
    
aes64ks1i:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - IZk
    - IZkn
    - IZknd
    - IZkne
  formattype: 'iformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  imm_val_data: 'gen_usign_dataset(ceil(log(xlen,2)))'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
    
aes64ks2:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - IZk
    - IZkn
    - IZknd
    - IZkne
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
    
sha512sig0:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - IZk
    - IZkn
    - IZknh
  formattype: 'kformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    LI($rs1,$rs1_val)
    sha512sig0 $rd, $rs1
    SREG $rd, $offset($swreg)
    RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)

sha512sig1:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - IZk
    - IZkn
    - IZknh
  formattype: 'kformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    LI($rs1,$rs1_val)
    sha512sig1 $rd, $rs1
    SREG $rd, $offset($swreg)
    RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)
    
sha512sum0:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - IZk
    - IZkn
    - IZknh
  formattype: 'kformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    LI($rs1,$rs1_val)
    sha512sum0 $rd, $rs1
    SREG $rd, $offset($swreg)
    RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)
    
sha512sum1:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - IZk
    - IZkn
    - IZknh
  formattype: 'kformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    LI($rs1,$rs1_val)
    sha512sum1 $rd, $rs1
    SREG $rd, $offset($swreg)
    RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)
    
aes64im:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - IZk
    - IZkn
    - IZknd
  formattype: 'kformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    LI($rs1,$rs1_val)
    aes64im $rd, $rs1
    SREG $rd, $offset($swreg)
    RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)
    
rolw:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - IZbb
    - IZbkb
    - IZk
    - IZkn
    - IZks
    - IB
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
    
rev8.w:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op: grevi
  isa: 
    - I
  formattype: 'kformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    LI($rs1,$rs1_val)
    grevi  $rd, $rs1, 24
    SREG $rd, $offset($swreg)
    RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)

packw:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - IZk
    - IZbkb
    - IZkn
    - IZks
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

packuw:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - I
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

add.uw:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - IZba
    - IB
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_bitmanip_dataset(xlen,False)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_bitmanip_dataset(xlen,False)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
    
sh1add:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZba
    - IB
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen) + gen_bitmanip_dataset(xlen,True)'
  rs2_val_data: 'gen_sign_dataset(xlen) + gen_bitmanip_dataset(xlen,True)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
    
sh1add.uw:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - IZba
    - IB
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)'
  rs2_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
    
sh2add:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZba
    - IB
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_bitmanip_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_bitmanip_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
    
sh2add.uw:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - IZba
    - IB
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)'
  rs2_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
    
sh3add:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZba
    - IB
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_bitmanip_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_bitmanip_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
    
sh3add.uw:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - IZba
    - IB
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)'
  rs2_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
    
slli.uw:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - IZba
    - IB
  formattype: 'iformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  operation: 'hex(sign_extend((rs1_val << imm_val) , 32))'
  rs1_val_data: 'gen_usign_dataset(xlen)+ gen_bitmanip_dataset(xlen,False)'
  imm_val_data: 'gen_usign_dataset(5)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)

andn:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZbb
    - IZbkb
    - IZk
    - IZkn
    - IZks
    - IB
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  operation: 'hex((rs1_val & rs2_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)'
  rs2_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

# 3.1.1. 16-bit Addition & Subtraction Instructions

add16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

radd16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

uradd16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  rs2_h0_val_data: 'gen_usign_dataset(16)'
  rs2_h1_val_data: 'gen_usign_dataset(16)'
  rs2_h2_val_data: 'gen_usign_dataset(16)'
  rs2_h3_val_data: 'gen_usign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

kadd16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

ukadd16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  rs2_h0_val_data: 'gen_usign_dataset(16)'
  rs2_h1_val_data: 'gen_usign_dataset(16)'
  rs2_h2_val_data: 'gen_usign_dataset(16)'
  rs2_h3_val_data: 'gen_usign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

sub16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)


rsub16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)


ursub16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  rs2_h0_val_data: 'gen_usign_dataset(16)'
  rs2_h1_val_data: 'gen_usign_dataset(16)'
  rs2_h2_val_data: 'gen_usign_dataset(16)'
  rs2_h3_val_data: 'gen_usign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

ksub16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

uksub16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  rs2_h0_val_data: 'gen_usign_dataset(16)'
  rs2_h1_val_data: 'gen_usign_dataset(16)'
  rs2_h2_val_data: 'gen_usign_dataset(16)'
  rs2_h3_val_data: 'gen_usign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

cras16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

rcras16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)


urcras16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  rs2_h0_val_data: 'gen_usign_dataset(16)'
  rs2_h1_val_data: 'gen_usign_dataset(16)'
  rs2_h2_val_data: 'gen_usign_dataset(16)'
  rs2_h3_val_data: 'gen_usign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

kcras16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

clz:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZbb
    - IB
  formattype: 'kformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_usign_dataset(xlen)+gen_sign_dataset(xlen)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)  
    
clzw:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - IZbb
    - IB
  formattype: 'kformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)

cpop:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZbb
    - IB
  formattype: 'kformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_usign_dataset(xlen)+gen_sign_dataset(xlen)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) 
    
cpopw:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - IZbb
    - IB
  formattype: 'kformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)  
    
ctz:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZbb
    - IB
  formattype: 'kformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_usign_dataset(xlen)+gen_sign_dataset(xlen)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)  
    
ctzw:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - IZbb
    - IB
  formattype: 'kformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_usign_dataset(xlen)+gen_sign_dataset(xlen)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)
    
max:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZbb
    - IB
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen) + gen_bitmanip_dataset(xlen,True)'
  rs2_val_data: 'gen_sign_dataset(xlen) + gen_bitmanip_dataset(xlen,True)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

ukcras16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  rs2_h0_val_data: 'gen_usign_dataset(16)'
  rs2_h1_val_data: 'gen_usign_dataset(16)'
  rs2_h2_val_data: 'gen_usign_dataset(16)'
  rs2_h3_val_data: 'gen_usign_dataset(16)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) 
    
maxu:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZbb
    - IB
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)'
  rs2_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

crsa16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
    
min:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZbb
    - IB
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen) + gen_bitmanip_dataset(xlen,True)'
  rs2_val_data: 'gen_sign_dataset(xlen) + gen_bitmanip_dataset(xlen,True)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

rcrsa16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
    
minu:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZbb
    - IB
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)'
  rs2_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

urcrsa16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  rs2_h0_val_data: 'gen_usign_dataset(16)'
  rs2_h1_val_data: 'gen_usign_dataset(16)'
  rs2_h2_val_data: 'gen_usign_dataset(16)'
  rs2_h3_val_data: 'gen_usign_dataset(16)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

kcrsa16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

orc.b:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op: orc.b
  isa: 
    - IZbb
    - IB
  formattype: 'kformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)+[16909320,33818625,67633410,134283780,72624976414508040,145249888404506625,290483284134592770,576744443617542660]'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) 

orn:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa:
    - IZbb
    - IZbkb
    - IZk
    - IZkn
    - IZks
    - IB
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)'
  rs2_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

ukcrsa16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  rs2_h0_val_data: 'gen_usign_dataset(16)'
  rs2_h1_val_data: 'gen_usign_dataset(16)'
  rs2_h2_val_data: 'gen_usign_dataset(16)'
  rs2_h3_val_data: 'gen_usign_dataset(16)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

stas16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

rstas16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
    
rev8:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op: grevi
  isa: 
    - IZbb
    - IZbkb
    - IZk
    - IZkn
    - IZks
    - IB
  formattype: 'kformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)+gen_bitmanip_dataset(xlen,False)+[16909320,33818625,67633410,134283780,72624976414508040,145249888404506625,290483284134592770,576744443617542660]'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    LI($rs1,$rs1_val)
    rev8 $rd, $rs1
    RVTEST_SIGUPD($swreg,$rd,$offset)
    RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)


ror:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZbb
    - IZbkb
    - IZk
    - IZkn
    - IZks
    - IB
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
  rs2_val_data: 'gen_usign_dataset(ceil(log(xlen,2)))'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

urstas16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  rs2_h0_val_data: 'gen_usign_dataset(16)'
  rs2_h1_val_data: 'gen_usign_dataset(16)'
  rs2_h2_val_data: 'gen_usign_dataset(16)'
  rs2_h3_val_data: 'gen_usign_dataset(16)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

kstas16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

ukstas16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  rs2_h0_val_data: 'gen_usign_dataset(16)'
  rs2_h1_val_data: 'gen_usign_dataset(16)'
  rs2_h2_val_data: 'gen_usign_dataset(16)'
  rs2_h3_val_data: 'gen_usign_dataset(16)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

rori:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZbb
    - IZbkb
    - IZk
    - IZkn
    - IZks
    - IB
  formattype: 'iformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_usign_dataset(ceil(log(xlen,2)))'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)

roriw:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - IZbb
    - IZbkb
    - IZk
    - IZkn
    - IZks
    - IB
  formattype: 'iformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_usign_dataset(ceil(log(xlen,2)))'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)

rorw:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - IZbb
    - IZbkb
    - IZk
    - IZkn
    - IZks
    - IB
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)'
  rs2_val_data: 'gen_usign_dataset(ceil(log(xlen,2)))'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

stsa16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

rstsa16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

urstsa16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  rs2_h0_val_data: 'gen_usign_dataset(16)'
  rs2_h1_val_data: 'gen_usign_dataset(16)'
  rs2_h2_val_data: 'gen_usign_dataset(16)'
  rs2_h3_val_data: 'gen_usign_dataset(16)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

sext.b:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZbb
    - IB
  formattype: 'kformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)  
    
sext.h:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZbb
    - IB
  formattype: 'kformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)+[65408]'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) 

xnor:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa:
    - IZbb
    - IZbkb
    - IZk
    - IZkn
    - IZks
    - IB
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_usign_dataset(xlen)+gen_bitmanip_dataset(xlen,False)'
  rs2_val_data: 'gen_usign_dataset(xlen)+gen_bitmanip_dataset(xlen,False)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

kstsa16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

ukstsa16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  rs2_h0_val_data: 'gen_usign_dataset(16)'
  rs2_h1_val_data: 'gen_usign_dataset(16)'
  rs2_h2_val_data: 'gen_usign_dataset(16)'
  rs2_h3_val_data: 'gen_usign_dataset(16)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
  
zext.h:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZbb
    - IB
  formattype: 'kformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_usign_dataset(xlen)+[65408]'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)

clmul:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa:
    - IZbc
    - IZbkc
    - IZk
    - IZkn
    - IZks
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)


# 3.1.2. 8-bit Addition & Subtraction Instructions

add8:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_sign_dataset(8)'
  rs1_b1_val_data: 'gen_sign_dataset(8)'
  rs1_b2_val_data: 'gen_sign_dataset(8)'
  rs1_b3_val_data: 'gen_sign_dataset(8)'
  rs1_b4_val_data: 'gen_sign_dataset(8)'
  rs1_b5_val_data: 'gen_sign_dataset(8)'
  rs1_b6_val_data: 'gen_sign_dataset(8)'
  rs1_b7_val_data: 'gen_sign_dataset(8)'
  rs2_b0_val_data: 'gen_sign_dataset(8)'
  rs2_b1_val_data: 'gen_sign_dataset(8)'
  rs2_b2_val_data: 'gen_sign_dataset(8)'
  rs2_b3_val_data: 'gen_sign_dataset(8)'
  rs2_b4_val_data: 'gen_sign_dataset(8)'
  rs2_b5_val_data: 'gen_sign_dataset(8)'
  rs2_b6_val_data: 'gen_sign_dataset(8)'
  rs2_b7_val_data: 'gen_sign_dataset(8)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

clmulh:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa:
    - IZbc
    - IZbkc
    - IZk
    - IZkn
    - IZks
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)


radd8:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_sign_dataset(8)'
  rs1_b1_val_data: 'gen_sign_dataset(8)'
  rs1_b2_val_data: 'gen_sign_dataset(8)'
  rs1_b3_val_data: 'gen_sign_dataset(8)'
  rs1_b4_val_data: 'gen_sign_dataset(8)'
  rs1_b5_val_data: 'gen_sign_dataset(8)'
  rs1_b6_val_data: 'gen_sign_dataset(8)'
  rs1_b7_val_data: 'gen_sign_dataset(8)'
  rs2_b0_val_data: 'gen_sign_dataset(8)'
  rs2_b1_val_data: 'gen_sign_dataset(8)'
  rs2_b2_val_data: 'gen_sign_dataset(8)'
  rs2_b3_val_data: 'gen_sign_dataset(8)'
  rs2_b4_val_data: 'gen_sign_dataset(8)'
  rs2_b5_val_data: 'gen_sign_dataset(8)'
  rs2_b6_val_data: 'gen_sign_dataset(8)'
  rs2_b7_val_data: 'gen_sign_dataset(8)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)


clmulr:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZbc
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

uradd8:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_usign_dataset(8)'
  rs1_b1_val_data: 'gen_usign_dataset(8)'
  rs1_b2_val_data: 'gen_usign_dataset(8)'
  rs1_b3_val_data: 'gen_usign_dataset(8)'
  rs1_b4_val_data: 'gen_usign_dataset(8)'
  rs1_b5_val_data: 'gen_usign_dataset(8)'
  rs1_b6_val_data: 'gen_usign_dataset(8)'
  rs1_b7_val_data: 'gen_usign_dataset(8)'
  rs2_b0_val_data: 'gen_usign_dataset(8)'
  rs2_b1_val_data: 'gen_usign_dataset(8)'
  rs2_b2_val_data: 'gen_usign_dataset(8)'
  rs2_b3_val_data: 'gen_usign_dataset(8)'
  rs2_b4_val_data: 'gen_usign_dataset(8)'
  rs2_b5_val_data: 'gen_usign_dataset(8)'
  rs2_b6_val_data: 'gen_usign_dataset(8)'
  rs2_b7_val_data: 'gen_usign_dataset(8)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

bclr:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZbs
    - IB
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'zerotoxlen(xlen)+gen_usign_dataset(xlen)+[-1]'
  rs2_val_data: 'zerotoxlen(xlen)+gen_usign_dataset(xlen)+[-1]'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)


kadd8:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_sign_dataset(8)'
  rs1_b1_val_data: 'gen_sign_dataset(8)'
  rs1_b2_val_data: 'gen_sign_dataset(8)'
  rs1_b3_val_data: 'gen_sign_dataset(8)'
  rs1_b4_val_data: 'gen_sign_dataset(8)'
  rs1_b5_val_data: 'gen_sign_dataset(8)'
  rs1_b6_val_data: 'gen_sign_dataset(8)'
  rs1_b7_val_data: 'gen_sign_dataset(8)'
  rs2_b0_val_data: 'gen_sign_dataset(8)'
  rs2_b1_val_data: 'gen_sign_dataset(8)'
  rs2_b2_val_data: 'gen_sign_dataset(8)'
  rs2_b3_val_data: 'gen_sign_dataset(8)'
  rs2_b4_val_data: 'gen_sign_dataset(8)'
  rs2_b5_val_data: 'gen_sign_dataset(8)'
  rs2_b6_val_data: 'gen_sign_dataset(8)'
  rs2_b7_val_data: 'gen_sign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

ukadd8:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_usign_dataset(8)'
  rs1_b1_val_data: 'gen_usign_dataset(8)'
  rs1_b2_val_data: 'gen_usign_dataset(8)'
  rs1_b3_val_data: 'gen_usign_dataset(8)'
  rs1_b4_val_data: 'gen_usign_dataset(8)'
  rs1_b5_val_data: 'gen_usign_dataset(8)'
  rs1_b6_val_data: 'gen_usign_dataset(8)'
  rs1_b7_val_data: 'gen_usign_dataset(8)'
  rs2_b0_val_data: 'gen_usign_dataset(8)'
  rs2_b1_val_data: 'gen_usign_dataset(8)'
  rs2_b2_val_data: 'gen_usign_dataset(8)'
  rs2_b3_val_data: 'gen_usign_dataset(8)'
  rs2_b4_val_data: 'gen_usign_dataset(8)'
  rs2_b5_val_data: 'gen_usign_dataset(8)'
  rs2_b6_val_data: 'gen_usign_dataset(8)'
  rs2_b7_val_data: 'gen_usign_dataset(8)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
    
bclri:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZbs
    - IB
  formattype: 'iformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'zerotoxlen(xlen)+[-1]'
  imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
    
bext:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZbs
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'zerotoxlen(xlen)+gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'zerotoxlen(xlen)+gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

sub8:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_sign_dataset(8)'
  rs1_b1_val_data: 'gen_sign_dataset(8)'
  rs1_b2_val_data: 'gen_sign_dataset(8)'
  rs1_b3_val_data: 'gen_sign_dataset(8)'
  rs1_b4_val_data: 'gen_sign_dataset(8)'
  rs1_b5_val_data: 'gen_sign_dataset(8)'
  rs1_b6_val_data: 'gen_sign_dataset(8)'
  rs1_b7_val_data: 'gen_sign_dataset(8)'
  rs2_b0_val_data: 'gen_sign_dataset(8)'
  rs2_b1_val_data: 'gen_sign_dataset(8)'
  rs2_b2_val_data: 'gen_sign_dataset(8)'
  rs2_b3_val_data: 'gen_sign_dataset(8)'
  rs2_b4_val_data: 'gen_sign_dataset(8)'
  rs2_b5_val_data: 'gen_sign_dataset(8)'
  rs2_b6_val_data: 'gen_sign_dataset(8)'
  rs2_b7_val_data: 'gen_sign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

rsub8:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_sign_dataset(8)'
  rs1_b1_val_data: 'gen_sign_dataset(8)'
  rs1_b2_val_data: 'gen_sign_dataset(8)'
  rs1_b3_val_data: 'gen_sign_dataset(8)'
  rs1_b4_val_data: 'gen_sign_dataset(8)'
  rs1_b5_val_data: 'gen_sign_dataset(8)'
  rs1_b6_val_data: 'gen_sign_dataset(8)'
  rs1_b7_val_data: 'gen_sign_dataset(8)'
  rs2_b0_val_data: 'gen_sign_dataset(8)'
  rs2_b1_val_data: 'gen_sign_dataset(8)'
  rs2_b2_val_data: 'gen_sign_dataset(8)'
  rs2_b3_val_data: 'gen_sign_dataset(8)'
  rs2_b4_val_data: 'gen_sign_dataset(8)'
  rs2_b5_val_data: 'gen_sign_dataset(8)'
  rs2_b6_val_data: 'gen_sign_dataset(8)'
  rs2_b7_val_data: 'gen_sign_dataset(8)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

    
bexti:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZbs
    - IB
  formattype: 'iformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'zerotoxlen(xlen)+gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
    
binv:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZbs
    - IB
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'zerotoxlen(xlen)+gen_usign_dataset(xlen)+gen_sign_dataset(xlen)'
  rs2_val_data: 'zerotoxlen(xlen)+gen_usign_dataset(xlen)+gen_sign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)


ursub8:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_usign_dataset(8)'
  rs1_b1_val_data: 'gen_usign_dataset(8)'
  rs1_b2_val_data: 'gen_usign_dataset(8)'
  rs1_b3_val_data: 'gen_usign_dataset(8)'
  rs1_b4_val_data: 'gen_usign_dataset(8)'
  rs1_b5_val_data: 'gen_usign_dataset(8)'
  rs1_b6_val_data: 'gen_usign_dataset(8)'
  rs1_b7_val_data: 'gen_usign_dataset(8)'
  rs2_b0_val_data: 'gen_usign_dataset(8)'
  rs2_b1_val_data: 'gen_usign_dataset(8)'
  rs2_b2_val_data: 'gen_usign_dataset(8)'
  rs2_b3_val_data: 'gen_usign_dataset(8)'
  rs2_b4_val_data: 'gen_usign_dataset(8)'
  rs2_b5_val_data: 'gen_usign_dataset(8)'
  rs2_b6_val_data: 'gen_usign_dataset(8)'
  rs2_b7_val_data: 'gen_usign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)


ksub8:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_sign_dataset(8)'
  rs1_b1_val_data: 'gen_sign_dataset(8)'
  rs1_b2_val_data: 'gen_sign_dataset(8)'
  rs1_b3_val_data: 'gen_sign_dataset(8)'
  rs1_b4_val_data: 'gen_sign_dataset(8)'
  rs1_b5_val_data: 'gen_sign_dataset(8)'
  rs1_b6_val_data: 'gen_sign_dataset(8)'
  rs1_b7_val_data: 'gen_sign_dataset(8)'
  rs2_b0_val_data: 'gen_sign_dataset(8)'
  rs2_b1_val_data: 'gen_sign_dataset(8)'
  rs2_b2_val_data: 'gen_sign_dataset(8)'
  rs2_b3_val_data: 'gen_sign_dataset(8)'
  rs2_b4_val_data: 'gen_sign_dataset(8)'
  rs2_b5_val_data: 'gen_sign_dataset(8)'
  rs2_b6_val_data: 'gen_sign_dataset(8)'
  rs2_b7_val_data: 'gen_sign_dataset(8)'
  template: |-
    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

    
binvi:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZbs
    - IB
  formattype: 'iformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'zerotoxlen(xlen)+gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
    
bset:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZbs
    - IB
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'zerotoxlen(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'zerotoxlen(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

uksub8:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_usign_dataset(8)'
  rs1_b1_val_data: 'gen_usign_dataset(8)'
  rs1_b2_val_data: 'gen_usign_dataset(8)'
  rs1_b3_val_data: 'gen_usign_dataset(8)'
  rs1_b4_val_data: 'gen_usign_dataset(8)'
  rs1_b5_val_data: 'gen_usign_dataset(8)'
  rs1_b6_val_data: 'gen_usign_dataset(8)'
  rs1_b7_val_data: 'gen_usign_dataset(8)'
  rs2_b0_val_data: 'gen_usign_dataset(8)'
  rs2_b1_val_data: 'gen_usign_dataset(8)'
  rs2_b2_val_data: 'gen_usign_dataset(8)'
  rs2_b3_val_data: 'gen_usign_dataset(8)'
  rs2_b4_val_data: 'gen_usign_dataset(8)'
  rs2_b5_val_data: 'gen_usign_dataset(8)'
  rs2_b6_val_data: 'gen_usign_dataset(8)'
  rs2_b7_val_data: 'gen_usign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

# 3.1.3. 16-bit Shift Instructions

sra16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'pshrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_val_data: 'gen_usign_dataset(ceil(log(16,2)))'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

srai16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phriformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  imm_val_data: 'gen_imm_dataset(4)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)

sra16.u:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'pshrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_val_data: 'gen_usign_dataset(ceil(log(16,2)))'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

srai16.u:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phriformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  imm_val_data: 'gen_imm_dataset(4)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)

srl16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'pshrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  rs2_val_data: 'gen_usign_dataset(ceil(log(16,2)))'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

srli16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phriformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  imm_val_data: 'gen_imm_dataset(4)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)

srl16.u:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'pshrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  rs2_val_data: 'gen_usign_dataset(ceil(log(16,2)))'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

srli16.u:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phriformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  imm_val_data: 'gen_imm_dataset(4)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)

sll16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'pshrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  rs2_val_data: 'gen_usign_dataset(ceil(log(16,2)))'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

slli16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phriformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  imm_val_data: 'gen_imm_dataset(4)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)

ksll16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'pshrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_val_data: 'gen_usign_dataset(ceil(log(16,2)))'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kslli16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phriformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  imm_val_data: 'gen_imm_dataset(4)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_PKIMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $rs1, $swreg, $offset, $testreg)

kslra16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16,xlen
  formattype: 'pshrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_val_data: 'gen_sign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kslra16.u:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16,xlen
  formattype: 'pshrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  rs2_val_data: 'gen_sign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

# 3.1.4. 8-bit Shift Instructions

sra8:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'psbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_sign_dataset(8)'
  rs1_b1_val_data: 'gen_sign_dataset(8)'
  rs1_b2_val_data: 'gen_sign_dataset(8)'
  rs1_b3_val_data: 'gen_sign_dataset(8)'
  rs1_b4_val_data: 'gen_sign_dataset(8)'
  rs1_b5_val_data: 'gen_sign_dataset(8)'
  rs1_b6_val_data: 'gen_sign_dataset(8)'
  rs1_b7_val_data: 'gen_sign_dataset(8)'
  rs2_val_data: 'gen_usign_dataset(ceil(log(8,2)))'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

srai8:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbriformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_sign_dataset(8)'
  rs1_b1_val_data: 'gen_sign_dataset(8)'
  rs1_b2_val_data: 'gen_sign_dataset(8)'
  rs1_b3_val_data: 'gen_sign_dataset(8)'
  rs1_b4_val_data: 'gen_sign_dataset(8)'
  rs1_b5_val_data: 'gen_sign_dataset(8)'
  rs1_b6_val_data: 'gen_sign_dataset(8)'
  rs1_b7_val_data: 'gen_sign_dataset(8)'
  imm_val_data: 'gen_imm_dataset(3)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)

sra8.u:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'psbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_sign_dataset(8)'
  rs1_b1_val_data: 'gen_sign_dataset(8)'
  rs1_b2_val_data: 'gen_sign_dataset(8)'
  rs1_b3_val_data: 'gen_sign_dataset(8)'
  rs1_b4_val_data: 'gen_sign_dataset(8)'
  rs1_b5_val_data: 'gen_sign_dataset(8)'
  rs1_b6_val_data: 'gen_sign_dataset(8)'
  rs1_b7_val_data: 'gen_sign_dataset(8)'
  rs2_val_data: 'gen_usign_dataset(ceil(log(8,2)))'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

srai8.u:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbriformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_sign_dataset(8)'
  rs1_b1_val_data: 'gen_sign_dataset(8)'
  rs1_b2_val_data: 'gen_sign_dataset(8)'
  rs1_b3_val_data: 'gen_sign_dataset(8)'
  rs1_b4_val_data: 'gen_sign_dataset(8)'
  rs1_b5_val_data: 'gen_sign_dataset(8)'
  rs1_b6_val_data: 'gen_sign_dataset(8)'
  rs1_b7_val_data: 'gen_sign_dataset(8)'
  imm_val_data: 'gen_imm_dataset(3)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)

srl8:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'psbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_usign_dataset(8)'
  rs1_b1_val_data: 'gen_usign_dataset(8)'
  rs1_b2_val_data: 'gen_usign_dataset(8)'
  rs1_b3_val_data: 'gen_usign_dataset(8)'
  rs1_b4_val_data: 'gen_usign_dataset(8)'
  rs1_b5_val_data: 'gen_usign_dataset(8)'
  rs1_b6_val_data: 'gen_usign_dataset(8)'
  rs1_b7_val_data: 'gen_usign_dataset(8)'
  rs2_val_data: 'gen_usign_dataset(ceil(log(8,2)))'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

srli8:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbriformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_usign_dataset(8)'
  rs1_b1_val_data: 'gen_usign_dataset(8)'
  rs1_b2_val_data: 'gen_usign_dataset(8)'
  rs1_b3_val_data: 'gen_usign_dataset(8)'
  rs1_b4_val_data: 'gen_usign_dataset(8)'
  rs1_b5_val_data: 'gen_usign_dataset(8)'
  rs1_b6_val_data: 'gen_usign_dataset(8)'
  rs1_b7_val_data: 'gen_usign_dataset(8)'
  imm_val_data: 'gen_imm_dataset(3)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)

srl8.u:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'psbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_usign_dataset(8)'
  rs1_b1_val_data: 'gen_usign_dataset(8)'
  rs1_b2_val_data: 'gen_usign_dataset(8)'
  rs1_b3_val_data: 'gen_usign_dataset(8)'
  rs1_b4_val_data: 'gen_usign_dataset(8)'
  rs1_b5_val_data: 'gen_usign_dataset(8)'
  rs1_b6_val_data: 'gen_usign_dataset(8)'
  rs1_b7_val_data: 'gen_usign_dataset(8)'
  rs2_val_data: 'gen_usign_dataset(ceil(log(8,2)))'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

srli8.u:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbriformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_usign_dataset(8)'
  rs1_b1_val_data: 'gen_usign_dataset(8)'
  rs1_b2_val_data: 'gen_usign_dataset(8)'
  rs1_b3_val_data: 'gen_usign_dataset(8)'
  rs1_b4_val_data: 'gen_usign_dataset(8)'
  rs1_b5_val_data: 'gen_usign_dataset(8)'
  rs1_b6_val_data: 'gen_usign_dataset(8)'
  rs1_b7_val_data: 'gen_usign_dataset(8)'
  imm_val_data: 'gen_imm_dataset(3)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)

sll8:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'psbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_usign_dataset(8)'
  rs1_b1_val_data: 'gen_usign_dataset(8)'
  rs1_b2_val_data: 'gen_usign_dataset(8)'
  rs1_b3_val_data: 'gen_usign_dataset(8)'
  rs1_b4_val_data: 'gen_usign_dataset(8)'
  rs1_b5_val_data: 'gen_usign_dataset(8)'
  rs1_b6_val_data: 'gen_usign_dataset(8)'
  rs1_b7_val_data: 'gen_usign_dataset(8)'
  rs2_val_data: 'gen_usign_dataset(ceil(log(8,2)))'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

slli8:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbriformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_usign_dataset(8)'
  rs1_b1_val_data: 'gen_usign_dataset(8)'
  rs1_b2_val_data: 'gen_usign_dataset(8)'
  rs1_b3_val_data: 'gen_usign_dataset(8)'
  rs1_b4_val_data: 'gen_usign_dataset(8)'
  rs1_b5_val_data: 'gen_usign_dataset(8)'
  rs1_b6_val_data: 'gen_usign_dataset(8)'
  rs1_b7_val_data: 'gen_usign_dataset(8)'
  imm_val_data: 'gen_imm_dataset(3)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)

ksll8:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'psbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_sign_dataset(8)'
  rs1_b1_val_data: 'gen_sign_dataset(8)'
  rs1_b2_val_data: 'gen_sign_dataset(8)'
  rs1_b3_val_data: 'gen_sign_dataset(8)'
  rs1_b4_val_data: 'gen_sign_dataset(8)'
  rs1_b5_val_data: 'gen_sign_dataset(8)'
  rs1_b6_val_data: 'gen_sign_dataset(8)'
  rs1_b7_val_data: 'gen_sign_dataset(8)'
  rs2_val_data: 'gen_usign_dataset(ceil(log(8,2)))'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kslli8:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbriformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_sign_dataset(8)'
  rs1_b1_val_data: 'gen_sign_dataset(8)'
  rs1_b2_val_data: 'gen_sign_dataset(8)'
  rs1_b3_val_data: 'gen_sign_dataset(8)'
  rs1_b4_val_data: 'gen_sign_dataset(8)'
  rs1_b5_val_data: 'gen_sign_dataset(8)'
  rs1_b6_val_data: 'gen_sign_dataset(8)'
  rs1_b7_val_data: 'gen_sign_dataset(8)'
  imm_val_data: 'gen_imm_dataset(3)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_PKIMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $rs1, $swreg, $offset, $testreg)

kslra8:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8,xlen
  formattype: 'psbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_sign_dataset(8)'
  rs1_b1_val_data: 'gen_sign_dataset(8)'
  rs1_b2_val_data: 'gen_sign_dataset(8)'
  rs1_b3_val_data: 'gen_sign_dataset(8)'
  rs1_b4_val_data: 'gen_sign_dataset(8)'
  rs1_b5_val_data: 'gen_sign_dataset(8)'
  rs1_b6_val_data: 'gen_sign_dataset(8)'
  rs1_b7_val_data: 'gen_sign_dataset(8)'
  rs2_val_data: 'gen_sign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kslra8.u:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8,xlen
  formattype: 'psbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_usign_dataset(8)'
  rs1_b1_val_data: 'gen_usign_dataset(8)'
  rs1_b2_val_data: 'gen_usign_dataset(8)'
  rs1_b3_val_data: 'gen_usign_dataset(8)'
  rs1_b4_val_data: 'gen_usign_dataset(8)'
  rs1_b5_val_data: 'gen_usign_dataset(8)'
  rs1_b6_val_data: 'gen_usign_dataset(8)'
  rs1_b7_val_data: 'gen_usign_dataset(8)'
  rs2_val_data: 'gen_sign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

# 3.1.5. 16-bit Compare Instructions

cmpeq16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

scmplt16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

scmple16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

ucmplt16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  rs2_h0_val_data: 'gen_usign_dataset(16)'
  rs2_h1_val_data: 'gen_usign_dataset(16)'
  rs2_h2_val_data: 'gen_usign_dataset(16)'
  rs2_h3_val_data: 'gen_usign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

ucmple16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  rs2_h0_val_data: 'gen_usign_dataset(16)'
  rs2_h1_val_data: 'gen_usign_dataset(16)'
  rs2_h2_val_data: 'gen_usign_dataset(16)'
  rs2_h3_val_data: 'gen_usign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

# 3.1.6. 8-bit Compare Instructions

cmpeq8:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_sign_dataset(8)'
  rs1_b1_val_data: 'gen_sign_dataset(8)'
  rs1_b2_val_data: 'gen_sign_dataset(8)'
  rs1_b3_val_data: 'gen_sign_dataset(8)'
  rs1_b4_val_data: 'gen_sign_dataset(8)'
  rs1_b5_val_data: 'gen_sign_dataset(8)'
  rs1_b6_val_data: 'gen_sign_dataset(8)'
  rs1_b7_val_data: 'gen_sign_dataset(8)'
  rs2_b0_val_data: 'gen_sign_dataset(8)'
  rs2_b1_val_data: 'gen_sign_dataset(8)'
  rs2_b2_val_data: 'gen_sign_dataset(8)'
  rs2_b3_val_data: 'gen_sign_dataset(8)'
  rs2_b4_val_data: 'gen_sign_dataset(8)'
  rs2_b5_val_data: 'gen_sign_dataset(8)'
  rs2_b6_val_data: 'gen_sign_dataset(8)'
  rs2_b7_val_data: 'gen_sign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

scmplt8:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_sign_dataset(8)'
  rs1_b1_val_data: 'gen_sign_dataset(8)'
  rs1_b2_val_data: 'gen_sign_dataset(8)'
  rs1_b3_val_data: 'gen_sign_dataset(8)'
  rs1_b4_val_data: 'gen_sign_dataset(8)'
  rs1_b5_val_data: 'gen_sign_dataset(8)'
  rs1_b6_val_data: 'gen_sign_dataset(8)'
  rs1_b7_val_data: 'gen_sign_dataset(8)'
  rs2_b0_val_data: 'gen_sign_dataset(8)'
  rs2_b1_val_data: 'gen_sign_dataset(8)'
  rs2_b2_val_data: 'gen_sign_dataset(8)'
  rs2_b3_val_data: 'gen_sign_dataset(8)'
  rs2_b4_val_data: 'gen_sign_dataset(8)'
  rs2_b5_val_data: 'gen_sign_dataset(8)'
  rs2_b6_val_data: 'gen_sign_dataset(8)'
  rs2_b7_val_data: 'gen_sign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

scmple8:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_sign_dataset(8)'
  rs1_b1_val_data: 'gen_sign_dataset(8)'
  rs1_b2_val_data: 'gen_sign_dataset(8)'
  rs1_b3_val_data: 'gen_sign_dataset(8)'
  rs1_b4_val_data: 'gen_sign_dataset(8)'
  rs1_b5_val_data: 'gen_sign_dataset(8)'
  rs1_b6_val_data: 'gen_sign_dataset(8)'
  rs1_b7_val_data: 'gen_sign_dataset(8)'
  rs2_b0_val_data: 'gen_sign_dataset(8)'
  rs2_b1_val_data: 'gen_sign_dataset(8)'
  rs2_b2_val_data: 'gen_sign_dataset(8)'
  rs2_b3_val_data: 'gen_sign_dataset(8)'
  rs2_b4_val_data: 'gen_sign_dataset(8)'
  rs2_b5_val_data: 'gen_sign_dataset(8)'
  rs2_b6_val_data: 'gen_sign_dataset(8)'
  rs2_b7_val_data: 'gen_sign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

ucmplt8:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_usign_dataset(8)'
  rs1_b1_val_data: 'gen_usign_dataset(8)'
  rs1_b2_val_data: 'gen_usign_dataset(8)'
  rs1_b3_val_data: 'gen_usign_dataset(8)'
  rs1_b4_val_data: 'gen_usign_dataset(8)'
  rs1_b5_val_data: 'gen_usign_dataset(8)'
  rs1_b6_val_data: 'gen_usign_dataset(8)'
  rs1_b7_val_data: 'gen_usign_dataset(8)'
  rs2_b0_val_data: 'gen_usign_dataset(8)'
  rs2_b1_val_data: 'gen_usign_dataset(8)'
  rs2_b2_val_data: 'gen_usign_dataset(8)'
  rs2_b3_val_data: 'gen_usign_dataset(8)'
  rs2_b4_val_data: 'gen_usign_dataset(8)'
  rs2_b5_val_data: 'gen_usign_dataset(8)'
  rs2_b6_val_data: 'gen_usign_dataset(8)'
  rs2_b7_val_data: 'gen_usign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

ucmple8:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_usign_dataset(8)'
  rs1_b1_val_data: 'gen_usign_dataset(8)'
  rs1_b2_val_data: 'gen_usign_dataset(8)'
  rs1_b3_val_data: 'gen_usign_dataset(8)'
  rs1_b4_val_data: 'gen_usign_dataset(8)'
  rs1_b5_val_data: 'gen_usign_dataset(8)'
  rs1_b6_val_data: 'gen_usign_dataset(8)'
  rs1_b7_val_data: 'gen_usign_dataset(8)'
  rs2_b0_val_data: 'gen_usign_dataset(8)'
  rs2_b1_val_data: 'gen_usign_dataset(8)'
  rs2_b2_val_data: 'gen_usign_dataset(8)'
  rs2_b3_val_data: 'gen_usign_dataset(8)'
  rs2_b4_val_data: 'gen_usign_dataset(8)'
  rs2_b5_val_data: 'gen_usign_dataset(8)'
  rs2_b6_val_data: 'gen_usign_dataset(8)'
  rs2_b7_val_data: 'gen_usign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

# 3.1.7. 16-bit Multiply Instructions

smul16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  p64_profile: 'pnn'
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *pair_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

smulx16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  p64_profile: 'pnn'
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *pair_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

umul16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  p64_profile: 'pnn'
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *pair_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  rs2_h0_val_data: 'gen_usign_dataset(16)'
  rs2_h1_val_data: 'gen_usign_dataset(16)'
  rs2_h2_val_data: 'gen_usign_dataset(16)'
  rs2_h3_val_data: 'gen_usign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

umulx16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  p64_profile: 'pnn'
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *pair_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  rs2_h0_val_data: 'gen_usign_dataset(16)'
  rs2_h1_val_data: 'gen_usign_dataset(16)'
  rs2_h2_val_data: 'gen_usign_dataset(16)'
  rs2_h3_val_data: 'gen_usign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

khm16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

khmx16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

# 3.1.8. 8-bit Multiply Instructions

smul8:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  p64_profile: 'pnn'
  formattype: 'pbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *pair_regs
  rs1_b0_val_data: 'gen_sign_dataset(8)'
  rs1_b1_val_data: 'gen_sign_dataset(8)'
  rs1_b2_val_data: 'gen_sign_dataset(8)'
  rs1_b3_val_data: 'gen_sign_dataset(8)'
  rs1_b4_val_data: 'gen_sign_dataset(8)'
  rs1_b5_val_data: 'gen_sign_dataset(8)'
  rs1_b6_val_data: 'gen_sign_dataset(8)'
  rs1_b7_val_data: 'gen_sign_dataset(8)'
  rs2_b0_val_data: 'gen_sign_dataset(8)'
  rs2_b1_val_data: 'gen_sign_dataset(8)'
  rs2_b2_val_data: 'gen_sign_dataset(8)'
  rs2_b3_val_data: 'gen_sign_dataset(8)'
  rs2_b4_val_data: 'gen_sign_dataset(8)'
  rs2_b5_val_data: 'gen_sign_dataset(8)'
  rs2_b6_val_data: 'gen_sign_dataset(8)'
  rs2_b7_val_data: 'gen_sign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

smulx8:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  p64_profile: 'pnn'
  formattype: 'pbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *pair_regs
  rs1_b0_val_data: 'gen_sign_dataset(8)'
  rs1_b1_val_data: 'gen_sign_dataset(8)'
  rs1_b2_val_data: 'gen_sign_dataset(8)'
  rs1_b3_val_data: 'gen_sign_dataset(8)'
  rs1_b4_val_data: 'gen_sign_dataset(8)'
  rs1_b5_val_data: 'gen_sign_dataset(8)'
  rs1_b6_val_data: 'gen_sign_dataset(8)'
  rs1_b7_val_data: 'gen_sign_dataset(8)'
  rs2_b0_val_data: 'gen_sign_dataset(8)'
  rs2_b1_val_data: 'gen_sign_dataset(8)'
  rs2_b2_val_data: 'gen_sign_dataset(8)'
  rs2_b3_val_data: 'gen_sign_dataset(8)'
  rs2_b4_val_data: 'gen_sign_dataset(8)'
  rs2_b5_val_data: 'gen_sign_dataset(8)'
  rs2_b6_val_data: 'gen_sign_dataset(8)'
  rs2_b7_val_data: 'gen_sign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

umul8:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  p64_profile: 'pnn'
  formattype: 'pbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *pair_regs
  rs1_b0_val_data: 'gen_usign_dataset(8)'
  rs1_b1_val_data: 'gen_usign_dataset(8)'
  rs1_b2_val_data: 'gen_usign_dataset(8)'
  rs1_b3_val_data: 'gen_usign_dataset(8)'
  rs1_b4_val_data: 'gen_usign_dataset(8)'
  rs1_b5_val_data: 'gen_usign_dataset(8)'
  rs1_b6_val_data: 'gen_usign_dataset(8)'
  rs1_b7_val_data: 'gen_usign_dataset(8)'
  rs2_b0_val_data: 'gen_usign_dataset(8)'
  rs2_b1_val_data: 'gen_usign_dataset(8)'
  rs2_b2_val_data: 'gen_usign_dataset(8)'
  rs2_b3_val_data: 'gen_usign_dataset(8)'
  rs2_b4_val_data: 'gen_usign_dataset(8)'
  rs2_b5_val_data: 'gen_usign_dataset(8)'
  rs2_b6_val_data: 'gen_usign_dataset(8)'
  rs2_b7_val_data: 'gen_usign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

umulx8:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  p64_profile: 'pnn'
  formattype: 'pbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *pair_regs
  rs1_b0_val_data: 'gen_usign_dataset(8)'
  rs1_b1_val_data: 'gen_usign_dataset(8)'
  rs1_b2_val_data: 'gen_usign_dataset(8)'
  rs1_b3_val_data: 'gen_usign_dataset(8)'
  rs1_b4_val_data: 'gen_usign_dataset(8)'
  rs1_b5_val_data: 'gen_usign_dataset(8)'
  rs1_b6_val_data: 'gen_usign_dataset(8)'
  rs1_b7_val_data: 'gen_usign_dataset(8)'
  rs2_b0_val_data: 'gen_usign_dataset(8)'
  rs2_b1_val_data: 'gen_usign_dataset(8)'
  rs2_b2_val_data: 'gen_usign_dataset(8)'
  rs2_b3_val_data: 'gen_usign_dataset(8)'
  rs2_b4_val_data: 'gen_usign_dataset(8)'
  rs2_b5_val_data: 'gen_usign_dataset(8)'
  rs2_b6_val_data: 'gen_usign_dataset(8)'
  rs2_b7_val_data: 'gen_usign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

khm8:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_sign_dataset(8)'
  rs1_b1_val_data: 'gen_sign_dataset(8)'
  rs1_b2_val_data: 'gen_sign_dataset(8)'
  rs1_b3_val_data: 'gen_sign_dataset(8)'
  rs1_b4_val_data: 'gen_sign_dataset(8)'
  rs1_b5_val_data: 'gen_sign_dataset(8)'
  rs1_b6_val_data: 'gen_sign_dataset(8)'
  rs1_b7_val_data: 'gen_sign_dataset(8)'
  rs2_b0_val_data: 'gen_sign_dataset(8)'
  rs2_b1_val_data: 'gen_sign_dataset(8)'
  rs2_b2_val_data: 'gen_sign_dataset(8)'
  rs2_b3_val_data: 'gen_sign_dataset(8)'
  rs2_b4_val_data: 'gen_sign_dataset(8)'
  rs2_b5_val_data: 'gen_sign_dataset(8)'
  rs2_b6_val_data: 'gen_sign_dataset(8)'
  rs2_b7_val_data: 'gen_sign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

khmx8:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_sign_dataset(8)'
  rs1_b1_val_data: 'gen_sign_dataset(8)'
  rs1_b2_val_data: 'gen_sign_dataset(8)'
  rs1_b3_val_data: 'gen_sign_dataset(8)'
  rs1_b4_val_data: 'gen_sign_dataset(8)'
  rs1_b5_val_data: 'gen_sign_dataset(8)'
  rs1_b6_val_data: 'gen_sign_dataset(8)'
  rs1_b7_val_data: 'gen_sign_dataset(8)'
  rs2_b0_val_data: 'gen_sign_dataset(8)'
  rs2_b1_val_data: 'gen_sign_dataset(8)'
  rs2_b2_val_data: 'gen_sign_dataset(8)'
  rs2_b3_val_data: 'gen_sign_dataset(8)'
  rs2_b4_val_data: 'gen_sign_dataset(8)'
  rs2_b5_val_data: 'gen_sign_dataset(8)'
  rs2_b6_val_data: 'gen_sign_dataset(8)'
  rs2_b7_val_data: 'gen_sign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

# 3.1.9. 16-bit Misc Instructions

smin16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

umin16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  rs2_h0_val_data: 'gen_usign_dataset(16)'
  rs2_h1_val_data: 'gen_usign_dataset(16)'
  rs2_h2_val_data: 'gen_usign_dataset(16)'
  rs2_h3_val_data: 'gen_usign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

smax16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

umax16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  rs2_h0_val_data: 'gen_usign_dataset(16)'
  rs2_h1_val_data: 'gen_usign_dataset(16)'
  rs2_h2_val_data: 'gen_usign_dataset(16)'
  rs2_h3_val_data: 'gen_usign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

sclip16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phriformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  imm_val_data: 'gen_imm_dataset(4)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_PKIMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $rs1, $swreg, $offset, $testreg)

uclip16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phriformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  imm_val_data: 'gen_imm_dataset(4)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_PKIMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $rs1, $swreg, $offset, $testreg)

kabs16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    TEST_PKR_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $rs1, $swreg, $offset, $testreg)

clrs16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)

clz16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)

swap16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)

# 3.1.10. 8-bit Misc Instructions

smin8:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_sign_dataset(8)'
  rs1_b1_val_data: 'gen_sign_dataset(8)'
  rs1_b2_val_data: 'gen_sign_dataset(8)'
  rs1_b3_val_data: 'gen_sign_dataset(8)'
  rs1_b4_val_data: 'gen_sign_dataset(8)'
  rs1_b5_val_data: 'gen_sign_dataset(8)'
  rs1_b6_val_data: 'gen_sign_dataset(8)'
  rs1_b7_val_data: 'gen_sign_dataset(8)'
  rs2_b0_val_data: 'gen_sign_dataset(8)'
  rs2_b1_val_data: 'gen_sign_dataset(8)'
  rs2_b2_val_data: 'gen_sign_dataset(8)'
  rs2_b3_val_data: 'gen_sign_dataset(8)'
  rs2_b4_val_data: 'gen_sign_dataset(8)'
  rs2_b5_val_data: 'gen_sign_dataset(8)'
  rs2_b6_val_data: 'gen_sign_dataset(8)'
  rs2_b7_val_data: 'gen_sign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

umin8:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_usign_dataset(8)'
  rs1_b1_val_data: 'gen_usign_dataset(8)'
  rs1_b2_val_data: 'gen_usign_dataset(8)'
  rs1_b3_val_data: 'gen_usign_dataset(8)'
  rs1_b4_val_data: 'gen_usign_dataset(8)'
  rs1_b5_val_data: 'gen_usign_dataset(8)'
  rs1_b6_val_data: 'gen_usign_dataset(8)'
  rs1_b7_val_data: 'gen_usign_dataset(8)'
  rs2_b0_val_data: 'gen_usign_dataset(8)'
  rs2_b1_val_data: 'gen_usign_dataset(8)'
  rs2_b2_val_data: 'gen_usign_dataset(8)'
  rs2_b3_val_data: 'gen_usign_dataset(8)'
  rs2_b4_val_data: 'gen_usign_dataset(8)'
  rs2_b5_val_data: 'gen_usign_dataset(8)'
  rs2_b6_val_data: 'gen_usign_dataset(8)'
  rs2_b7_val_data: 'gen_usign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

smax8:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_sign_dataset(8)'
  rs1_b1_val_data: 'gen_sign_dataset(8)'
  rs1_b2_val_data: 'gen_sign_dataset(8)'
  rs1_b3_val_data: 'gen_sign_dataset(8)'
  rs1_b4_val_data: 'gen_sign_dataset(8)'
  rs1_b5_val_data: 'gen_sign_dataset(8)'
  rs1_b6_val_data: 'gen_sign_dataset(8)'
  rs1_b7_val_data: 'gen_sign_dataset(8)'
  rs2_b0_val_data: 'gen_sign_dataset(8)'
  rs2_b1_val_data: 'gen_sign_dataset(8)'
  rs2_b2_val_data: 'gen_sign_dataset(8)'
  rs2_b3_val_data: 'gen_sign_dataset(8)'
  rs2_b4_val_data: 'gen_sign_dataset(8)'
  rs2_b5_val_data: 'gen_sign_dataset(8)'
  rs2_b6_val_data: 'gen_sign_dataset(8)'
  rs2_b7_val_data: 'gen_sign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

umax8:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_usign_dataset(8)'
  rs1_b1_val_data: 'gen_usign_dataset(8)'
  rs1_b2_val_data: 'gen_usign_dataset(8)'
  rs1_b3_val_data: 'gen_usign_dataset(8)'
  rs1_b4_val_data: 'gen_usign_dataset(8)'
  rs1_b5_val_data: 'gen_usign_dataset(8)'
  rs1_b6_val_data: 'gen_usign_dataset(8)'
  rs1_b7_val_data: 'gen_usign_dataset(8)'
  rs2_b0_val_data: 'gen_usign_dataset(8)'
  rs2_b1_val_data: 'gen_usign_dataset(8)'
  rs2_b2_val_data: 'gen_usign_dataset(8)'
  rs2_b3_val_data: 'gen_usign_dataset(8)'
  rs2_b4_val_data: 'gen_usign_dataset(8)'
  rs2_b5_val_data: 'gen_usign_dataset(8)'
  rs2_b6_val_data: 'gen_usign_dataset(8)'
  rs2_b7_val_data: 'gen_usign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

kabs8:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_sign_dataset(8)'
  rs1_b1_val_data: 'gen_sign_dataset(8)'
  rs1_b2_val_data: 'gen_sign_dataset(8)'
  rs1_b3_val_data: 'gen_sign_dataset(8)'
  rs1_b4_val_data: 'gen_sign_dataset(8)'
  rs1_b5_val_data: 'gen_sign_dataset(8)'
  rs1_b6_val_data: 'gen_sign_dataset(8)'
  rs1_b7_val_data: 'gen_sign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    TEST_PKR_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $rs1, $swreg, $offset, $testreg)

sclip8:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbriformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_sign_dataset(8)'
  rs1_b1_val_data: 'gen_sign_dataset(8)'
  rs1_b2_val_data: 'gen_sign_dataset(8)'
  rs1_b3_val_data: 'gen_sign_dataset(8)'
  rs1_b4_val_data: 'gen_sign_dataset(8)'
  rs1_b5_val_data: 'gen_sign_dataset(8)'
  rs1_b6_val_data: 'gen_sign_dataset(8)'
  rs1_b7_val_data: 'gen_sign_dataset(8)'
  imm_val_data: 'gen_imm_dataset(3)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_PKIMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $rs1, $swreg, $offset, $testreg)

uclip8:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbriformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_usign_dataset(8)'
  rs1_b1_val_data: 'gen_usign_dataset(8)'
  rs1_b2_val_data: 'gen_usign_dataset(8)'
  rs1_b3_val_data: 'gen_usign_dataset(8)'
  rs1_b4_val_data: 'gen_usign_dataset(8)'
  rs1_b5_val_data: 'gen_usign_dataset(8)'
  rs1_b6_val_data: 'gen_usign_dataset(8)'
  rs1_b7_val_data: 'gen_usign_dataset(8)'
  imm_val_data: 'gen_imm_dataset(3)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_PKIMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $rs1, $swreg, $offset, $testreg)

clrs8:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_sign_dataset(8)'
  rs1_b1_val_data: 'gen_sign_dataset(8)'
  rs1_b2_val_data: 'gen_sign_dataset(8)'
  rs1_b3_val_data: 'gen_sign_dataset(8)'
  rs1_b4_val_data: 'gen_sign_dataset(8)'
  rs1_b5_val_data: 'gen_sign_dataset(8)'
  rs1_b6_val_data: 'gen_sign_dataset(8)'
  rs1_b7_val_data: 'gen_sign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)

clz8:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_usign_dataset(8)'
  rs1_b1_val_data: 'gen_usign_dataset(8)'
  rs1_b2_val_data: 'gen_usign_dataset(8)'
  rs1_b3_val_data: 'gen_usign_dataset(8)'
  rs1_b4_val_data: 'gen_usign_dataset(8)'
  rs1_b5_val_data: 'gen_usign_dataset(8)'
  rs1_b6_val_data: 'gen_usign_dataset(8)'
  rs1_b7_val_data: 'gen_usign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)

swap8:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_usign_dataset(8)'
  rs1_b1_val_data: 'gen_usign_dataset(8)'
  rs1_b2_val_data: 'gen_usign_dataset(8)'
  rs1_b3_val_data: 'gen_usign_dataset(8)'
  rs1_b4_val_data: 'gen_usign_dataset(8)'
  rs1_b5_val_data: 'gen_usign_dataset(8)'
  rs1_b6_val_data: 'gen_usign_dataset(8)'
  rs1_b7_val_data: 'gen_usign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)

# 3.1.11. 8-bit Unpacking Instructions

sunpkd810:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_sign_dataset(8)'
  rs1_b1_val_data: 'gen_sign_dataset(8)'
  rs1_b2_val_data: 'gen_sign_dataset(8)'
  rs1_b3_val_data: 'gen_sign_dataset(8)'
  rs1_b4_val_data: 'gen_sign_dataset(8)'
  rs1_b5_val_data: 'gen_sign_dataset(8)'
  rs1_b6_val_data: 'gen_sign_dataset(8)'
  rs1_b7_val_data: 'gen_sign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)

sunpkd820:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_sign_dataset(8)'
  rs1_b1_val_data: 'gen_sign_dataset(8)'
  rs1_b2_val_data: 'gen_sign_dataset(8)'
  rs1_b3_val_data: 'gen_sign_dataset(8)'
  rs1_b4_val_data: 'gen_sign_dataset(8)'
  rs1_b5_val_data: 'gen_sign_dataset(8)'
  rs1_b6_val_data: 'gen_sign_dataset(8)'
  rs1_b7_val_data: 'gen_sign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)

sunpkd830:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_sign_dataset(8)'
  rs1_b1_val_data: 'gen_sign_dataset(8)'
  rs1_b2_val_data: 'gen_sign_dataset(8)'
  rs1_b3_val_data: 'gen_sign_dataset(8)'
  rs1_b4_val_data: 'gen_sign_dataset(8)'
  rs1_b5_val_data: 'gen_sign_dataset(8)'
  rs1_b6_val_data: 'gen_sign_dataset(8)'
  rs1_b7_val_data: 'gen_sign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)

sunpkd831:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_sign_dataset(8)'
  rs1_b1_val_data: 'gen_sign_dataset(8)'
  rs1_b2_val_data: 'gen_sign_dataset(8)'
  rs1_b3_val_data: 'gen_sign_dataset(8)'
  rs1_b4_val_data: 'gen_sign_dataset(8)'
  rs1_b5_val_data: 'gen_sign_dataset(8)'
  rs1_b6_val_data: 'gen_sign_dataset(8)'
  rs1_b7_val_data: 'gen_sign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)

sunpkd832:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_sign_dataset(8)'
  rs1_b1_val_data: 'gen_sign_dataset(8)'
  rs1_b2_val_data: 'gen_sign_dataset(8)'
  rs1_b3_val_data: 'gen_sign_dataset(8)'
  rs1_b4_val_data: 'gen_sign_dataset(8)'
  rs1_b5_val_data: 'gen_sign_dataset(8)'
  rs1_b6_val_data: 'gen_sign_dataset(8)'
  rs1_b7_val_data: 'gen_sign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)

zunpkd810:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_usign_dataset(8)'
  rs1_b1_val_data: 'gen_usign_dataset(8)'
  rs1_b2_val_data: 'gen_usign_dataset(8)'
  rs1_b3_val_data: 'gen_usign_dataset(8)'
  rs1_b4_val_data: 'gen_usign_dataset(8)'
  rs1_b5_val_data: 'gen_usign_dataset(8)'
  rs1_b6_val_data: 'gen_usign_dataset(8)'
  rs1_b7_val_data: 'gen_usign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)

zunpkd820:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_usign_dataset(8)'
  rs1_b1_val_data: 'gen_usign_dataset(8)'
  rs1_b2_val_data: 'gen_usign_dataset(8)'
  rs1_b3_val_data: 'gen_usign_dataset(8)'
  rs1_b4_val_data: 'gen_usign_dataset(8)'
  rs1_b5_val_data: 'gen_usign_dataset(8)'
  rs1_b6_val_data: 'gen_usign_dataset(8)'
  rs1_b7_val_data: 'gen_usign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)

zunpkd830:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_usign_dataset(8)'
  rs1_b1_val_data: 'gen_usign_dataset(8)'
  rs1_b2_val_data: 'gen_usign_dataset(8)'
  rs1_b3_val_data: 'gen_usign_dataset(8)'
  rs1_b4_val_data: 'gen_usign_dataset(8)'
  rs1_b5_val_data: 'gen_usign_dataset(8)'
  rs1_b6_val_data: 'gen_usign_dataset(8)'
  rs1_b7_val_data: 'gen_usign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)

zunpkd831:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_usign_dataset(8)'
  rs1_b1_val_data: 'gen_usign_dataset(8)'
  rs1_b2_val_data: 'gen_usign_dataset(8)'
  rs1_b3_val_data: 'gen_usign_dataset(8)'
  rs1_b4_val_data: 'gen_usign_dataset(8)'
  rs1_b5_val_data: 'gen_usign_dataset(8)'
  rs1_b6_val_data: 'gen_usign_dataset(8)'
  rs1_b7_val_data: 'gen_usign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)

zunpkd832:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_usign_dataset(8)'
  rs1_b1_val_data: 'gen_usign_dataset(8)'
  rs1_b2_val_data: 'gen_usign_dataset(8)'
  rs1_b3_val_data: 'gen_usign_dataset(8)'
  rs1_b4_val_data: 'gen_usign_dataset(8)'
  rs1_b5_val_data: 'gen_usign_dataset(8)'
  rs1_b6_val_data: 'gen_usign_dataset(8)'
  rs1_b7_val_data: 'gen_usign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)

# 3.2 Partial-SIMD Data Processing Instructions

pkbb16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  rs2_h0_val_data: 'gen_usign_dataset(16)'
  rs2_h1_val_data: 'gen_usign_dataset(16)'
  rs2_h2_val_data: 'gen_usign_dataset(16)'
  rs2_h3_val_data: 'gen_usign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

pkbt16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  rs2_h0_val_data: 'gen_usign_dataset(16)'
  rs2_h1_val_data: 'gen_usign_dataset(16)'
  rs2_h2_val_data: 'gen_usign_dataset(16)'
  rs2_h3_val_data: 'gen_usign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

pktb16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  rs2_h0_val_data: 'gen_usign_dataset(16)'
  rs2_h1_val_data: 'gen_usign_dataset(16)'
  rs2_h2_val_data: 'gen_usign_dataset(16)'
  rs2_h3_val_data: 'gen_usign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

pktt16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  rs2_h0_val_data: 'gen_usign_dataset(16)'
  rs2_h1_val_data: 'gen_usign_dataset(16)'
  rs2_h2_val_data: 'gen_usign_dataset(16)'
  rs2_h3_val_data: 'gen_usign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
# 3.2.2 Most Significant Word 32x32 Multiply & Add Instructions
smmul:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

smmul.u:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)'
  rs1_w1_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)'
  rs2_w0_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)'
  rs2_w1_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

kmmac:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)'
  rs1_w1_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)'
  rs2_w0_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)'
  rs2_w1_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmmac.u:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)'
  rs1_w1_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)'
  rs2_w0_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)'
  rs2_w1_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmmsb:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)'
  rs1_w1_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)'
  rs2_w0_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)'
  rs2_w1_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmmsb.u:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)'
  rs1_w1_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)'
  rs2_w0_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)'
  rs2_w1_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kwmmul:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)'
  rs1_w1_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)'
  rs2_w0_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)'
  rs2_w1_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kwmmul.u:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)'
  rs1_w1_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)'
  rs2_w0_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)'
  rs2_w1_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)


# 3.2.3 Most Significant Word 32x16 Multiply & Add Instructions
smmwb:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32, 16
  formattype: 'pwhrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

smmwb.u:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32, 16
  formattype: 'pwhrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

smmwt:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32, 16
  formattype: 'pwhrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

smmwt.u:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32, 16
  formattype: 'pwhrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

kmmawb:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32, 16
  formattype: 'pwhrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmmawb.u:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32, 16
  formattype: 'pwhrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmmawt:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32, 16
  formattype: 'pwhrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmmawt.u:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32, 16
  formattype: 'pwhrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmmwb2:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32, 16
  formattype: 'pwhrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)


kmmwb2.u:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32, 16
  formattype: 'pwhrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmmwt2:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32, 16
  formattype: 'pwhrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmmwt2.u:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32, 16
  formattype: 'pwhrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)


kmmawb2:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32, 16
  formattype: 'pwhrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmmawb2.u:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32, 16
  formattype: 'pwhrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmmawt2:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32, 16
  formattype: 'pwhrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmmawt2.u:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32, 16
  formattype: 'pwhrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)


# 3.2.4 Signed 16-bit Multiply with 32-bit Add/Subtract Instructions

smbb16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

smbt16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

smtt16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

kmda:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmxda:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

smds:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

smdrs:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

smxds:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

kmabb:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmabt:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmatt:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmada:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmaxda:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmads:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmadrs:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmaxds:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmsda:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmsxda:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

# 3.2.5 Signed 16-bit Multiply with 64-bit Add/Subtract Instructions

smal:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 64,16
  p64_profile: 'ppn'
  formattype: 'pphrrformat'
  rs1_op_data: *pair_regs
  rs2_op_data: *all_regs

  rd_op_data: *pair_regs
  rs1_val_data: 'gen_sign_dataset(64)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val64; op2val:$rs2_val;
    TEST_P64_PPN_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $swreg, $offset, $testreg)


# 3.2.6 Miscellaneous Instructions

sclip32:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwriformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  imm_val_data: 'gen_imm_dataset(5)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_PKIMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $rs1, $swreg, $offset, $testreg)

uclip32:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwriformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  imm_val_data: 'gen_imm_dataset(5)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_PKIMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $rs1, $swreg, $offset, $testreg)

clrs32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)

clz32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)

pbsad:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_usign_dataset(8)'
  rs1_b1_val_data: 'gen_usign_dataset(8)'
  rs1_b2_val_data: 'gen_usign_dataset(8)'
  rs1_b3_val_data: 'gen_usign_dataset(8)'
  rs1_b4_val_data: 'gen_usign_dataset(8)'
  rs1_b5_val_data: 'gen_usign_dataset(8)'
  rs1_b6_val_data: 'gen_usign_dataset(8)'
  rs1_b7_val_data: 'gen_usign_dataset(8)'
  rs2_b0_val_data: 'gen_usign_dataset(8)'
  rs2_b1_val_data: 'gen_usign_dataset(8)'
  rs2_b2_val_data: 'gen_usign_dataset(8)'
  rs2_b3_val_data: 'gen_usign_dataset(8)'
  rs2_b4_val_data: 'gen_usign_dataset(8)'
  rs2_b5_val_data: 'gen_usign_dataset(8)'
  rs2_b6_val_data: 'gen_usign_dataset(8)'
  rs2_b7_val_data: 'gen_usign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

pbsada:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_usign_dataset(8)'
  rs1_b1_val_data: 'gen_usign_dataset(8)'
  rs1_b2_val_data: 'gen_usign_dataset(8)'
  rs1_b3_val_data: 'gen_usign_dataset(8)'
  rs1_b4_val_data: 'gen_usign_dataset(8)'
  rs1_b5_val_data: 'gen_usign_dataset(8)'
  rs1_b6_val_data: 'gen_usign_dataset(8)'
  rs1_b7_val_data: 'gen_usign_dataset(8)'
  rs2_b0_val_data: 'gen_usign_dataset(8)'
  rs2_b1_val_data: 'gen_usign_dataset(8)'
  rs2_b2_val_data: 'gen_usign_dataset(8)'
  rs2_b3_val_data: 'gen_usign_dataset(8)'
  rs2_b4_val_data: 'gen_usign_dataset(8)'
  rs2_b5_val_data: 'gen_usign_dataset(8)'
  rs2_b6_val_data: 'gen_usign_dataset(8)'
  rs2_b7_val_data: 'gen_usign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

# 3.2.7. 8-bit Multiply with 32-bit Add Instructions

smaqa:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_sign_dataset(8)'
  rs1_b1_val_data: 'gen_sign_dataset(8)'
  rs1_b2_val_data: 'gen_sign_dataset(8)'
  rs1_b3_val_data: 'gen_sign_dataset(8)'
  rs1_b4_val_data: 'gen_sign_dataset(8)'
  rs1_b5_val_data: 'gen_sign_dataset(8)'
  rs1_b6_val_data: 'gen_sign_dataset(8)'
  rs1_b7_val_data: 'gen_sign_dataset(8)'
  rs2_b0_val_data: 'gen_sign_dataset(8)'
  rs2_b1_val_data: 'gen_sign_dataset(8)'
  rs2_b2_val_data: 'gen_sign_dataset(8)'
  rs2_b3_val_data: 'gen_sign_dataset(8)'
  rs2_b4_val_data: 'gen_sign_dataset(8)'
  rs2_b5_val_data: 'gen_sign_dataset(8)'
  rs2_b6_val_data: 'gen_sign_dataset(8)'
  rs2_b7_val_data: 'gen_sign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

umaqa:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_usign_dataset(8)'
  rs1_b1_val_data: 'gen_usign_dataset(8)'
  rs1_b2_val_data: 'gen_usign_dataset(8)'
  rs1_b3_val_data: 'gen_usign_dataset(8)'
  rs1_b4_val_data: 'gen_usign_dataset(8)'
  rs1_b5_val_data: 'gen_usign_dataset(8)'
  rs1_b6_val_data: 'gen_usign_dataset(8)'
  rs1_b7_val_data: 'gen_usign_dataset(8)'
  rs2_b0_val_data: 'gen_usign_dataset(8)'
  rs2_b1_val_data: 'gen_usign_dataset(8)'
  rs2_b2_val_data: 'gen_usign_dataset(8)'
  rs2_b3_val_data: 'gen_usign_dataset(8)'
  rs2_b4_val_data: 'gen_usign_dataset(8)'
  rs2_b5_val_data: 'gen_usign_dataset(8)'
  rs2_b6_val_data: 'gen_usign_dataset(8)'
  rs2_b7_val_data: 'gen_usign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

smaqa.su:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 8
  formattype: 'pbrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_b0_val_data: 'gen_sign_dataset(8)'
  rs1_b1_val_data: 'gen_sign_dataset(8)'
  rs1_b2_val_data: 'gen_sign_dataset(8)'
  rs1_b3_val_data: 'gen_sign_dataset(8)'
  rs1_b4_val_data: 'gen_sign_dataset(8)'
  rs1_b5_val_data: 'gen_sign_dataset(8)'
  rs1_b6_val_data: 'gen_sign_dataset(8)'
  rs1_b7_val_data: 'gen_sign_dataset(8)'
  rs2_b0_val_data: 'gen_sign_dataset(8)'
  rs2_b1_val_data: 'gen_sign_dataset(8)'
  rs2_b2_val_data: 'gen_sign_dataset(8)'
  rs2_b3_val_data: 'gen_sign_dataset(8)'
  rs2_b4_val_data: 'gen_sign_dataset(8)'
  rs2_b5_val_data: 'gen_sign_dataset(8)'
  rs2_b6_val_data: 'gen_sign_dataset(8)'
  rs2_b7_val_data: 'gen_sign_dataset(8)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

# 3.3.1 64-bit Addition & Subtraction Instructions

add64:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 64
  p64_profile: 'ppp'
  formattype: 'prrformat'
  rs1_op_data: *pair_regs
  rs2_op_data: *pair_regs
  rd_op_data: *pair_regs
  rs1_val_data: 'gen_sign_dataset(64)'
  rs2_val_data: 'gen_sign_dataset(64)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val64 op2val:$rs2_val64
    TEST_P64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $swreg, $offset, $testreg)

radd64:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 64
  p64_profile: 'ppp'
  formattype: 'prrformat'
  rs1_op_data: *pair_regs
  rs2_op_data: *pair_regs
  rd_op_data: *pair_regs
  rs1_val_data: 'gen_sign_dataset(64)'
  rs2_val_data: 'gen_sign_dataset(64)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val64;  op2val:$rs2_val64;
    TEST_P64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $swreg, $offset, $testreg)

uradd64:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 64
  p64_profile: 'ppp'
  formattype: 'prrformat'
  rs1_op_data: *pair_regs
  rs2_op_data: *pair_regs
  rd_op_data: *pair_regs
  rs1_val_data: 'gen_usign_dataset(64)'
  rs2_val_data: 'gen_usign_dataset(64)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val64;  op2val:$rs2_val64;
    TEST_P64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $swreg, $offset, $testreg)

kadd64:
  sig:
    stride: 3
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 64
  p64_profile: 'ppp'
  formattype: 'prrformat'
  rs1_op_data: *pair_regs
  rs2_op_data: *pair_regs
  rd_op_data: *pair_regs
  rs1_val_data: 'gen_sign_dataset(64)'
  rs2_val_data: 'gen_sign_dataset(64)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val64;  op2val:$rs2_val64;
    TEST_PK64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $rs1, $swreg, $offset, $testreg)

ukadd64:
  sig:
    stride: 3
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 64
  p64_profile: 'ppp'
  formattype: 'prrformat'
  rs1_op_data: *pair_regs
  rs2_op_data: *pair_regs
  rd_op_data: *pair_regs
  rs1_val_data: 'gen_usign_dataset(64)'
  rs2_val_data: 'gen_usign_dataset(64)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val64;  op2val:$rs2_val64;
    TEST_PK64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $rs1, $swreg, $offset, $testreg)

sub64:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 64
  p64_profile: 'ppp'
  formattype: 'prrformat'
  rs1_op_data: *pair_regs
  rs2_op_data: *pair_regs
  rd_op_data: *pair_regs
  rs1_val_data: 'gen_sign_dataset(64)'
  rs2_val_data: 'gen_sign_dataset(64)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val64;  op2val:$rs2_val64;
    TEST_P64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $swreg, $offset, $testreg)

rsub64:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 64
  p64_profile: 'ppp'
  formattype: 'prrformat'
  rs1_op_data: *pair_regs
  rs2_op_data: *pair_regs
  rd_op_data: *pair_regs
  rs1_val_data: 'gen_sign_dataset(64)'
  rs2_val_data: 'gen_sign_dataset(64)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val64;  op2val:$rs2_val64;
    TEST_P64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $swreg, $offset, $testreg)

ursub64:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 64
  p64_profile: 'ppp'
  formattype: 'prrformat'
  rs1_op_data: *pair_regs
  rs2_op_data: *pair_regs
  rd_op_data: *pair_regs
  rs1_val_data: 'gen_usign_dataset(64)'
  rs2_val_data: 'gen_usign_dataset(64)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val64;  op2val:$rs2_val64;
    TEST_P64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $swreg, $offset, $testreg)

ksub64:
  sig:
    stride: 3
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 64
  p64_profile: 'ppp'
  formattype: 'prrformat'
  rs1_op_data: *pair_regs
  rs2_op_data: *pair_regs
  rd_op_data: *pair_regs
  rs1_val_data: 'gen_sign_dataset(64)'
  rs2_val_data: 'gen_sign_dataset(64)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val64;  op2val:$rs2_val64;
    TEST_PK64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $rs1, $swreg, $offset, $testreg)

uksub64:
  sig:
    stride: 3
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 64
  p64_profile: 'ppp'
  formattype: 'prrformat'
  rs1_op_data: *pair_regs
  rs2_op_data: *pair_regs
  rd_op_data: *pair_regs
  rs1_val_data: 'gen_usign_dataset(64)'
  rs2_val_data: 'gen_usign_dataset(64)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val64;  op2val:$rs2_val64;
    TEST_PK64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $rs1, $swreg, $offset, $testreg)
# 3.2.2 32-bit Multiply with 64-bit Add/Subtract Instructions

smar64:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  p64_profile: 'pnn'
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *pair_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

smsr64:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  p64_profile: 'pnn'
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *pair_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

umar64:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  p64_profile: 'pnn'
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *pair_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  rs2_w0_val_data: 'gen_usign_dataset(32)'
  rs2_w1_val_data: 'gen_usign_dataset(32)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

umsr64:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  p64_profile: 'pnn'
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *pair_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  rs2_w0_val_data: 'gen_usign_dataset(32)'
  rs2_w1_val_data: 'gen_usign_dataset(32)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

kmar64:
  sig:
    stride: 3
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  p64_profile: 'pnn'
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *pair_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PK64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmsr64:
  sig:
    stride: 3
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  p64_profile: 'pnn'
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *pair_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PK64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

ukmar64:
  sig:
    stride: 3
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  p64_profile: 'pnn'
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *pair_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  rs2_w0_val_data: 'gen_usign_dataset(32)'
  rs2_w1_val_data: 'gen_usign_dataset(32)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PK64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

ukmsr64:
  sig:
    stride: 3
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  p64_profile: 'pnn'
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *pair_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  rs2_w0_val_data: 'gen_usign_dataset(32)'
  rs2_w1_val_data: 'gen_usign_dataset(32)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PK64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)


# 3.3.3 Signed 16-bit Multiply with 64-bit Add/Subtract Instructions

smalbb:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  p64_profile: 'pnn'
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *pair_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

smalbt:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  p64_profile: 'pnn'
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *pair_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

smaltt:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  p64_profile: 'pnn'
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *pair_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

smalda:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  p64_profile: 'pnn'
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *pair_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

smalxda:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  p64_profile: 'pnn'
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *pair_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

smalds:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  p64_profile: 'pnn'
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *pair_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

smaldrs:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  p64_profile: 'pnn'
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *pair_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

smalxds:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  p64_profile: 'pnn'
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *pair_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

smslda:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  p64_profile: 'pnn'
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *pair_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

smslxda:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  p64_profile: 'pnn'
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *pair_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

# 3.4.1 Q15 Saturation Instructions

kaddh:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

ksubh:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

khmbb:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

khmbt:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

khmtt:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

ukaddh:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  rs2_h0_val_data: 'gen_usign_dataset(16)'
  rs2_h1_val_data: 'gen_usign_dataset(16)'
  rs2_h2_val_data: 'gen_usign_dataset(16)'
  rs2_h3_val_data: 'gen_usign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

uksubh:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_usign_dataset(16)'
  rs1_h1_val_data: 'gen_usign_dataset(16)'
  rs1_h2_val_data: 'gen_usign_dataset(16)'
  rs1_h3_val_data: 'gen_usign_dataset(16)'
  rs2_h0_val_data: 'gen_usign_dataset(16)'
  rs2_h1_val_data: 'gen_usign_dataset(16)'
  rs2_h2_val_data: 'gen_usign_dataset(16)'
  rs2_h3_val_data: 'gen_usign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

# 3.4.2 Q31 Saturation Instructions

kaddw:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

ukaddw:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  rs2_w0_val_data: 'gen_usign_dataset(32)'
  rs2_w1_val_data: 'gen_usign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

ksubw:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

uksubw:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  rs2_w0_val_data: 'gen_usign_dataset(32)'
  rs2_w1_val_data: 'gen_usign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kdmbb:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kdmbt:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kdmtt:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kslraw:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kslraw.u:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

ksllw:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pswrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_val_data: 'gen_usign_dataset(ceil(log(32,2)))'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kslliw:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwriformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  imm_val_data: 'gen_imm_dataset(5)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_PKIMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $rs1, $swreg, $offset, $testreg)

kdmabb:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kdmabt:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kdmatt:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kabsw:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    TEST_PKR_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $rs1, $swreg, $offset, $testreg)

# 3.4.3. 32-bit Computation Instructions

raddw:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

uraddw:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  rs2_w0_val_data: 'gen_usign_dataset(32)'
  rs2_w1_val_data: 'gen_usign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

rsubw:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

ursubw:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  rs2_w0_val_data: 'gen_usign_dataset(32)'
  rs2_w1_val_data: 'gen_usign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

mulr64:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  p64_profile: 'pnn'
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *pair_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs2_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  rs2_w1_val_data: 'gen_usign_dataset(32)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val;
    TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

mulsr64:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  p64_profile: 'pnn'
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *pair_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

maddr32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)'
  rs1_w1_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)'
  rs2_w0_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)'
  rs2_w1_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

msubr32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

# 3.4.4 Overflow/Saturation Status Manipulation Instructions
# alias for CSRR Rd, vxsat 
# rdov:
#   sig:
#    stride: 1
#    sz: 'XLEN/8'
#   rd_op_data: *all_regs
#   xlen: [32,64]
#   std_op:
#   isa: 
#    - IP
#   formattype: 'uformat'
#   imm_val_data: 'gen_usign_dataset(2)'
#   template: |-
# 
#     // $comment
#     // opcode: $inst ; dest:$rd
#     TEST_CASE($testreg, $rd, $correctval, $swreg, $offset, $inst $rd)

# alias for CSRRCI x0, vxsat, 1
# clrov:
#   sig:
#    stride: 1
#    sz: 'XLEN/8'
#   rd_op_data: *all_regs
#   xlen: [32,64]
#   std_op:
#   isa: 
#    - IP
#   formattype: 'uformat'
#   imm_val_data: 'gen_usign_dataset(2)'
#   template: |-
# 
#     // $comment
#     // opcode: $inst
#     TEST_CASE($testreg, x0, $correctval, $swreg, $offset, $inst)

# 3.4.5. Miscellaneous Instructions

ave:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

sra.u:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

srai.u:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  formattype: 'iformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)'
  imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)

bitrev:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

bitrevi:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  formattype: 'iformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)'
  imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)

wext:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 64, 8
  p64_profile: 'npn'
  formattype: 'ppbrrformat'
  rs1_op_data: *pair_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(64)'
  rs2_b0_val_data: 'gen_usign_dataset(8)'
  rs2_b1_val_data: 'gen_usign_dataset(8)'
  rs2_b2_val_data: 'gen_usign_dataset(8)'
  rs2_b3_val_data: 'gen_usign_dataset(8)'
  rs2_b4_val_data: 'gen_usign_dataset(8)'
  rs2_b5_val_data: 'gen_usign_dataset(8)'
  rs2_b6_val_data: 'gen_usign_dataset(8)'
  rs2_b7_val_data: 'gen_usign_dataset(8)'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val64; op2val:$rs2_val
    TEST_P64_NPN_OP($inst, $rd, $rs1, $rs1_hi, $rs2, $correctval, $rs1_val, $rs1_val_hi, $rs2_val, $swreg, $offset, $testreg)

wexti:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 64
  p64_profile: 'npi'
  formattype: 'iformat'
  rs1_op_data: *pair_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(64)'
  imm_val_data: 'gen_imm_dataset(ceil(log(32,2)))'

  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val64; immval:$imm_val
    TEST_P64_NP_OP($inst, $rd, $rs1, $rs1_hi, $correctval, $rs1_val, $rs1_val_hi, $imm_val, $swreg, $offset, $testreg)


insb:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
   - IPZicsr
  formattype: 'iformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)'
  imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2))-3)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)

# 8. RV64 Only Instructions
# Table 27. (RV64 Only) SIMD 32-bit Add/Subtract Instructions

add32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

radd32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

uradd32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  rs2_w0_val_data: 'gen_usign_dataset(32)'
  rs2_w1_val_data: 'gen_usign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

kadd32:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

ukadd32:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  rs2_w0_val_data: 'gen_usign_dataset(32)'
  rs2_w1_val_data: 'gen_usign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

sub32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

rsub32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

ursub32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  rs2_w0_val_data: 'gen_usign_dataset(32)'
  rs2_w1_val_data: 'gen_usign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

ksub32:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

uksub32:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  rs2_w0_val_data: 'gen_usign_dataset(32)'
  rs2_w1_val_data: 'gen_usign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

cras32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

rcras32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

urcras32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  rs2_w0_val_data: 'gen_usign_dataset(32)'
  rs2_w1_val_data: 'gen_usign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

kcras32:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

ukcras32:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  rs2_w0_val_data: 'gen_usign_dataset(32)'
  rs2_w1_val_data: 'gen_usign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

crsa32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

rcrsa32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

urcrsa32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  rs2_w0_val_data: 'gen_usign_dataset(32)'
  rs2_w1_val_data: 'gen_usign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

kcrsa32:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

ukcrsa32:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  rs2_w0_val_data: 'gen_usign_dataset(32)'
  rs2_w1_val_data: 'gen_usign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

stas32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

rstas32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

urstas32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  rs2_w0_val_data: 'gen_usign_dataset(32)'
  rs2_w1_val_data: 'gen_usign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

kstas32:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

ukstas32:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  rs2_w0_val_data: 'gen_usign_dataset(32)'
  rs2_w1_val_data: 'gen_usign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

stsa32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

rstsa32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

urstsa32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  rs2_w0_val_data: 'gen_usign_dataset(32)'
  rs2_w1_val_data: 'gen_usign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

kstsa32:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

ukstsa32:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  rs2_w0_val_data: 'gen_usign_dataset(32)'
  rs2_w1_val_data: 'gen_usign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

# Table 28. (RV64 Only) SIMD 32-bit Shift Instructions

sra32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pswrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_val_data: 'gen_usign_dataset(ceil(log(32,2)))'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

srai32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwriformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  imm_val_data: 'gen_imm_dataset(5)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)

sra32.u:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pswrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_val_data: 'gen_usign_dataset(ceil(log(32,2)))'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

srai32.u:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwriformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  imm_val_data: 'gen_imm_dataset(5)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)

srl32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pswrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  rs2_val_data: 'gen_usign_dataset(ceil(log(32,2)))'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

srli32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwriformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  imm_val_data: 'gen_imm_dataset(5)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)

srl32.u:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pswrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  rs2_val_data: 'gen_usign_dataset(ceil(log(32,2)))'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

srli32.u:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwriformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  imm_val_data: 'gen_imm_dataset(5)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)

sll32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pswrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  rs2_val_data: 'gen_usign_dataset(ceil(log(32,2)))'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

slli32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwriformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  imm_val_data: 'gen_imm_dataset(5)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)

ksll32:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pswrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_val_data: 'gen_usign_dataset(ceil(log(32,2)))'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kslli32:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwriformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  imm_val_data: 'gen_imm_dataset(5)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_PKIMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $rs1, $swreg, $offset, $testreg)

kslra32:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32,xlen
  formattype: 'pswrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_val_data: 'gen_sign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kslra32.u:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32,xlen
  formattype: 'pswrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  rs2_val_data: 'gen_sign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

# Table 29. (RV64 Only) SIMD 32-bit Miscellaneous Instructions

smin32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

umin32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  rs2_w0_val_data: 'gen_usign_dataset(32)'
  rs2_w1_val_data: 'gen_usign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

smax32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

umax32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  rs2_w0_val_data: 'gen_usign_dataset(32)'
  rs2_w1_val_data: 'gen_usign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

kabs32:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    TEST_PKR_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $rs1, $swreg, $offset, $testreg)

# Table 30. (RV64 Only) SIMD Q15 saturating Multiply Instructions

khmbb16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

khmbt16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

khmtt16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kdmbb16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kdmbt16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kdmtt16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kdmabb16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kdmabt16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kdmatt16:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 16
  formattype: 'phrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_h0_val_data: 'gen_sign_dataset(16)'
  rs1_h1_val_data: 'gen_sign_dataset(16)'
  rs1_h2_val_data: 'gen_sign_dataset(16)'
  rs1_h3_val_data: 'gen_sign_dataset(16)'
  rs2_h0_val_data: 'gen_sign_dataset(16)'
  rs2_h1_val_data: 'gen_sign_dataset(16)'
  rs2_h2_val_data: 'gen_sign_dataset(16)'
  rs2_h3_val_data: 'gen_sign_dataset(16)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

# Table 31. (RV64 Only) 32-bit Multiply Instructions

smbb32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

smbt32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

smtt32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

# Table 32. (RV64 Only) 32-bit Multiply & Add Instructions

kmabb32:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmabt32:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmatt32:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

# Table 33. (RV64 Only) 32-bit Parallel Multiply & Add Instructions

kmda32:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmxda32:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmada32:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmaxda32:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmads32:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmadrs32:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmaxds32:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmsda32:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

kmsxda32:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)

smds32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

smdrs32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

smxds32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  rs2_w0_val_data: 'gen_sign_dataset(32)'
  rs2_w1_val_data: 'gen_sign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

# Table 34. (RV64 Only) Non-SIMD 32-bit Shift Instructions

sraiw.u:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwriformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_sign_dataset(32)'
  rs1_w1_val_data: 'gen_sign_dataset(32)'
  imm_val_data: 'gen_imm_dataset(5)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)

# Table 35. (RV64 Only) 32-bit Packing Instructions

pkbb32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  rs2_w0_val_data: 'gen_usign_dataset(32)'
  rs2_w1_val_data: 'gen_usign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

pkbt32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  rs2_w0_val_data: 'gen_usign_dataset(32)'
  rs2_w1_val_data: 'gen_usign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

pktb32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  rs2_w0_val_data: 'gen_usign_dataset(32)'
  rs2_w1_val_data: 'gen_usign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

pktt32:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
   - IPZicsr
  bit_width: 32
  formattype: 'pwrrformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_w0_val_data: 'gen_usign_dataset(32)'
  rs1_w1_val_data: 'gen_usign_dataset(32)'
  rs2_w0_val_data: 'gen_usign_dataset(32)'
  rs2_w1_val_data: 'gen_usign_dataset(32)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
    
bseti:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZbs
    - IB
  formattype: 'iformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'zerotoxlen(xlen)'
  imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)

xperm4:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IZk
    - IZbkx
    - IZkn
    - IZks
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_usign_dataset(xlen)+gen_sign_dataset(xlen)'
  rs2_val_data: 'gen_usign_dataset(xlen)+gen_sign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

xperm8:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa:
    - IZk
    - IZbkx
    - IZkn
    - IZks
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen)+gen_sign_dataset(xlen)'
  rs2_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen)+gen_sign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

brev8:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op: brev8
  isa:
    - IZbkb
    - IZk
    - IZkn
    - IZks
  formattype: 'kformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)+gen_bitmanip_dataset(xlen,False)+[16909320,33818625,67633410,134283780,72624976414508040,145249888404506625,290483284134592770,576744443617542660]'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;
    LI($rs1,$rs1_val)
    brev8 $rd, $rs1
    RVTEST_SIGUPD($swreg,$rd,$offset)
    RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)

# place holder for gorci instruction until it is rattified
gorci:
  stride: 1
  xlen: [32,64]
  std_op: gorci
  isa:
    - IB
  formattype: 'iformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val;
    LI($rs1,$rs1_val)
    gorci $rd, $rs1, $imm_val
    SREG $rd, $offset($swreg)
    RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)

# place holder for grevi instruction until it is rattified
grevi:
  stride: 1
  xlen: [32,64]
  std_op: grevi
  isa:
    - IB
  formattype: 'iformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  template: |-

    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val;
    LI($rs1,$rs1_val)
    grevi $rd, $rs1, $imm_val
    SREG $rd, $offset($swreg)
    RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)

shfli:
  stride: 1
  xlen: [32]
  std_op: shfli
  isa:
    - IB
  formattype: 'iformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  template: |-

    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val;
    LI($rs1,$rs1_val)
    shfli $rd, $rs1, $imm_val
    SREG $rd, $offset($swreg)
    RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)

unshfli:
  stride: 1
  xlen: [32]
  std_op: unshfli
  isa:
    - IB
  formattype: 'iformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  template: |-

    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val;
    LI($rs1,$rs1_val)
    unshfli $rd, $rs1, $imm_val
    SREG $rd, $offset($swreg)
    RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)

czero.eqz:
  std_op:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  isa:
    - IZicond
  operation: 'hex(int(rs2_val != 0) * rs1_val)'
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

czero.nez:
  std_op:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  isa:
    - IZicond
  operation: 'hex(int(rs2_val == 0) * rs1_val)'
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)    

amoadd.w:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IA
    - IZaamo
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)

amoand.w:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IA
    - IZaamo
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)

amoswap.w:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IA
    - IZaamo
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)

amoxor.w:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IA
    - IZaamo
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)

amoor.w:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IA
    - IZaamo
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)

amomin.w:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IA
    - IZaamo
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)

amominu.w:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IA
    - IZaamo
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)

amomax.w:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IA
    - IZaamo
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
 
amomaxu.w:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IA
    - IZaamo
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)

amoadd.d:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - IA
    - IZaamo
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)

amoand.d:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - IA
    - IZaamo
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)

amoswap.d:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - IA
    - IZaamo
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)

amoxor.d:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - IA
    - IZaamo
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)

amoor.d:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - IA
    - IZaamo
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)

amomin.d:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - IA
    - IZaamo
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)

amominu.d:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - IA
    - IZaamo
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)

amomax.d:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - IA
    - IZaamo
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
 
amomaxu.d:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - IA
    - IZaamo
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)

amocas.w:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa:
    - IZacas
  formattype: 'rformat'
  rs1_op_data: *all_regs_mx0
  rs2_op_data: *pair_regs
  rd_op_data: *pair_regs
  rs1_val_data: 'gen_sign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)'

  template: |-

    // $comment
    // opcode: $inst ; dest:$rd; addr:$rs1; src:$rs2; swap_val:$rs2_val; swreg:$swreg; $offset
    TEST_CAS_OP($inst, $rd, $rs1, $rs2, $rs2_val, $swreg, $offset);

amocas.d_32:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32]
  std_op:
  isa:
   - IZacas
  bit_width: 64
  dcas_profile: 'pnp'
  formattype: 'dcasrformat'
  rs1_op_data: *all_regs_mx0
  rs2_op_data: *pair_regs
  rd_op_data: *pair_regs
  rs1_val_data: 'gen_sign_dataset(64)'
  rs2_val_data: 'gen_sign_dataset(64)'

  template: |-

    // $comment
    // opcode: $inst ; dest($rd, $rd_hi) addr:$rs1; src:($rs2, $rs2_hi); swap_val:($rs2_val, $rs2_val_hi); swreg:$swreg; $offset
    TEST_DCAS_OP(amocas.d, $rd, $rd_hi, $rs1, $rs2, $rs2_hi, $rs2_val, $rs2_val_hi, $swreg, $offset);

amocas.d_64:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa:
    - IZacas
  formattype: 'rformat'
  rs1_op_data: *all_regs_mx0
  rs2_op_data: *pair_regs
  rd_op_data: *pair_regs
  rs1_val_data: 'gen_sign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)'

  template: |-

    // $comment
    // opcode: $inst ; dest:$rd; addr:$rs1; src:$rs2; swap_val:$rs2_val; swreg:$swreg; $offset
    TEST_CAS_OP(amocas.d, $rd, $rs1, $rs2, $rs2_val, $swreg, $offset);

amocas.q:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa:
   - IZacas
  bit_width: 128
  dcas_profile: 'pnp'
  formattype: 'dcasrformat'
  rs1_op_data: *all_regs_mx0
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(128)'
  rs2_val_data: 'gen_sign_dataset(128)'

  template: |-

    // $comment
    // opcode: $inst ; dest($rd, $rd_hi) addr:$rs1; src:($rs2, $rs2_hi); swap_val:($rs2_val, $rs2_val_hi), swreg:$swreg, $offset
    TEST_DCAS_OP($inst, $rd, $rd_hi, $rs1, $rs2, $rs2_hi, $rs2_val, $rs2_val_hi, $swreg, $offset);

c.lbu:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *c_regs
  rd_op_data: *c_regs
  xlen: [32,64]
  std_op:
  isa: 
    - I_Zca_Zcb
  formattype: 'clformat'
  rs1_val_data: '[0]'
  imm_val_data: 'gen_usign_dataset(2)'
  template: |-

    // $comment
    // opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val
    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,0)
    
c.lhu:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *c_regs
  rd_op_data: *c_regs
  xlen: [32,64]
  std_op:
  isa: 
    - I_Zca_Zcb
  formattype: 'clformat'
  rs1_val_data: '[0]'
  imm_val_data: 'gen_usign_dataset(2)'
  template: |-

    // $comment
    // opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val
    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,0)
  
c.lh:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *c_regs
  rd_op_data: *c_regs
  xlen: [32,64]
  std_op:
  isa: 
    - I_Zca_Zcb
  formattype: 'clformat'
  rs1_val_data: '[0]'
  imm_val_data: 'gen_usign_dataset(2)'
  template: |-

    // $comment
    // opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val
    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,0)

c.sb:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *c_regs
  rs2_op_data: *c_regs
  xlen: [32,64]
  std_op:
  isa: 
    - I_Zca_Zcb
  formattype: 'csformat'
  rs1_val_data: '[0]'
  rs2_val_data: 'gen_sign_dataset(xlen)'
  imm_val_data: 'gen_usign_dataset(2)'
  template: |-

    // $comment
    // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val
    TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,0)

c.sh:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *c_regs
  rs2_op_data: *c_regs
  xlen: [32,64]
  std_op:
  isa: 
    - I_Zca_Zcb
  formattype: 'csformat'
  rs1_val_data: '[0]'
  rs2_val_data: 'gen_sign_dataset(xlen)'
  imm_val_data: 'gen_usign_dataset(2)'
  template: |-

    // $comment
    // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val
    TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,0)

c.sext.b:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - I_Zca_Zcb_Zbb
  formattype: 'ckformat'
  rs1_op_data: *c_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val;
    TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)

c.sext.h:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - I_Zca_Zcb_Zbb
  formattype: 'ckformat'
  rs1_op_data: *c_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)+[65408]'
  template: |-

    // $comment
    // opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val;
    TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)

c.zext.b:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - I_Zca_Zcb
  formattype: 'ckformat'
  rs1_op_data: *c_regs
  rs1_val_data: 'gen_usign_dataset(xlen)+[128]'
  template: |-

    // $comment
    // opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val;
    TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)

c.zext.h:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - I_Zca_Zcb_Zbb
  formattype: 'ckformat'
  rs1_op_data: *c_regs
  rs1_val_data: 'gen_usign_dataset(xlen)+[65408]'
  template: |-

    // $comment
    // opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val;
    TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)

c.zext.w:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa: 
    - I_Zca_Zcb_Zba
  formattype: 'ckformat'
  rs1_op_data: *c_regs
  rs1_val_data: 'gen_usign_dataset(xlen)+[65408]'
  template: |-

    // $comment
    // opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val;
    TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)

c.not:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - I_Zca_Zcb
  formattype: 'kformat'
  rs1_op_data: *c_regs
  rs1_val_data: 'gen_usign_dataset(xlen)+[65408]'
  template: |-

    // $comment
    // opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val;
    TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)

c.mul:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *c_regs
  rs2_op_data: *c_regs
  xlen: [32,64]
  std_op:
  isa: 
    - IM_Zca_Zcb
  formattype: 'crformat'
  operation: 'hex((rs1_val * rs2_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
  template: |-

    // $comment
    // opcode: $inst; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val
    TEST_CR_OP( $inst, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

amoadd.b:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IA
  formattype: 'rformat'
  rs1_op_data: *all_regs_mx0
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)

amoand.b:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IA
  formattype: 'rformat'
  rs1_op_data: *all_regs_mx0
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)

amoswap.b:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IA
  formattype: 'rformat'
  rs1_op_data: *all_regs_mx0
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)

amoxor.b:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IA
  formattype: 'rformat'
  rs1_op_data: *all_regs_mx0
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)

amoor.b:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IA
  formattype: 'rformat'
  rs1_op_data: *all_regs_mx0
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)

amomin.b:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IA
  formattype: 'rformat'
  rs1_op_data: *all_regs_mx0
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)

amominu.b:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IA
  formattype: 'rformat'
  rs1_op_data: *all_regs_mx0
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)

amomax.b:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IA
  formattype: 'rformat'
  rs1_op_data: *all_regs_mx0
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
 
amomaxu.b:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IA
  formattype: 'rformat'
  rs1_op_data: *all_regs_mx0
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)

amocas.b:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa:
    - IZacas
  formattype: 'rformat'
  rs1_op_data: *all_regs_mx0
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)'

  template: |-

    // $comment
    // opcode: $inst ; dest:$rd; addr:$rs1; src:$rs2; swap_val:$rs2_val; swreg:$swreg; $offset
    TEST_CAS_OP($inst, $rd, $rs1, $rs2, $rs2_val, $swreg, $offset);

amoadd.h:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IA
  formattype: 'rformat'
  rs1_op_data: *all_regs_mx0
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)

amoand.h:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IA
  formattype: 'rformat'
  rs1_op_data: *all_regs_mx0
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)

amoswap.h:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IA
  formattype: 'rformat'
  rs1_op_data: *all_regs_mx0
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)

amoxor.h:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IA
  formattype: 'rformat'
  rs1_op_data: *all_regs_mx0
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)

amoor.h:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IA
  formattype: 'rformat'
  rs1_op_data: *all_regs_mx0
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)

amomin.h:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IA
  formattype: 'rformat'
  rs1_op_data: *all_regs_mx0
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)

amominu.h:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IA
  formattype: 'rformat'
  rs1_op_data: *all_regs_mx0
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)

amomax.h:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IA
  formattype: 'rformat'
  rs1_op_data: *all_regs_mx0
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
 
amomaxu.h:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa: 
    - IA
  formattype: 'rformat'
  rs1_op_data: *all_regs_mx0
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)

amocas.h:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa:
    - IZacas
  formattype: 'rformat'
  rs1_op_data: *all_regs_mx0
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)'

  template: |-

    // $comment
    // opcode: $inst ; dest:$rd; addr:$rs1; src:$rs2; swap_val:$rs2_val; swreg:$swreg; $offset
    TEST_CAS_OP($inst, $rd, $rs1, $rs2, $rs2_val, $swreg, $offset);

mop.rr.0:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, 0, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

mop.rr.1:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, 0, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

mop.rr.2:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, 0, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

mop.rr.3:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, 0, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

mop.rr.4:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, 0, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

mop.rr.5:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, 0, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

mop.rr.6:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, 0, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

mop.rr.7:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
    TEST_RR_OP($inst, $rd, $rs1, $rs2, 0, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

mop.r.0:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
  formattype: 'iformat'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)

mop.r.1:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
  formattype: 'iformat'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)

mop.r.2:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
  formattype: 'iformat'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)

mop.r.3:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
  formattype: 'iformat'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)

mop.r.4:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
  formattype: 'iformat'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)

mop.r.5:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
  formattype: 'iformat'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)

mop.r.6:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
  formattype: 'iformat'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)

mop.r.7:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
  formattype: 'iformat'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)

mop.r.8:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
  formattype: 'iformat'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)

mop.r.9:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
  formattype: 'iformat'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)

mop.r.10:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
  formattype: 'iformat'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)

mop.r.11:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
  formattype: 'iformat'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)

mop.r.12:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
  formattype: 'iformat'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)

mop.r.13:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
  formattype: 'iformat'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)

mop.r.14:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
  formattype: 'iformat'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)

mop.r.15:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
  formattype: 'iformat'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)

mop.r.16:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
  formattype: 'iformat'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)

mop.r.17:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
  formattype: 'iformat'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)

mop.r.18:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
  formattype: 'iformat'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)

mop.r.19:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
  formattype: 'iformat'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)

mop.r.20:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
  formattype: 'iformat'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)

mop.r.21:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
  formattype: 'iformat'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)

mop.r.22:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
  formattype: 'iformat'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)

mop.r.23:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
  formattype: 'iformat'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)

mop.r.24:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
  formattype: 'iformat'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)

mop.r.25:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
  formattype: 'iformat'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)

mop.r.26:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
  formattype: 'iformat'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)

mop.r.27:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
  formattype: 'iformat'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)

mop.r.28:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
  formattype: 'iformat'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)

mop.r.29:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
  formattype: 'iformat'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)

mop.r.30:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
  formattype: 'iformat'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)

mop.r.31:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rs1_op_data: *all_regs
  rd_op_data: *all_regs
  xlen: [32,64]
  std_op:
  isa:
    - IZimop
  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
  formattype: 'iformat'
  template: |-

    // $comment
    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)

c.mop.1:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa:
    - ICZcmop
  formattype: 'cjformat'
  imm_val_data: 'gen_sign_dataset(6)'
  template: |-
    // $comment
    // opcode:$inst; immval:$imm_val
    TEST_CMOP_OP($inst, x1, $imm_val, $swreg, $testreg, $offset)

c.mop.3:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa:
    - ICZcmop
  formattype: 'cjformat'
  imm_val_data: 'gen_sign_dataset(6)'
  template: |-
    // $comment
    // opcode:$inst; immval:$imm_val
    TEST_CMOP_OP($inst, x3, $imm_val, $swreg, $testreg, $offset)

c.mop.5:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa:
    - ICZcmop
  formattype: 'cjformat'
  imm_val_data: 'gen_sign_dataset(6)'
  template: |-
    // $comment
    // opcode:$inst; immval:$imm_val
    TEST_CMOP_OP($inst, x5, $imm_val, $swreg, $testreg, $offset)

c.mop.7:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa:
    - ICZcmop
  formattype: 'cjformat'
  imm_val_data: 'gen_sign_dataset(6)'
  template: |-
    // $comment
    // opcode:$inst; immval:$imm_val
    TEST_CMOP_OP($inst, x7, $imm_val, $swreg, $testreg, $offset)

c.mop.9:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa:
    - ICZcmop
  formattype: 'cjformat'
  imm_val_data: 'gen_sign_dataset(6)'
  template: |-
    // $comment
    // opcode:$inst; immval:$imm_val
    TEST_CMOP_OP($inst, x9, $imm_val, $swreg, $testreg, $offset)

c.mop.11:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa:
    - ICZcmop
  formattype: 'cjformat'
  imm_val_data: 'gen_sign_dataset(6)'
  template: |-
    // $comment
    // opcode:$inst; immval:$imm_val
    TEST_CMOP_OP($inst, x11, $imm_val, $swreg, $testreg, $offset)

c.mop.13:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa:
    - ICZcmop
  formattype: 'cjformat'
  imm_val_data: 'gen_sign_dataset(6)'
  template: |-
    // $comment
    // opcode:$inst; immval:$imm_val
    TEST_CMOP_OP($inst, x13, $imm_val, $swreg, $testreg, $offset)

c.mop.15:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa:
    - ICZcmop
  formattype: 'cjformat'
  imm_val_data: 'gen_sign_dataset(6)'
  template: |-
    // $comment
    // opcode:$inst; immval:$imm_val
    TEST_CMOP_OP($inst, x15, $imm_val, $swreg, $testreg, $offset)

lpad-m:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa:
    - IZicfilp
  formattype: 'uformat'
  imm_val_data: 'gen_usign_dataset(20)+ gen_sp_dataset(20,False)'
  template: |-
    // $comment
    // opcode: lpad ; dest:x0; immval:$imm_val
    TEST_LPAD_MMODE($testreg, $swreg, $offset, $imm_val)

lpad-s:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa:
    - IZicfilp
  formattype: 'uformat'
  imm_val_data: 'gen_usign_dataset(20)+ gen_sp_dataset(20,False)'
  template: |-
    // $comment
    // opcode: lpad ; dest:x0; immval:$imm_val
    TEST_LPAD_SMODE($testreg, $swreg, $offset, $imm_val)

lpad-u:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa:
    - IZicfilp
  formattype: 'uformat'
  imm_val_data: 'gen_usign_dataset(20)+ gen_sp_dataset(20,False)'
  template: |-
    // $comment
    // opcode: lpad ; dest:x0; immval:$imm_val
    TEST_LPAD_UMODE($testreg, $swreg, $offset, $imm_val)

sspushpopchk_u:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32, 64]
  std_op:
  isa:
    - I_Zicfiss_Zicsr
  formattype: 'rformat'
  rs1_val_data: 'gen_sign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)'
  template: |-
    // $comment
    TEST_SSPUSH_SSPOP_OP($swreg, $offset, $rs2_val, Umode)

sspushpopchk_s:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32, 64]
  std_op:
  isa:
    - I_Zicfiss_Zicsr
  formattype: 'rformat'
  rs1_val_data: 'gen_sign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)'
  template: |-
    // $comment
    TEST_SSPUSH_SSPOP_OP($swreg, $offset, $rs2_val, Smode)

c.sspushpopchk_u:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32, 64]
  std_op:
  isa:
    - IC_Zicfiss_Zicsr
  formattype: 'crformat'
  rs1_val_data: 'gen_sign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)'
  template: |-
    // $comment
    TEST_C_SSPUSH_SSPOP_OP($swreg, $offset, $rs2_val, Umode)

c.sspushpopchk_s:
  sig:
    stride: 1
    sz: 'XLEN/8'
  xlen: [32, 64]
  std_op:
  isa:
    - IC_Zicfiss_Zicsr
  formattype: 'crformat'
  rs1_val_data: 'gen_sign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)'
  template: |-
    // $comment
    TEST_C_SSPUSH_SSPOP_OP($swreg, $offset, $rs2_val, Smode)

ssamoswap.w_s:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa:
    - IA_Zicfiss_Zicsr
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-
    // $comment
    // opcode: $inst ; dest: $rd op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; $swreg; $testreg; Priv
    #ifndef ZICFISS_SETUP_DONE
    .set zicfiss_setup_done, 0
    #define ZICFISS_SETUP_DONE 1
    #endif
    TEST_SSAMOSWAP_OP(ssamoswap.w, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $testreg, Smode)

ssamoswap.d_s:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa:
    - IA_Zicfiss_Zicsr
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-
    // $comment
    // opcode: $inst ; dest: $rd op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; $swreg; $testreg; Priv
    #ifndef ZICFISS_SETUP_DONE
    .set zicfiss_setup_done, 0
    #define ZICFISS_SETUP_DONE 1
    #endif
    TEST_SSAMOSWAP_OP(ssamoswap.d, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $testreg, Smode)

ssamoswap.w_u:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [32,64]
  std_op:
  isa:
    - IA_Zicfiss_Zicsr
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-
    // $comment
    // opcode: $inst ; dest: $rd op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; $swreg; $testreg; Priv
    #ifndef ZICFISS_SETUP_DONE
    .set zicfiss_setup_done, 0
    #define ZICFISS_SETUP_DONE 1
    #endif
    TEST_SSAMOSWAP_OP(ssamoswap.w, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $testreg, Umode)

ssamoswap.d_u:
  sig:
    stride: 2
    sz: 'XLEN/8'
  xlen: [64]
  std_op:
  isa:
    - IA_Zicfiss_Zicsr
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_regs
  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
  template: |-
    // $comment
    // opcode: $inst ; dest: $rd op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; $swreg; $testreg; Priv
    #ifndef ZICFISS_SETUP_DONE
    .set zicfiss_setup_done, 0
    #define ZICFISS_SETUP_DONE 1
    #endif
    TEST_SSAMOSWAP_OP(ssamoswap.d, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $testreg, Umode)

ssrdp_s:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rd_op_data: *all_regs_mx0
  xlen: [32,64]
  std_op:
  isa:
    - I_Zicfiss_Zicsr
  rs1_val_data: 'gen_sign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)'
  formattype: 'rformat'
  template: |-
    // $comment
    // opcode:ssrdp; dest: $rd; $swreg; $testreg; Priv
    #ifndef ZICFISS_SETUP_DONE
    .set zicfiss_setup_done, 0
    #define ZICFISS_SETUP_DONE 1
    #endif
    TEST_SSRDP_OP(ssrdp, $rd, $swreg, $testreg, Smode)

ssrdp_u:
  sig:
    stride: 1
    sz: 'XLEN/8'
  rd_op_data: *all_regs_mx0
  xlen: [32,64]
  std_op:
  isa:
    - I_Zicfiss_Zicsr
  rs1_val_data: 'gen_sign_dataset(xlen)'
  rs2_val_data: 'gen_sign_dataset(xlen)'
  formattype: 'rformat'
  template: |-
    // $comment
    // opcode:ssrdp; dest: $rd; $swreg; $testreg; Priv
    #ifndef ZICFISS_SETUP_DONE
    .set zicfiss_setup_done, 0
    #define ZICFISS_SETUP_DONE 1
    #endif
    TEST_SSRDP_OP(ssrdp, $rd, $swreg, $testreg, Umode)
