# See LICENSE.incore for details
fadd.s:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IF_Zicsr
    - IFD_Zicsr
  flen: [32,64]
  std_op:
  formattype: 'rformat'
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; 
       valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr;
       correctval:??; testreg:$testreg 
    */
    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
fadd.d:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IFD_Zicsr
  flen: [64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; 
       valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr;
       correctval:??; testreg:$testreg 
    */
    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
fadd.q:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IFDQ_Zicsr
  flen: [128]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_fregs
  rs1_val_data: 'gen_sign_dataset(128)'
  rs2_val_data: 'gen_sign_dataset(128)'
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; 
       valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr;
       correctval:??; testreg:$testreg 
    */
    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)

fsub.s:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IF_Zicsr
    - IFD_Zicsr
  flen: [32,64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
       valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr;
       correctval:??; testreg:$testreg
    */
    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
fsub.d:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IFD_Zicsr
  flen: [64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
       valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr;
       correctval:??; testreg:$testreg
    */
    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
fmul.s:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IF_Zicsr
    - IFD_Zicsr
  flen: [32,64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
       valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr;
       correctval:??; testreg:$testreg
    */
    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
fmul.d:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IFD_Zicsr
  flen: [64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
       valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr;
       correctval:??; testreg:$testreg
    */
    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
fdiv.s:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IF_Zicsr
    - IFD_Zicsr
  flen: [32,64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
       valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr;
       correctval:??; testreg:$testreg
    */
    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
fdiv.d:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IFD_Zicsr
  flen: [64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
       valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr;
       correctval:??; testreg:$testreg
    */
    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
fsqrt.s:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IF_Zicsr
    - IFD_Zicsr
  flen: [32,64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'fsrformat'
  rs1_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg;
    fcsr_val: $fcsr */
    TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
fsqrt.d:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IFD_Zicsr
  flen: [64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'fsrformat'
  rs1_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg;
    fcsr_val: $fcsr */
    TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
fmadd.s:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 3
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IF_Zicsr
    - IFD_Zicsr
  flen: [32,64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'r4format'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rs3_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
    op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val;
    testreg:$testreg; fcsr_val:$fcsr */
    TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
fmadd.d:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 3
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IFD_Zicsr
  flen: [64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'r4format'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rs3_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
    op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val;
    testreg:$testreg; fcsr_val:$fcsr */
    TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
fmsub.s:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 3
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IF_Zicsr
    - IFD_Zicsr
  flen: [32,64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'r4format'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rs3_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
    op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val;
    testreg:$testreg; fcsr_val:$fcsr */
    TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
fmsub.d:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 3
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IFD_Zicsr
  flen: [64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'r4format'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rs3_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
    op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val;
    testreg:$testreg; fcsr_val:$fcsr */
    TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
fnmadd.s:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 3
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IF_Zicsr
    - IFD_Zicsr
  flen: [32,64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'r4format'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rs3_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
    op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val;
    testreg:$testreg; fcsr_val:$fcsr */
    TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
fnmadd.d:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 3
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IFD_Zicsr
  flen: [64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'r4format'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rs3_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
    op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val;
    testreg:$testreg; fcsr_val:$fcsr */
    TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
fnmsub.s:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 3
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IF_Zicsr
    - IFD_Zicsr
  flen: [32,64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'r4format'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rs3_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
    op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val;
    testreg:$testreg; fcsr_val:$fcsr */
    TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
fnmsub.d:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 3
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IFD_Zicsr
  flen: [64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'r4format'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rs3_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
    op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val;
    testreg:$testreg; fcsr_val:$fcsr */
    TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)

fsgnj.s:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IF_Zicsr
    - IFD_Zicsr
  flen: [32,64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
       valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr;
       correctval:??; testreg:$testreg
    */
    TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
fsgnj.d:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IFD_Zicsr
  flen: [64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
       valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr;
       correctval:??; testreg:$testreg
    */
    TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2,  $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
fsgnjn.s:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IF_Zicsr
    - IFD_Zicsr
  flen: [32,64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
       valaddr_reg:$valaddr_reg; val_offset:$val_offset;  fcsr: $fcsr;
       correctval:??; testreg:$testreg
    */
    TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
fsgnjn.d:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IFD_Zicsr
  flen: [64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
       valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr;
       correctval:??; testreg:$testreg
    */
    TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
fsgnjx.s:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IF_Zicsr
    - IFD_Zicsr
  flen: [32,64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
       valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr;
       correctval:??; testreg:$testreg
    */
    TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
fsgnjx.d:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IFD_Zicsr
  flen: [64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
       valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr;
       correctval:??; testreg:$testreg
    */
    TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
fmin.s:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IF_Zicsr
    - IFD_Zicsr
  flen: [32,64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
       valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr;
       correctval:??; testreg:$testreg
    */
    TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
fmin.d:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IFD_Zicsr
  flen: [64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
       valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr;
       correctval:??; testreg:$testreg
    */
    TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
fmax.s:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IF_Zicsr
    - IFD_Zicsr
  flen: [32,64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
       valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr;
       correctval:??; testreg:$testreg
    */
    TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
fmax.d:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IFD_Zicsr
  flen: [64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
       valaddr_reg:$valaddr_reg; val_offset:$val_offset;  fcsr: $fcsr;
       correctval:??; testreg:$testreg
    */
    TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
feq.s:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IF_Zicsr
    - IFD_Zicsr
  flen: [32,64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_regs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
    valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg;
    fcsr_val: $fcsr*/
    TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
feq.d:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IFD_Zicsr
  flen: [64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_regs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
    valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg;
    fcsr_val: $fcsr*/
    TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
flt.s:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IF_Zicsr
    - IFD_Zicsr
  flen: [32,64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_regs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
    valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg;
    fcsr_val: $fcsr*/
    TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
flt.d:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IFD_Zicsr
  flen: [64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_regs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
    valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg;
    fcsr_val: $fcsr*/
    TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
fle.s:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IF_Zicsr
    - IFD_Zicsr
  flen: [32,64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_regs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
    valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg;
    fcsr_val: $fcsr*/
    TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
fle.d:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IFD_Zicsr
  flen: [64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_regs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
    valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg;
    fcsr_val: $fcsr*/
    TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
fmv.w.x:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: '4'
    val_template: "'.word $val;'"
    load_instr: "lw"
  xlen: [32,64]
  isa: 
    - IF_Zicsr
    - IFD_Zicsr
  flen: [32,64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'fsrformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_fregs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; correctval:??; testreg:$testreg;
    fcsr_val: $fcsr*/
    TEST_FPIO_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)
    
fmv.x.w:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IF_Zicsr
    - IFD_Zicsr
  flen: [32,64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'fsrformat'
  rs1_op_data: *all_fregs
  rd_op_data: *all_regs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; correctval:??; testreg:$testreg;
    fcsr_val:$fcsr*/
    TEST_FPID_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
fcvt.w.s:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IF_Zicsr
    - IFD_Zicsr
  flen: [32,64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'fsrformat'
  rs1_op_data: *all_fregs
  rd_op_data: *all_regs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg;
    fcsr_val:$fcsr*/
    TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)
    
fcvt.w.d:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IFD_Zicsr
  flen: [64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'fsrformat'
  rs1_op_data: *all_fregs
  rd_op_data: *all_regs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg;
    fcsr_val:$fcsr*/
    TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)
    
fcvt.wu.s:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IF_Zicsr
    - IFD_Zicsr
  flen: [32,64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'fsrformat'
  rs1_op_data: *all_fregs
  rd_op_data: *all_regs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg;
    fcsr_val:$fcsr*/
    TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)

fcvt.wu.d:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IFD_Zicsr
  flen: [64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'fsrformat'
  rs1_op_data: *all_fregs
  rd_op_data: *all_regs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg;
    fcsr_val:$fcsr*/
    TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)
    
fcvt.l.d:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [64]
  isa: 
    - IFD_Zicsr
  flen: [64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'fsrformat'
  rs1_op_data: *all_fregs
  rd_op_data: *all_regs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg;
    fcsr_val:$fcsr*/
    TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)

fcvt.lu.d:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [64]
  isa: 
    - IFD_Zicsr
  flen: [64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'fsrformat'
  rs1_op_data: *all_fregs
  rd_op_data: *all_regs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg;
    fcsr_val:$fcsr*/
    TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)
    
fmv.x.d:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [64]
  isa: 
    - IFD_Zicsr
  flen: [64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'fsrformat'
  rs1_op_data: *all_fregs
  rd_op_data: *all_regs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; correctval:??; testreg:$testreg;
    fcsr_val:$fcsr*/
    TEST_FPID_OP_NRM($inst, $rd, $rs1,  $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
fcvt.s.d:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IFD_Zicsr
  flen: [64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'fsrformat'
  rs1_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg;
    fcsr_val: $fcsr */
    TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
    
fcvt.d.s:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IFD_Zicsr
  flen: [64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'fsrformat'
  rs1_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; correctval:??; testreg:$testreg;
    fcsr_val: $fcsr */
    TEST_FPSR_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)  
    
fcvt.s.w:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: '4'
    val_template: "'.word $val;'"
    load_instr: "lw"
  xlen: [32,64]
  isa: 
    - IF_Zicsr
    - IFD_Zicsr
  flen: [32,64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'fsrformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_fregs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg;
    fcsr_val: $fcsr*/
    TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)

fcvt.s.wu:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: '4'
    val_template: "'.word $val;'"
    load_instr: "LREGWU"
  xlen: [32,64]
  isa: 
    - IF_Zicsr
    - IFD_Zicsr
  flen: [32,64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'fsrformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_fregs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg;
    fcsr_val: $fcsr*/
    TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)

fcvt.d.w:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: '4'
    val_template: "'.word $val;'"
    load_instr: "lw"
  xlen: [32,64]
  isa: 
    - IFD_Zicsr
  flen: [64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'fsrformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_fregs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; correctval:??; testreg:$testreg;
    fcsr_val: $fcsr*/
    TEST_FPIO_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)

fcvt.d.wu:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: '4'
    val_template: "'.word $val;'"
    load_instr: "LREGWU"
  xlen: [32,64]
  isa: 
    - IFD_Zicsr
  flen: [64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'fsrformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_fregs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; correctval:??; testreg:$testreg;
    fcsr_val: $fcsr*/
    TEST_FPIO_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)
    
fcvt.d.l:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: '8'
    val_template: "'.dword $val;'"
    load_instr: "ld"
  xlen: [64]
  isa: 
    - IFD_Zicsr
  flen: [64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'fsrformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_fregs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg;
    fcsr_val: $fcsr*/
    TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)

fcvt.d.lu:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: '8'
    val_template: "'.dword $val;'"
    load_instr: "ld"
  xlen: [64]
  isa: 
    - IFD_Zicsr
  flen: [64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'fsrformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_fregs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg;
    fcsr_val: $fcsr*/
    TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)

fmv.d.x:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: '8'
    val_template: "'.dword $val;'"
    load_instr: "ld"
  xlen: [64]
  isa: 
    - IFD_Zicsr
  flen: [64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'fsrformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_fregs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; correctval:??; testreg:$testreg;
    fcsr_val: $fcsr*/
    TEST_FPIO_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)
    
fclass.s:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa: 
    - IF_Zicsr
    - IFD_Zicsr
  flen: [32,64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'fsrformat'
  rs1_op_data: *all_fregs
  rd_op_data: *all_regs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; correctval:??; testreg:$testreg;
    fcsr_val:$fcsr*/
    TEST_FPID_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
   
fclass.d:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32, 64]
  isa: 
    - IFD_Zicsr
  flen: [64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'fsrformat'
  rs1_op_data: *all_fregs
  rd_op_data: *all_regs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; correctval:??; testreg:$testreg;
    fcsr_val:$fcsr*/
    TEST_FPID_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)

# The val nodes are present in the fmem ops right now as a hack to force allocation of flagreg. Once
# anxilliary registers are moved to their own functions, this can be removed.
fsw:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  rs1_op_data: *all_regs_mx0
  rs2_op_data: *all_fregs
  xlen: [32,64]
  isa: 
    - IF_Zicsr
    - IFD_Zicsr
  flen: [32,64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'sformat'
  ea_align_data: '[0,1,2,3]'
  rs2_val_data: '[0xABCDEF12]'
  imm_val_data: 'gen_sign_dataset(12)'
  template: |-
    // $comment
    // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg;
    // valreg: $valaddr_reg; valoffset: $val_offset
    TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset)
    
flw:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: '4'
    val_template: "''"
    load_instr: "flw"
  rs1_op_data: *all_regs_mx0 
  rd_op_data: *all_fregs
  xlen: [32,64]
  std_op:
  isa: 
    - IF_Zicsr
    - IFD_Zicsr
  flen: [32,64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  formattype: 'iformat'
  ea_align_data: '[0,1,2,3]'
  imm_val_data: 'gen_sign_dataset(12)'
  template: |-
    // $comment
    // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg
    TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg)
    
fsd:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  rs1_op_data: *all_regs_mx0
  rs2_op_data: *all_fregs
  std_op:
  xlen: [32,64]
  isa: 
    - IFD_Zicsr
  flen: [64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  formattype: 'sformat'
  ea_align_data: '[0,1,2,3]'
  rs2_val_data: '[0x0123456789ABCDEF]'
  imm_val_data: 'gen_sign_dataset(12)'
  template: |-
    // $comment
    // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg;
    // valreg: $valaddr_reg; valoffset: $val_offset
    TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset)
    
fld:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: '8'
    val_template: "''"
    load_instr: "fld"
  rs1_op_data: *all_regs_mx0 
  rd_op_data: *all_fregs
  xlen: [32,64]
  std_op:
  isa: 
    - IFD_Zicsr
  flen: [64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  formattype: 'iformat'
  ea_align_data: '[0,1,2,3]'
  imm_val_data: 'gen_sign_dataset(12)'
  template: |-
    // $comment
    // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flag_reg
    TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg)

fsq:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  rs1_op_data: *all_regs_mx0
  rs2_op_data: *all_fregs
  std_op:
  xlen: [32,64]
  isa: 
    - IFDQ_Zicsr
  flen: [128]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  formattype: 'sformat'
  ea_align_data: '[0,1,2,3]'
  rs2_val_data: '[0x0123456789ABCDEF]'
  imm_val_data: 'gen_sign_dataset(12)'
  template: |-
    // $comment
    // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg;
    // valreg: $valaddr_reg; valoffset: $val_offset
    TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset)
    
flq:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: '16'
    val_template: "''"
    load_instr: "fld"
  rs1_op_data: *all_regs_mx0 
  rd_op_data: *all_fregs
  xlen: [32,64]
  std_op:
  isa: 
    - IFDQ_Zicsr
  flen: [128]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  formattype: 'iformat'
  ea_align_data: '[0,1,2,3]'
  imm_val_data: 'gen_sign_dataset(12)'
  template: |-
    // $comment
    // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flag_reg
    TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg)
    
fcvt.l.s:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [64]
  std_op:
  isa: 
    - IF_Zicsr
    - IFD_Zicsr
  flen: [32,64]
  rm_val_data: '[0,1,2,3,4,7]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  formattype: 'fsrformat'
  rs1_op_data: *all_fregs
  rd_op_data: *all_regs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg;
    fcsr_val:$fcsr*/
    TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)
    
fcvt.lu.s:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [64]
  isa: 
    - IF_Zicsr
    - IFD_Zicsr
  flen: [32,64]
  rm_val_data: '[0,1,2,3,4,7]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'fsrformat'
  rs1_op_data: *all_fregs
  rd_op_data: *all_regs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg;
    fcsr_val:$fcsr*/
    TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)
    
fcvt.s.l:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: '8'
    val_template: "'.dword $val;'"
    load_instr: "ld"
  xlen: [64]
  isa: 
    - IF_Zicsr
    - IFD_Zicsr
  std_op:
  flen: [32,64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  formattype: 'fsrformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_fregs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg;
    fcsr_val: $fcsr*/
    TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)

fcvt.s.lu:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: '8'
    val_template: "'.dword $val;'"
    load_instr: "ld"
  xlen: [64]
  isa: 
    - IF_Zicsr
    - IFD_Zicsr
  flen: [32,64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'fsrformat'
  rs1_op_data: *all_regs
  rd_op_data: *all_fregs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg;
    fcsr_val: $fcsr*/
    TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)

#
# Zfa extension
#

fminm.s:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa:
    - IF_Zicsr_Zfa
    - IFD_Zicsr_Zfa
  flen: [32,64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
       valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr;
       correctval:??; testreg:$testreg
    */
    TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)

fminm.d:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa:
    - IFD_Zicsr_Zfa
  flen: [64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
       valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr;
       correctval:??; testreg:$testreg
    */
    TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)

fmaxm.s:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa:
    - IF_Zicsr_Zfa
    - IFD_Zicsr_Zfa
  flen: [32,64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
       valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr;
       correctval:??; testreg:$testreg
    */
    TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)

fmaxm.d:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa:
    - IFD_Zicsr_Zfa
  flen: [64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
       valaddr_reg:$valaddr_reg; val_offset:$val_offset;  fcsr: $fcsr;
       correctval:??; testreg:$testreg
    */
    TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)

fround.s:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa:
    - IF_Zicsr_Zfa
    - IFD_Zicsr_Zfa
  flen: [32,64]
  std_op:
  formattype: 'fsrformat'
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  rs1_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg;
    fcsr_val: $fcsr */
    TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)

fround.d:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa:
    - IFD_Zicsr_Zfa
  flen: [64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'fsrformat'
  rs1_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg;
    fcsr_val: $fcsr */
    TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)

froundnx.s:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa:
    - IF_Zicsr_Zfa
    - IFD_Zicsr_Zfa
  flen: [32,64]
  std_op:
  formattype: 'fsrformat'
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  rs1_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg;
    fcsr_val: $fcsr */
    TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)

froundnx.d:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa:
    - IFD_Zicsr_Zfa
  flen: [64]
  rm_val_data: '[7,0,1,2,3,4]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'fsrformat'
  rs1_op_data: *all_fregs
  rd_op_data: *all_fregs
  template: |-

    // $comment
    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg;
    fcsr_val: $fcsr */
    TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)

fmvh.x.d:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32]
  isa:
    - IFD_Zicsr_Zfa
  flen: [64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'fsrformat'
  rs1_op_data: *all_fregs
  rd_op_data: *all_regs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; correctval:??; testreg:$testreg;
    fcsr_val:$fcsr*/
    TEST_FPID_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)

fmvp.d.x:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: '4'
    val_template: "'.word $val;'"
    load_instr: "lw"
  xlen: [32]
  isa:
    - IFD_Zicsr_Zfa
  flen: [64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_regs
  rs2_op_data: *all_regs
  rd_op_data: *all_fregs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; correctval:??; testreg:$testreg;
    fcsr_val: $fcsr*/
    TEST_FPIOIO_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)

fcvtmod.w.d:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 1
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa:
    - IFD_Zicsr_Zfa
  flen: [64]
  rm_val_data: '[1]'
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'fsrformat'
  rs1_op_data: *all_fregs
  rd_op_data: *all_regs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
    val_offset:$val_offset; rmval:rtz; correctval:??; testreg:$testreg;
    fcsr_val:$fcsr*/
    TEST_FPID_OP($inst, $rd, $rs1, rtz, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)

fltq.s:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa:
    - IF_Zicsr_Zfa
    - IFD_Zicsr_Zfa
  flen: [32,64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_regs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
    valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg;
    fcsr_val: $fcsr*/
    TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)

fltq.d:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa:
    - IFD_Zicsr_Zfa
  flen: [64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_regs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
    valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg;
    fcsr_val: $fcsr*/
    TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)

fleq.s:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa:
    - IF_Zicsr_Zfa
    - IFD_Zicsr_Zfa
  flen: [32,64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_regs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
    valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg;
    fcsr_val: $fcsr*/
    TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)

fleq.d:
  sig:
    stride: 2
    sz: 'SIGALIGN'
  val:
    stride: 2
    sz: 'FLEN/8'
    val_template: "'NAN_BOXED($val,$width,FLEN)'"
    load_instr: "FLREG"
  xlen: [32,64]
  isa:
    - IFD_Zicsr_Zfa
  flen: [64]
  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
  std_op:
  formattype: 'rformat'
  rs1_op_data: *all_fregs
  rs2_op_data: *all_fregs
  rd_op_data: *all_regs
  template: |-
    // $comment
    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
    valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg;
    fcsr_val: $fcsr*/
    TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
