00000aaa # readback value from writing mie to enable interrupts
00000000
0000000b # Test 5.3.1.4: mcause from ecall going from M mode to U mode
00000000
00000000 # mtval of ecall (*** defined to be zero for now)
00000000
00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000 # skipping instruction address fault since they're impossible with compressed instrs enabled
00000001 # scause from an instruction access fault
00000000
00000000 # stval of faulting instruction address (0x0)
00000000
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
00000002 # scause from an Illegal instruction
00000000
00000000 # stval of faulting instruction (0x0)
00000000
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
00000003 # scause from Breakpoint
00000000
800003f4 # stval of breakpoint instruction adress (0x80000400)
00000000
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
00000004 # scause from load address misaligned
00000000
800003fd # stval of misaligned address (0x80000409)
00000000
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
00000005 # scause from load access
00000000
00000000 # stval of accessed adress (0x0)
00000000
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
00000006 # scause from store misaligned
00000000
80000415 # stval of address with misaligned store instr (0x80000421)
00000000
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
00000007 # scause from store access
00000000
00000000 # stval of accessed address (0x0)
00000000
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
00000008 # scause from U mode ecall 
00000000
00000000 # stval of ecall (*** defined to be zero for now)
00000000
00000000 # masked out mstatus.mpp = 0 (from U mode), mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
0007ec03 # value to indicate successful vectoring on m soft interrupt 
00000000
00000003 # scause value from m soft interrupt
80000000
00000000 # stval for msoft interrupt (0x0)
00000000
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
0007ec07 # value to indicate successful vectoring on m time interrupt 
00000000
00000007 # scause value from m time interrupt
80000000
00000000 # stval for mtime interrupt (0x0)
00000000
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
0007ec09 # value to indicate successful vectoring on s ext interrupt 
00000000
00000009 # scause value from s ext interrupt
80000000
00000000 # stval for sext interrupt (0x0)
00000000
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
0007ec0b # value to indicate successful vectoring on m ext interrupt 
00000000
0000000b # scause value from m ext interrupt
80000000
00000000 # stval for mext interrupt (0x0)
00000000
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
00000008 # scause from U mode ecall 
00000000
00000000 # stval of ecall (*** defined to be zero for now)
00000000
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000
fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
ffffffff
00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
00000000
0000000b # scause from M mode ecall 
00000000
00000000 # stval of ecall (*** defined to be zero for now)
00000000
00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000 # skipping instruction address fault since they're impossible with compressed instrs enabled
00000001 # scause from an instruction access fault
00000000
00000000 # stval of faulting instruction address (0x0)
00000000
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000000
00000002 # scause from an Illegal instruction
00000000
00000000 # stval of faulting instruction (0x0)
00000000
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000000
00000003 # scause from Breakpoint
00000000
800003f4 # stval of breakpoint instruction adress (0x80000400)
00000000
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000000
00000004 # scause from load address misaligned
00000000
800003fd # stval of misaligned address (0x80000409)
00000000
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000000
00000005 # scause from load access
00000000
00000000 # stval of accessed adress (0x0)
00000000
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000000
00000006 # scause from store misaligned
00000000
80000415 # stval of address with misaligned store instr (0x80000421)
00000000
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000000
00000007 # scause from store access
00000000
00000000 # stval of accessed address (0x0)
00000000
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000000
00000008 # scause from U mode ecall 
00000000
00000000 # stval of ecall (*** defined to be zero for now)
00000000
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000000
0007ec09 # value to indicate successful vectoring on s ext interrupt 
00000000
00000009 # scause value from s ext interrupt
80000000
00000000 # stval for sext interrupt (0x0)
00000000
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000000
00000008 # scause from U mode ecall from test termination
00000000
00000000 # stval of ecall (*** defined to be zero for now)
00000000
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000000
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