00000000 # Reset tests
00000001 # 00000000 *** commented because LCR should reset to zero but resets to 3 due to the FPGA
00000000
00000060
00000000
00000060 # read-write test
00000020 # transmitter register empty but shift register not
00000101 # transmitter is not empty when done transmitting 5 bits
00000000
00000060
00000101 # Multi-bit transmission: 5 bits
00000015
00000101 # Transmit 6 bits
0000002A
00000101 # Transmit 7 bits
0000007F
00000101 # Transmit 8 bits
ffffff80
00000101 # Odd parity
00000079
00000101 # Even parity
0000006A
00000101 # Extra stop bit
0000005B
00000002 # Transmission interrupt tests
00000401 # Interrupt generated by finished transmission
00000004
00000006 # IIR return LSR intr and LSR has an overflow error
00000063
00000004
00000001
00000001 # MODEM interrupt tests
00000000
00000011
00000001
00000000 # DSR Test
00000032
00000001
00000000 # RI Test
00000034
00000001
00000000 # DCD Test
ffffffB8
00000001
ffffffC2 # FIFO interrupt
0000C101
00000000
ffffffC1
0000C401
ffffffA5
ffffffC1
00000001
00000002
00000061
00000003
00000060
0000C101
ffffffC1
00000060
ffffffC1 # FIFO filling/overrun test
0000C401 # Threshold = 1
ffffffC1 # Threshold = 4
0000C101
0000C401
ffffffC1 # Threshold = 8
0000C101
0000C401
ffffffC1 # Threshold = 14
0000C101
0000C401
0000C101
00000061 # FIFO has data, no overrun
00000006 # wait for interrupt
ffffffA3 # FIFO overrun error
0000000b # ecall from test termination
