
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version   : 0.10.3
// timestamp : Mon May 22 12:06:50 2023 GMT
// usage     : riscv_ctg \
//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fmaxm.s.cgf \
 \
//                  -- xlen 64  \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmaxm.s instruction of the RISC-V RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fmaxm_b1 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fmaxm_b1)

RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)

inst_0:
// rs1 == rd != rs2, rs1==f31, rs2==f30, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f31; op2:f30; dest:f31; op1val:0x0; op2val:0x0;
   valaddr_reg:x3; val_offset:0*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)

inst_1:
// rs2 == rd != rs1, rs1==f30, rs2==f29, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f29; op1val:0x0; op2val:0x80000000;
   valaddr_reg:x3; val_offset:2*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f29, f30, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)

inst_2:
// rs1 == rs2 == rd, rs1==f28, rs2==f28, rd==f28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f28; op2:f28; dest:f28; op1val:0x0; op2val:0x0;
   valaddr_reg:x3; val_offset:4*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f28, f28, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2)

inst_3:
// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==f29, rs2==f31, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f29; op2:f31; dest:f30; op1val:0x0; op2val:0x80000001;
   valaddr_reg:x3; val_offset:6*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f30, f29, f31, 0, 0, x3, 6*FLEN/8, x4, x1, x2)

inst_4:
// rs1 == rs2 != rd, rs1==f26, rs2==f26, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f26; op2:f26; dest:f27; op1val:0x0; op2val:0x0;
   valaddr_reg:x3; val_offset:8*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f27, f26, f26, 0, 0, x3, 8*FLEN/8, x4, x1, x2)

inst_5:
// rs1==f27, rs2==f25, rd==f26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f27; op2:f25; dest:f26; op1val:0x0; op2val:0x807ffffe;
   valaddr_reg:x3; val_offset:10*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f26, f27, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)

inst_6:
// rs1==f24, rs2==f27, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f24; op2:f27; dest:f25; op1val:0x0; op2val:0x7fffff;
   valaddr_reg:x3; val_offset:12*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f25, f24, f27, 0, 0, x3, 12*FLEN/8, x4, x1, x2)

inst_7:
// rs1==f25, rs2==f23, rd==f24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f25; op2:f23; dest:f24; op1val:0x0; op2val:0x807fffff;
   valaddr_reg:x3; val_offset:14*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f24, f25, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)

inst_8:
// rs1==f22, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f22; op2:f24; dest:f23; op1val:0x0; op2val:0x800000;
   valaddr_reg:x3; val_offset:16*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f23, f22, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)

inst_9:
// rs1==f23, rs2==f21, rd==f22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f23; op2:f21; dest:f22; op1val:0x0; op2val:0x80800000;
   valaddr_reg:x3; val_offset:18*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f22, f23, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)

inst_10:
// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f20; op2:f22; dest:f21; op1val:0x0; op2val:0x800001;
   valaddr_reg:x3; val_offset:20*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f21, f20, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)

inst_11:
// rs1==f21, rs2==f19, rd==f20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f21; op2:f19; dest:f20; op1val:0x0; op2val:0x80855555;
   valaddr_reg:x3; val_offset:22*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f20, f21, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)

inst_12:
// rs1==f18, rs2==f20, rd==f19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f18; op2:f20; dest:f19; op1val:0x0; op2val:0x7f7fffff;
   valaddr_reg:x3; val_offset:24*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f19, f18, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)

inst_13:
// rs1==f19, rs2==f17, rd==f18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f19; op2:f17; dest:f18; op1val:0x0; op2val:0xff7fffff;
   valaddr_reg:x3; val_offset:26*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f18, f19, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)

inst_14:
// rs1==f16, rs2==f18, rd==f17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f16; op2:f18; dest:f17; op1val:0x0; op2val:0x7f800000;
   valaddr_reg:x3; val_offset:28*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f17, f16, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)

inst_15:
// rs1==f17, rs2==f15, rd==f16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f17; op2:f15; dest:f16; op1val:0x0; op2val:0xff800000;
   valaddr_reg:x3; val_offset:30*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f16, f17, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)

inst_16:
// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f14; op2:f16; dest:f15; op1val:0x0; op2val:0x7fc00000;
   valaddr_reg:x3; val_offset:32*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f15, f14, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)

inst_17:
// rs1==f15, rs2==f13, rd==f14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f15; op2:f13; dest:f14; op1val:0x0; op2val:0xffc00000;
   valaddr_reg:x3; val_offset:34*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f14, f15, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)

inst_18:
// rs1==f12, rs2==f14, rd==f13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f12; op2:f14; dest:f13; op1val:0x0; op2val:0x7fc00001;
   valaddr_reg:x3; val_offset:36*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f13, f12, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)

inst_19:
// rs1==f13, rs2==f11, rd==f12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f13; op2:f11; dest:f12; op1val:0x0; op2val:0xffc55555;
   valaddr_reg:x3; val_offset:38*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f12, f13, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)

inst_20:
// rs1==f10, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f10; op2:f12; dest:f11; op1val:0x0; op2val:0x7f800001;
   valaddr_reg:x3; val_offset:40*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f11, f10, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)

inst_21:
// rs1==f11, rs2==f9, rd==f10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f11; op2:f9; dest:f10; op1val:0x0; op2val:0xffaaaaaa;
   valaddr_reg:x3; val_offset:42*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f10, f11, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)

inst_22:
// rs1==f8, rs2==f10, rd==f9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f8; op2:f10; dest:f9; op1val:0x0; op2val:0x3f800000;
   valaddr_reg:x3; val_offset:44*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f9, f8, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)

inst_23:
// rs1==f9, rs2==f7, rd==f8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f9; op2:f7; dest:f8; op1val:0x0; op2val:0xbf800000;
   valaddr_reg:x3; val_offset:46*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f8, f9, f7, 0, 0, x3, 46*FLEN/8, x4, x1, x2)

inst_24:
// rs1==f6, rs2==f8, rd==f7,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f6; op2:f8; dest:f7; op1val:0x80000000; op2val:0x0;
   valaddr_reg:x3; val_offset:48*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f7, f6, f8, 0, 0, x3, 48*FLEN/8, x4, x1, x2)

inst_25:
// rs1==f7, rs2==f5, rd==f6,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f7; op2:f5; dest:f6; op1val:0x80000000; op2val:0x80000000;
   valaddr_reg:x3; val_offset:50*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f6, f7, f5, 0, 0, x3, 50*FLEN/8, x4, x1, x2)

inst_26:
// rs1==f4, rs2==f6, rd==f5,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f4; op2:f6; dest:f5; op1val:0x80000000; op2val:0x1;
   valaddr_reg:x3; val_offset:52*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f5, f4, f6, 0, 0, x3, 52*FLEN/8, x4, x1, x2)

inst_27:
// rs1==f5, rs2==f3, rd==f4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f5; op2:f3; dest:f4; op1val:0x80000000; op2val:0x80000001;
   valaddr_reg:x3; val_offset:54*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f4, f5, f3, 0, 0, x3, 54*FLEN/8, x4, x1, x2)

inst_28:
// rs1==f2, rs2==f4, rd==f3,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f2; op2:f4; dest:f3; op1val:0x80000000; op2val:0x2;
   valaddr_reg:x3; val_offset:56*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f3, f2, f4, 0, 0, x3, 56*FLEN/8, x4, x1, x2)

inst_29:
// rs1==f3, rs2==f1, rd==f2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f3; op2:f1; dest:f2; op1val:0x80000000; op2val:0x807ffffe;
   valaddr_reg:x3; val_offset:58*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f2, f3, f1, 0, 0, x3, 58*FLEN/8, x4, x1, x2)

inst_30:
// rs1==f0, rs2==f2, rd==f1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f0; op2:f2; dest:f1; op1val:0x80000000; op2val:0x7fffff;
   valaddr_reg:x3; val_offset:60*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f1, f0, f2, 0, 0, x3, 60*FLEN/8, x4, x1, x2)

inst_31:
// rs1==f1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f1; op2:f30; dest:f31; op1val:0x80000000; op2val:0x807fffff;
   valaddr_reg:x3; val_offset:62*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f31, f1, f30, 0, 0, x3, 62*FLEN/8, x4, x1, x2)

inst_32:
// rs2==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f30; op2:f0; dest:f31; op1val:0x80000000; op2val:0x800000;
   valaddr_reg:x3; val_offset:64*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f0, 0, 0, x3, 64*FLEN/8, x4, x1, x2)

inst_33:
// rd==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
/* opcode: fmaxm.s ; op1:f31; op2:f30; dest:f0; op1val:0x80000000; op2val:0x80800000;
   valaddr_reg:x3; val_offset:66*FLEN/8; fcsr: 0;
   correctval:??; testreg:x2
*/
TEST_FPRR_OP_NRM(fmaxm.s, f0, f31, f30, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2155872254,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(8388607,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2155872255,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(8388608,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2155872256,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(8388609,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2156221781,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2139095039,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(4286578687,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2139095040,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(4286578688,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2143289344,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(4290772992,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2143289345,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(4291122517,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2139095041,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(4289374890,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(1065353216,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(3212836864,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(1,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2147483649,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872254,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(8388607,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872255,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(8388608,32,FLEN)
NAN_BOXED(2147483648,32,FLEN)
NAN_BOXED(2155872256,32,FLEN)
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;



signature_x1_0:
    .fill 0*((SIGALIGN)/4),4,0xdeadbeef


signature_x1_1:
    .fill 68*((SIGALIGN)/4),4,0xdeadbeef

#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;

mtrap_sigptr:
    .fill 64*XLEN/32,4,0xdeadbeef

tsig_end_canary:
CANARY;
#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*XLEN/32,4,0xdeadbeef

#endif


sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
