**/work*
**/wally_*.log

.nfs*

__pycache__/
.vscode/

#External repos
addins
addins/riscv-arch-test/Makefile.include
addins/riscv-tests/target
addins/coremark/work/*
addins/embench/bd_speed/*
addins/embench/bd_size/*
benchmarks/embench/wally*.json

#vsim work files to ignore
transcript
vsim.wlf
pipelined/wlft*
wlft*
/imperas-riscv-tests/FunctionRadix_32.addr
/imperas-riscv-tests/FunctionRadix_64.addr
/imperas-riscv-tests/FunctionRadix.addr
/imperas-riscv-tests/ProgramMap.txt
/imperas-riscv-tests/logs
*.o
*.d
*.vstf
testsBP/*/*/*.elf*
testsBP/*/OBJ/*
testsBP/*/*.a
tests/wally-riscv-arch-test/riscv-test-suite/*/I/*/*
tests/riscof/riscof_work/
tests/riscof/config32.ini
tests/riscof/config64.ini
tests/linux-testgen/linux-testvectors/*
!tests/linux-testgen/linux-testvectors/tvCopier.py
!tests/linux-testgen/linux-testvectors/tvLinker.sh
!tests/linux-testgen/linux-testvectors/tvUnlinker.sh
tests/linux-testgen/buildroot
tests/linux-testgen/buildroot-image-output
tests/linux-testgen/buildroot-config-src/main.config.old
tests/linux-testgen/buildroot-config-src/linux.config.old
tests/linux-testgen/buildroot-config-src/busybox.config.old
pipelined/regression/slack-notifier/slack-webhook-url.txt
pipelined/regression/logs
fpga/generator/IP
fpga/generator/vivado.*
fpga/generator/.Xil/*
fpga/generator/WallyFPGA*
fpga/generator/reports/
fpga/generator/*.log
fpga/generator/*.jou
*.objdump*
*.signature.output
examples/asm/sumtest/sumtest
examples/asm/example/example
examples/C/sum/sum
examples/C/fir/fir
examples/fp/softfloat_demo/softfloat_demo
examples/fp/fpcalc/fpcalc
pipelined/src/fma/fma16_testgen
linux/devicetree/debug/*
!linux/devicetree/debug/dump-dts.sh
linux/testvector-generation/genCheckpoint.gdb
linux/testvector-generation/silencePipe
linux/testvector-generation/silencePipe.control
linux/testvector-generation/fixBinMem
linux/testvector-generation/qemu-serial
*.dtb
synthDC/WORK
synthDC/alib-52
synthDC/*.log
synthDC/*.svf
synthDC/runs/
synthDC/newRuns
synthDC/PPAruns
synthDC/plots/
synthDC/runArchive
synthDC/hdl
/pipelined/regression/power.saif
tests/fp/vectors/*.tv
# Temporary configs produced for synthesis
pipelined/config/rv32e_FPUoff
pipelined/config/rv32e_PMP0
pipelined/config/rv32e_PMP16
pipelined/config/rv32e_noMulDiv
pipelined/config/rv32e_noPriv
pipelined/config/rv32e_orig
pipelined/config/rv32gc_FPUoff
pipelined/config/rv32gc_PMP0
pipelined/config/rv32gc_PMP16
pipelined/config/rv32gc_noMulDiv
pipelined/config/rv32gc_noPriv
pipelined/config/rv32gc_orig
pipelined/config/rv32ic_FPUoff
pipelined/config/rv32ic_PMP0
pipelined/config/rv32ic_PMP16
pipelined/config/rv32ic_noMulDiv
pipelined/config/rv32ic_noPriv
pipelined/config/rv32ic_orig
pipelined/config/rv64gc_FPUoff
pipelined/config/rv64gc_PMP0
pipelined/config/rv64gc_PMP16
pipelined/config/rv64gc_noMulDiv
pipelined/config/rv64gc_noPriv
pipelined/config/rv64gc_orig
pipelined/config/rv64ic_FPUoff
pipelined/config/rv64ic_PMP0
pipelined/config/rv64ic_PMP16
pipelined/config/rv64ic_noMulDiv
pipelined/config/rv64ic_noPriv
pipelined/config/rv64ic_orig
synthDC/Summary.csv
pipelined/srt/exptestgen
pipelined/srt/testgen
pipelined/srt/qslc_r4a2
pipelined/srt/qslc_r4a2.sv
pipelined/srt/testvectors
