From 03653f0336c666822bcd80bb7c3a321e16ee89c8 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 7 May 2025 16:26:05 -0500 Subject: [PATCH] Fixed the xtval misaligned address issue. --- src/lsu/align.sv | 6 +++++- src/lsu/lsu.sv | 7 ++++--- src/privileged/csr.sv | 4 ++-- src/privileged/privileged.sv | 4 ++-- src/wally/wallypipelinedcore.sv | 6 +++--- 5 files changed, 16 insertions(+), 11 deletions(-) diff --git a/src/lsu/align.sv b/src/lsu/align.sv index 2d635235f..0c900b3d4 100644 --- a/src/lsu/align.sv +++ b/src/lsu/align.sv @@ -52,6 +52,7 @@ module align import cvw::*; #(parameter cvw_t P) ( output logic [P.XLEN-1:0] IEUAdrSpillE, // The next PCF for one of the two memory addresses of the spill output logic [P.XLEN-1:0] IEUAdrSpillM, // IEUAdrM for one of the two memory addresses of the spill + output logic [P.XLEN-1:0] IEUAdrxTvalM, // IEUAdrM or spilled and aligned to next page output logic SelSpillE, // During the transition between the two spill operations, the IFU should stall the pipeline output logic [P.LLEN-1:0] DCacheReadDataWordSpillM, // The final 32 bit instruction after merging the two spilled fetches into 1 instruction output logic SpillStallM); @@ -80,10 +81,13 @@ module align import cvw::*; #(parameter cvw_t P) ( /* verilator lint_off WIDTHEXPAND */ - assign IEUAdrIncrementM = {IEUAdrM[P.XLEN-1:OFFSET_LEN], {{OFFSET_LEN}{1'b0}}} + LLENINBYTES; + //assign IEUAdrIncrementM = {IEUAdrM[P.XLEN-1:OFFSET_LEN], {{OFFSET_LEN}{1'b0}}} + LLENINBYTES; + assign IEUAdrIncrementM = IEUAdrM + LLENINBYTES; /* verilator lint_on WIDTHEXPAND */ mux2 #(P.XLEN) ieuadrspillemux(.d0(IEUAdrE), .d1(IEUAdrIncrementM), .s(SelSpillE), .y(IEUAdrSpillE)); mux2 #(P.XLEN) ieuadrspillmmux(.d0(IEUAdrM), .d1(IEUAdrIncrementM), .s(SelSpillM), .y(IEUAdrSpillM)); + //assign IEUAdrxTvalM = {IEUAdrSpillM[P.XLEN-1:OFFSET_LEN], {{OFFSET_LEN}{1'b0}}}; + mux2 #(P.XLEN) ieuadrxtvalmmux(.d0(IEUAdrM), .d1({IEUAdrIncrementM[P.XLEN-1:OFFSET_LEN], {{OFFSET_LEN}{1'b0}}}), .s(SelSpillM), .y(IEUAdrxTvalM)); //////////////////////////////////////////////////////////////////////////////////////////////////// // Detect spill diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 2d6e14166..b2126ae8f 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -57,7 +57,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( input logic BigEndianM, // Swap byte order to big endian input logic sfencevmaM, // Virtual memory address fence, invalidate TLB entries output logic DCacheStallM, // D$ busy with multicycle operation - output logic [P.XLEN-1:0] IEUAdrSpillM, // IEUAdrM, but could be spilled onto the next cacheline or virtual page. + output logic [P.XLEN-1:0] IEUAdrxTvalM, // IEUAdrM, but could be spilled onto the next cacheline or virtual page. // fpu input logic [P.FLEN-1:0] FWriteDataM, // Write data from FPU input logic FpLoadStoreM, // Selects FPU as store for write data @@ -160,11 +160,12 @@ module lsu import cvw::*; #(parameter cvw_t P) ( flopenrc #(P.XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM); if(MISALIGN_SUPPORT) begin : ziccslm_align logic [P.XLEN-1:0] IEUAdrSpillE; + logic [P.XLEN-1:0] IEUAdrSpillM; align #(P) align(.clk, .reset, .StallM, .FlushM, .IEUAdrE, .IEUAdrM, .Funct3M, .FpLoadStoreM, .MemRWM, .DCacheReadDataWordM, .CacheBusHPWTStall, .SelHPTW, .ByteMaskM, .ByteMaskExtendedM, .LSUWriteDataM, .ByteMaskSpillM, .LSUWriteDataSpillM, - .IEUAdrSpillE, .IEUAdrSpillM, .SelSpillE, .DCacheReadDataWordSpillM, .SpillStallM); + .IEUAdrSpillE, .IEUAdrSpillM, .IEUAdrxTvalM, .SelSpillE, .DCacheReadDataWordSpillM, .SpillStallM); assign IEUAdrExtM = {2'b00, IEUAdrSpillM}; assign IEUAdrExtE = {2'b00, IEUAdrSpillE}; end else begin : no_ziccslm_align @@ -176,7 +177,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign LSUWriteDataSpillM = LSUWriteDataM; assign MemRWSpillM = MemRWM; assign {SpillStallM} = 1'b0; - assign IEUAdrSpillM = IEUAdrM; + assign IEUAdrxTvalM = IEUAdrM; end if(P.ZICBOZ_SUPPORTED) begin : cboz diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index f21241f0a..3a5edf2ea 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -36,7 +36,7 @@ module csr import cvw::*; #(parameter cvw_t P) ( input logic [31:0] InstrM, // current instruction input logic [31:0] InstrOrigM, // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL input logic [P.XLEN-1:0] PCM, // program counter, next PC going to trap/return logic - input logic [P.XLEN-1:0] SrcAM, IEUAdrSpillM, // SrcA and memory address from IEU + input logic [P.XLEN-1:0] SrcAM, IEUAdrxTvalM, // SrcA and memory address from IEU input logic CSRReadM, CSRWriteM, // read or write CSR input logic TrapM, // trap is occurring input logic mretM, sretM, // return instruction @@ -142,7 +142,7 @@ module csr import cvw::*; #(parameter cvw_t P) ( else case (CauseM) 12, 1, 3: NextFaultMtvalM = PCM; // Instruction page/access faults, breakpoint 2: NextFaultMtvalM = {{(P.XLEN-32){1'b0}}, InstrOrigM}; // Illegal instruction fault - 0, 4, 6, 13, 15, 5, 7: NextFaultMtvalM = IEUAdrSpillM; // Instruction misaligned, Load/Store Misaligned/page/access faults + 0, 4, 6, 13, 15, 5, 7: NextFaultMtvalM = IEUAdrxTvalM; // Instruction misaligned, Load/Store Misaligned/page/access faults default: NextFaultMtvalM = '0; // Ecall, interrupts endcase diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv index ba7aeb960..36cc33026 100644 --- a/src/privileged/privileged.sv +++ b/src/privileged/privileged.sv @@ -37,7 +37,7 @@ module privileged import cvw::*; #(parameter cvw_t P) ( input logic [P.XLEN-1:0] SrcAM, // GPR register to write input logic [31:0] InstrM, // Instruction input logic [31:0] InstrOrigM, // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL - input logic [P.XLEN-1:0] IEUAdrSpillM, // address from IEU + input logic [P.XLEN-1:0] IEUAdrxTvalM, // address from IEU input logic [P.XLEN-1:0] PCM, // program counter // control signals input logic InstrValidM, // Current instruction is valid (not flushed) @@ -133,7 +133,7 @@ module privileged import cvw::*; #(parameter cvw_t P) ( // Control and Status Registers csr #(P) csr(.clk, .reset, .FlushM, .FlushW, .StallE, .StallM, .StallW, - .InstrM, .InstrOrigM, .PCM, .SrcAM, .IEUAdrSpillM, + .InstrM, .InstrOrigM, .PCM, .SrcAM, .IEUAdrxTvalM, .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .InterruptM, .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .StoreStallD, diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index 2c07d190c..4c8fd1cfe 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -130,7 +130,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( logic [P.XLEN-1:0] IEUAdrE; logic [P.XLEN-1:0] WriteDataM; logic [P.XLEN-1:0] IEUAdrM; - logic [P.XLEN-1:0] IEUAdrSpillM; + logic [P.XLEN-1:0] IEUAdrxTvalM; logic [P.LLEN-1:0] ReadDataW; logic CommittedM; @@ -243,7 +243,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .ENVCFG_ADUE, // from csr .sfencevmaM, // connects to privilege .DCacheStallM, // connects to privilege - .IEUAdrSpillM, // connects to privilege + .IEUAdrxTvalM, // connects to privilege .LoadPageFaultM, // connects to privilege .StoreAmoPageFaultM, // connects to privilege .LoadMisalignedFaultM, // connects to privilege @@ -301,7 +301,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .InstrMisalignedFaultM, .IllegalIEUFPUInstrD, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, .MTimerInt, .MExtInt, .SExtInt, .MSwInt, - .MTIME_CLINT, .IEUAdrSpillM, .SetFflagsM, + .MTIME_CLINT, .IEUAdrxTvalM, .SetFflagsM, .InstrAccessFaultF, .HPTWInstrAccessFaultF, .HPTWInstrPageFaultF, .LoadAccessFaultM, .StoreAmoAccessFaultM, .SelHPTW, .PrivilegeModeW, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS,