diff --git a/bin/regression-wally b/bin/regression-wally index 1e8d49b50..09f1e78ea 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -513,7 +513,7 @@ def main(): TIMEOUT_DUR = 20*60 os.system('rm -f questa/fcovrvvi_ucdb/* questa/fcovrvvi_logs/* questa/fcovrvvi/*') elif args.fcov: - TIMEOUT_DUR = 1*60 + TIMEOUT_DUR = 2*60 os.system('rm -f questa/fcov_ucdb/* questa/fcov_logs/* questa/fcov/*') elif args.buildroot: TIMEOUT_DUR = 60*1440 # 1 day diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh index 8fea2d27b..725d3b201 100755 --- a/bin/wally-package-install.sh +++ b/bin/wally-package-install.sh @@ -55,10 +55,9 @@ if [ "$FAMILY" == rhel ]; then SPIKE_PACKAGES+=(dtc boost-regex boost-system) VERILATOR_PACKAGES+=(help2man perl clang ccache gperftools numactl mold) BUILDROOT_PACKAGES+=(ncurses-base ncurses ncurses-libs ncurses-devel gcc-gfortran cpio) # gcc-gfortran is only needed for compiling spec benchmarks on buildroot linux - # Extra packages not availale in rhel8, nice for Verilator and needed for sail respectively + # Extra packages not availale in rhel8, nice for Verilator if (( RHEL_VERSION >= 9 )); then VERILATOR_PACKAGES+=(perl-doc) - SAIL_PACKAGES=(z3) fi # A newer version of gcc is required for qemu OTHER_PACKAGES=(gcc-toolset-13) @@ -80,7 +79,6 @@ elif [ "$FAMILY" == ubuntu ]; then QEMU_PACKAGES+=(libfdt-dev libpixman-1-dev) SPIKE_PACKAGES+=(device-tree-compiler libboost-regex-dev libboost-system-dev) VERILATOR_PACKAGES+=(help2man perl g++ clang ccache libunwind-dev libgoogle-perftools-dev numactl perl-doc libfl2 libfl-dev zlib1g) - SAIL_PACKAGES+=(opam z3) BUILDROOT_PACKAGES+=(ncurses-base ncurses-bin libncurses-dev gfortran cpio) # gfortran is only needed for compiling spec benchmarks on buildroot linux VIVADO_PACKAGES+=(libncurses*) # Vivado hangs on the third stage of installation without this fi @@ -90,11 +88,11 @@ fi if [ "${1}" == "--check" ]; then section_header "Checking Dependencies from Package Manager" if [ "$FAMILY" == rhel ]; then - for pack in "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${SAIL_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${OTHER_PACKAGES[@]}"; do + for pack in "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${OTHER_PACKAGES[@]}"; do rpm -q "$pack" > /dev/null || (echo -e "${FAIL_COLOR}Missing packages detected (${WARNING_COLOR}$pack${FAIL_COLOR}). Run as root to auto-install or run wally-package-install.sh first.${ENDC}" && exit 1) done elif [ "$FAMILY" == ubuntu ]; then - for pack in "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${SAIL_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${OTHER_PACKAGES[@]}"; do + for pack in "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${OTHER_PACKAGES[@]}"; do dpkg -l "$pack" | grep "ii" > /dev/null || (echo -e "${FAIL_COLOR}Missing packages detected (${WARNING_COLOR}$pack${FAIL_COLOR}). Run as root to auto-install or run wally-package-install.sh first." && exit 1) done fi @@ -124,6 +122,6 @@ else # Update and Upgrade tools eval "$UPDATE_COMMAND" # Install packages listed above using appropriate package manager - sudo $PACKAGE_MANAGER install -y "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${SAIL_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${OTHER_PACKAGES[@]}" "${VIVADO_PACKAGES[@]}" + sudo $PACKAGE_MANAGER install -y "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${OTHER_PACKAGES[@]}" "${VIVADO_PACKAGES[@]}" echo -e "${SUCCESS_COLOR}Packages successfully installed.${ENDC}" fi diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 474cbe9b5..a01298869 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -7,6 +7,7 @@ ## Modified: 22 January 2023 ## Modified: 23 March 2023 ## Modified: 30 June 2024, Jordan Carlin jcarlin@hmc.edu +## Modified: 1 September 2024 ## ## Purpose: Open source tool chain installation script ## @@ -148,11 +149,6 @@ source "$RISCV"/riscv-python/bin/activate # activate python virtual environment STATUS="python packages" pip install --upgrade pip && pip install -r "$dir"/requirements.txt -# z3 is needed for sail and not availabe from dnf for rhel 8 -if (( RHEL_VERSION == 8 )); then - pip install -U z3-solver -fi - source "$RISCV"/riscv-python/bin/activate # reload python virtual environment echo -e "${SUCCESS_COLOR}Python environment successfully configured!${ENDC}" @@ -166,9 +162,7 @@ if (( RHEL_VERSION == 8 )) || (( UBUNTU_VERSION == 20 )); then section_header "Installing glib" pip install -U meson # Meson is needed to build glib cd "$RISCV" - wget https://download.gnome.org/sources/glib/2.70/glib-2.70.5.tar.xz - tar -xJf glib-2.70.5.tar.xz - rm glib-2.70.5.tar.xz + curl --location https://download.gnome.org/sources/glib/2.70/glib-2.70.5.tar.xz | tar xJ cd glib-2.70.5 meson setup _build --prefix="$RISCV" meson compile -C _build @@ -185,9 +179,7 @@ if (( RHEL_VERSION == 8 )); then if [ ! -e "$RISCV"/include/gmp.h ]; then section_header "Installing gmp" cd "$RISCV" - wget https://ftp.gnu.org/gnu/gmp/gmp-6.3.0.tar.xz - tar -xJf gmp-6.3.0.tar.xz - rm gmp-6.3.0.tar.xz + curl --location https://ftp.gnu.org/gnu/gmp/gmp-6.3.0.tar.xz | tar xJ cd gmp-6.3.0 ./configure --prefix="$RISCV" make -j "${NUM_THREADS}" @@ -322,40 +314,20 @@ else fi -# Install opam from binary disribution on rhel as it is not available from dnf -# Opam is needed to install the sail compiler -if [ "$FAMILY" == rhel ]; then - section_header "Installing/Updating Opam" - STATUS="Opam" - export OPAMROOTISOK=1 # Silence warnings about running opam as root - cd "$RISCV" - mkdir -p opam - cd opam - wget https://raw.githubusercontent.com/ocaml/opam/master/shell/install.sh - printf '%s\n' "$RISCV"/bin Y | sh install.sh # the print command provides $RISCV/bin as the installation path when prompted - cd "$RISCV" - rm -rf opam - echo -e "${SUCCESS_COLOR}Opam successfully installed/updated!${ENDC}" -fi - # Sail Compiler (https://github.com/rems-project/sail) # Sail is a formal specification language designed for describing the semantics of an ISA. # It is used to generate the RISC-V Sail Model, which is the golden reference model for RISC-V. # The Sail Compiler is written in OCaml, which is an object-oriented extension of ML, which in turn -# is a functional programming language suited to formal verification. The Sail compiler is installed -# with the opam OCaml package manager. It has so many dependencies that it can be difficult to install, -# but a binary release of it should be available soon, removing the need to use opam. +# is a functional programming language suited to formal verification. section_header "Installing/Updating Sail Compiler" STATUS="Sail Compiler" -export OPAMROOTISOK=1 # Silence warnings about running opam as root -export OPAMROOT="$RISCV"/opam -cd "$RISCV" -opam init -y --disable-sandboxing --no-setup --compiler=5.1.0 -eval "$(opam config env)" -opam update -y -opam upgrade -y -opam install sail -y -echo -e "${SUCCESS_COLOR}Sail Compiler successfully installed/updated!${ENDC}" +if [ ! -e "$RISCV"/bin/sail ]; then + cd "$RISCV" + curl --location https://github.com/rems-project/sail/releases/latest/download/sail.tar.gz | tar xvz --directory="$RISCV" --strip-components=1 + echo -e "${SUCCESS_COLOR}Sail Compiler successfully installed/updated!${ENDC}" +else + echo -e "${SUCCESS_COLOR}Sail Compiler already installed.${ENDC}" +fi # RISC-V Sail Model (https://github.com/riscv/sail-riscv) # The RISC-V Sail Model is the golden reference model for RISC-V. It is written in Sail (described above) @@ -364,7 +336,6 @@ STATUS="RISC-V Sail Model" if git_check "sail-riscv" "https://github.com/riscv/sail-riscv.git" "$RISCV/bin/riscv_sim_RV32"; then cd sail-riscv git reset --hard && git clean -f && git checkout master && git pull - export OPAMCLI=2.0 # Sail is not compatible with opam 2.1 as of 4/16/24 ARCH=RV64 make -j "${NUM_THREADS}" c_emulator/riscv_sim_RV64 2>&1 | logger sailModel; [ "${PIPESTATUS[0]}" == 0 ] ARCH=RV32 make -j "${NUM_THREADS}" c_emulator/riscv_sim_RV32 2>&1 | logger sailModel; [ "${PIPESTATUS[0]}" == 0 ] cp -f c_emulator/riscv_sim_RV64 "$RISCV"/bin/riscv_sim_RV64 @@ -372,7 +343,6 @@ if git_check "sail-riscv" "https://github.com/riscv/sail-riscv.git" "$RISCV/bin/ if [ "$clean" ]; then cd "$RISCV" rm -rf sail-riscv - rm -rf opam fi echo -e "${SUCCESS_COLOR}RISC-V Sail Model successfully installed/updated!${ENDC}" else diff --git a/bugs.txt b/bugs.txt deleted file mode 100644 index 4c5a15a3c..000000000 --- a/bugs.txt +++ /dev/null @@ -1,2 +0,0 @@ -1. [ ] AMO should always generate store faults never load faults. We are generating both. - diff --git a/examples/fp/fpcalc/fpcalc.c b/examples/fp/fpcalc/fpcalc.c index 8264b1442..16dcce225 100644 --- a/examples/fp/fpcalc/fpcalc.c +++ b/examples/fp/fpcalc/fpcalc.c @@ -224,13 +224,20 @@ __uint128_t strtoul128(char *num, int base) { } __uint128_t parseNum(char *num) { -// uint64_t result; - __uint128_t result; - int size; // size of operands in bytes (2= half, 4=single, 8 = double) + __uint128_t result = 0; + + // Ensure input is in correct form + if (num[0] == '0' && num[1] == 'x') { + num += 2; // Skip "0x" + } else if (num[0] == 'x') { + num += 1; // Skip "x" + } + + int size; // size of operands in bytes (2= half, 4=single, 8 = double) if (strlen(num) < 8) size = 2; else if (strlen(num) < 16) size = 4; else if (strlen(num) < 32) size = 8; - else if (strlen(num) < 35) size = 16; // *** will need to increase + else if (strlen(num) < 35) size = 16; // *** will need to increase else { printf("Error: only half, single, double, or quad precision supported"); exit(1); @@ -239,12 +246,32 @@ __uint128_t parseNum(char *num) { if (size != opSize) { printf("Error: inconsistent operand sizes %d and %d\n", size, opSize); exit(1); - } + } } else { opSize = size; - //printf ("Operand size is %d\n", opSize); } - result = (__uint128_t)strtoul128(num, 16); + + if (strlen(num) <= 16) { + result = (__uint128_t)strtoull(num, NULL, 16); + } + else { + while (*num) { + int value; + if (*num >= '0' && *num <= '9') + value = *num - '0'; + else if (*num >= 'a' && *num <= 'f') + value = *num - 'a' + 10; + else if (*num >= 'A' && *num <= 'F') + value = *num - 'A' + 10; + else { + printf("Error: invalid character in input\n"); + exit(1); + } + result = (result << 4) | value; + num++; + } + } + //printf("Parsed %s as 0x%lx\n", num, result); return result; } @@ -269,8 +296,7 @@ char parseRound(char *rnd) { } } -int main(int argc, char *argv[]) -{ +int main(int argc, char *argv[]) { //uint64_t xn, yn, zn; __uint128_t xn, yn, zn; char op1, op2; @@ -387,8 +413,10 @@ int main(int argc, char *argv[]) } printF128("X", x); printF128("Y", y); //sprintf(cmd, "0x%016lx %c 0x%016lx", x.v, op1, y.v); + printf("0x%016" PRIx64 "_%016" PRIx64 " %c ", x.v[1], x.v[0], op1); + printf("0x%016" PRIx64 "_%016" PRIx64 " ", y.v[1], y.v[0]); printF128(cmd, r); printFlags(); - printF128val(r); + // printF128val(r); } } } diff --git a/fpga/debug_notes.org b/fpga/debug_notes.org deleted file mode 100644 index 84952d8c5..000000000 --- a/fpga/debug_notes.org +++ /dev/null @@ -1,16 +0,0 @@ -* December 12, 2021 -Indefinite lockup in the dcache with STATE_PTW_FAULT_CPU_BUSY -InstrM = f884_3803 -PCM = ffff_ffff_8030_8004 - -Indefinite lockup in the dcache with STATE_PTW_FAULT_CPU_BUSY -InstrM = 0207_ba03 -PCM = ffff_ffff_8034_89fe - -Indefinite lockup in the dcache with STATE_PTW_FAULT_CPU_BUSY -InstrM = 0016_c383 -PCM = ffff_ffff_8030_7504 - -Indefinite lockup in the dcache with STATE_PTW_FAULT_CPU_BUSY -InstrM = 0006_a703 -PCM = ffff_ffff_8028_fa02 diff --git a/fpga/generator/bootrom.txt b/fpga/generator/bootrom.txt deleted file mode 100644 index b49f25c09..000000000 --- a/fpga/generator/bootrom.txt +++ /dev/null @@ -1,42 +0,0 @@ -94e1819300002197 -4281420141014081 -4481440143814301 -4681460145814501 -4881480147814701 -4a814a0149814901 -4c814c014b814b01 -4e814e014d814d01 -0110011b4f814f01 -059b45011161016e -0004063705fe0010 -05a000ef8006061b -0ff003930000100f -4e952e3110060e37 -c602829b0053f2b7 -2023fe02dfe312fd -829b0053f2b7007e -fe02dfe312fdc602 -4de31efd000e2023 -059bf1402573fdd0 -0000061705e20870 -0010029b01260613 -11010002806702fe -84b2842ae426e822 -892ee04aec064505 -06e000ef07e000ef -979334fd02905563 -07930177d4930204 -4089093394be2004 -04138522008905b3 -19e3014000ef2004 -64a2644260e2fe94 -6749808261056902 -dfed8b8510472783 -2423479110a73823 -10472783674910f7 -20058693ffed8b89 -05a1118737836749 -fed59be3fef5bc23 -1047278367498082 -67c98082dfed8b85 -0000808210a7a023 diff --git a/fpga/sim/bufgce.sv b/fpga/sim/bufgce.sv deleted file mode 100644 index becf25eba..000000000 --- a/fpga/sim/bufgce.sv +++ /dev/null @@ -1,11 +0,0 @@ -module BUFGCE (input logic I, input logic CE, output logic O); - - logic CE_Q; - always_latch begin - if(~I) begin - CE_Q <= CE; - end - end - assign O = CE_Q & I; - -endmodule diff --git a/fpga/sim/bufgce_div.sv b/fpga/sim/bufgce_div.sv deleted file mode 100644 index da2aa059c..000000000 --- a/fpga/sim/bufgce_div.sv +++ /dev/null @@ -1,32 +0,0 @@ -module BUFGCE_DIV #(parameter string DivideAmt = "1") - (input logic I, input logic CLR, input logic CE, output logic O); - - integer PulseCount = 0; - logic Q; - - always_ff @(posedge I, posedge CLR) begin - if(CLR) PulseCount <= 0; - else begin - if(PulseCount < (DivideAmt.atoi()/2 - 1)) - PulseCount <= PulseCount + 1; - else - PulseCount <= 0; - end - end - - assign zero = PulseCount == 0; - - - flopenr #(1) ToggleFlipFLop - (.d(~Q), - .q(Q), - .clk(I), - .reset(CLR), // reset when told by outside - .en(zero)); // only update when counter overflows - - if (DivideAmt != "1") - assign O = Q; - else - assign O = I; - -endmodule diff --git a/fpga/sim/bufgmux.sv b/fpga/sim/bufgmux.sv deleted file mode 100644 index 047a6e529..000000000 --- a/fpga/sim/bufgmux.sv +++ /dev/null @@ -1,4 +0,0 @@ -module BUFGMUX(input logic I1, input logic I0, input logic S, output logic O); - - assign O = S ? I1 : I0; -endmodule diff --git a/setup.imperas.sh b/setup.imperas.sh deleted file mode 100644 index 71d5dcfd5..000000000 --- a/setup.imperas.sh +++ /dev/null @@ -1,57 +0,0 @@ -#!/bin/bash - -IMP_HASH=56b1479 - -REPO=davidharrishmc -REPO=eroom1966 -git clone https://github.com/${REPO}/riscv-wally -b imperas - -cd riscv-wally -WALLY=$(dirname ${BASH_SOURCE[0]:-$0}) -export WALLY=$(cd "$WALLY" && pwd) - -# clone the Imperas repo -if [ ! -d external ]; then - mkdir -p external -fi -pushd external - if [ ! -f ImperasDV-HMC ]; then - git clone git@github.com:Imperas/ImperasDV-HMC.git - fi - pushd ImperasDV-HMC - git checkout $IMP_HASH - popd -popd - -# Setup Imperas -source ${WALLY}/external/ImperasDV-HMC/Imperas/bin/setup.sh -setupImperas ${WALLY}/external/ImperasDV-HMC/Imperas -export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC - -# setup QUESTA (Imperas only command, YMMV) -svsetup -questa - -pushd sim - # With IDV - IMPERAS_TOOLS=$(pwd)/imperas.ic \ - OTHERFLAGS="+TRACE2LOG_ENABLE=1 VERBOSE=1" \ - TESTDIR=${WALLY}/external/ImperasDV-HMC/tests/riscof/work/riscv-arch-test/rv64i_m/F/src/fadd_b1-01.S \ - vsim -c -do "do wally-imperas.do rv64gc" -popd - -# notes -# run the pushd external code - -#source external/ImperasDV-HMC/Imperas/bin/setup.sh -# setupImperas /home/ross/repos/active-wally/riscv-wally/external/ImperasDV-HMC/Imperas -# env | grep IMPERAS -# export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC - -IMPERAS_TOOLS=$(pwd)/imperas.ic \ -OTHERFLAGS="+TRACE2LOG_ENABLE=1 VERBOSE=1" \ -TESTDIR=../../tests/riscof_lee/work/riscv-arch-test/rv64i_m/F/src/fadd_b1-01.S \ -vsim -c -do "do wally-imperas.do rv64gc" - - -# getting library issue. -# try switching to modelsim 2022.01 diff --git a/sim/FPbuild.txt b/sim/FPbuild.txt deleted file mode 100644 index 99f414804..000000000 --- a/sim/FPbuild.txt +++ /dev/null @@ -1,56 +0,0 @@ -Procedure for Runnning SoftFloat/TestFloat with Wally - -1.) First, compile SoftFloat and TestFloat by going to the addins -directory and finding the specific build directory (e.g., -Linux_x86_64-GCC. Currently, we are using v3e of -SoftFloat/TestFloat. I am not sure of the order, but I always compile -SoftFloat first as I believe TestFloat uses the static library -SoftFloat creates. - -2.) Once compiled both, go to the tests/fp directory and run the -create_vectors.sh Linux script. In the past, we have automated this, -but I believe this has fallen into more of a manual state lately. - -3.) Then, run remove_spaces.sh which will remove spaces from the -output and put underscores between vectors (this helps differentiate -the vectors that are generated). Again, this can be combined with -Step 2. - -4.) TestFloat is run from wally/cvw/sim and sim-testfloat-batch with -its respective test. The format is ./sim-testfloat-add add. All of -the tests are listed below. This can be augmented or added to for -other FP tests given by the great SoftFloat/TestFloat output. - - cvtint - test integer conversion unit (fcvtint) - cvtfp - test floating-point conversion unit (fcvtfp) - cmp - test comparison unit's LT, LE, EQ opperations (fcmp) - add - test addition - fma - test fma - mul - test mult with fma - sub - test subtraction - div - test division - sqrt - test square root - all - test everything - -4a.) Each test will test all its vectors - if you want to test a -subset of the vectors (e.g., only binary16), you should modify the -testfloat.do in the sim directory. Change the TEST_SIZE="all" to the -specific test you want to run. For example, if you want to run only -binary16, you should set this variable to TEST_SIZE="HP". - -4b.) If you want to turn off the generation of wlf files while running -sim-testfloat-batch, you can modify testfloat.do in the sim -directory. Inside this DO file, modify the WAV file to 0 --> i.e., -set "quietly set WAV 0;" - - - - - - - - - - - - diff --git a/sim/bpred-sim.py b/sim/bpred-sim.py deleted file mode 100755 index 45c0965a1..000000000 --- a/sim/bpred-sim.py +++ /dev/null @@ -1,194 +0,0 @@ -#!/usr/bin/env python3 -################################## -# -# regression-wally -# David_Harris@Hmc.edu 25 January 2021 -# Modified by Jarred Allen -# -# Run a regression with multiple configurations in parallel and exit with -# non-zero status code if an error happened, as well as printing human-readable -# output. -# -################################## -import sys,os,shutil -import argparse - -class bcolors: - HEADER = '\033[95m' - OKBLUE = '\033[94m' - OKCYAN = '\033[96m' - OKGREEN = '\033[92m' - WARNING = '\033[93m' - FAIL = '\033[91m' - ENDC = '\033[0m' - BOLD = '\033[1m' - UNDERLINE = '\033[4m' - -from collections import namedtuple -regressionDir = os.path.dirname(os.path.abspath(__file__)) -os.chdir(regressionDir) - -TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr']) -# name: the name of this test configuration (used in printing human-readable -# output and picking logfile names) -# cmd: the command to run to test (should include the logfile as '{}', and -# the command needs to write to that file) -# grepstr: the string to grep through the log file for. The test succeeds iff -# grep finds that string in the logfile (is used by grep, so it may -# be any pattern grep accepts, see `man 1 grep` for more info). - -# edit this list to add more test cases -configs = [ - TestCase( - name="lints", - variant="all", - cmd="./lint-wally | tee {}", - grepstr="All lints run with no errors or warnings" - ) -] - - -import os -from multiprocessing import Pool, TimeoutError - -def search_log_for_text(text, logfile): - """Search through the given log file for text, returning True if it is found or False if it is not""" - grepcmd = "grep -e '%s' '%s' > /dev/null" % (text, logfile) - return os.system(grepcmd) == 0 - -def run_test_case(config): - """Run the given test case, and return 0 if the test suceeds and 1 if it fails""" - logname = "logs/"+config.variant+"_"+config.name+".log" - cmd = config.cmd.format(logname) - print(cmd) - os.chdir(regressionDir) - os.system(cmd) - if search_log_for_text(config.grepstr, logname): - print(f"{bcolors.OKGREEN}%s_%s: Success{bcolors.ENDC}" % (config.variant, config.name)) - return 0 - else: - print(f"{bcolors.FAIL}%s_%s: Failures detected in output{bcolors.ENDC}" % (config.variant, config.name)) - print(" Check %s" % logname) - return 1 - -def main(): - """Run the tests and count the failures""" - TIMEOUT_DUR = 10800 # 3 hours - - global configs - try: - os.chdir(regressionDir) - os.mkdir("logs") - #print(os.getcwd()) - #print(regressionDir) - except: - pass - try: - shutil.rmtree("wkdir") - except: - pass - finally: - os.mkdir("wkdir") - - parser = argparse.ArgumentParser(description='Runs embench with sweeps of branch predictor sizes and types.') - mode = parser.add_mutually_exclusive_group() - mode.add_argument('-r', '--ras', action='store_const', help='Sweep size of return address stack (RAS).', default=False, const=True) - mode.add_argument('-d', '--direction', action='store_const', help='Sweep size of direction prediction (2-bit, Gshare, local, etc).', default=False, const=True) - mode.add_argument('-t', '--target', action='store_const', help='Sweep size of branch target buffer (BTB).', default=False, const=True) - mode.add_argument('-c', '--iclass', action='store_const', help='Sweep size of classification (BTB) Same as -t.', default=False, const=True) - - args = parser.parse_args() - - if(args.direction): - # for direction predictor size sweep - bpdSize = [6, 8, 10, 12, 14, 16] - #bpdType = ['twobit', 'gshare', 'global', 'gshare_basic', 'global_basic', 'local_basic'] - bpdType = ['twobit', 'gshare'] - for CurrBPType in bpdType: - for CurrBPSize in bpdSize: - name = CurrBPType+str(CurrBPSize) - configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_OVERRIDE +define+BPRED_TYPE=" + str(bpdType.index(CurrBPType)) + "+define+BPRED_SIZE=" + str(CurrBPSize) - tc = TestCase( - name=name, - variant="rv32gc", - cmd="vsim > {} -c < {} -c < {} -c < {} -c < {} -c < currInstrCount] - if len(checkpointList)==0: - break - checkpoint = checkpointList[0] - logFile = logDir+"checkpoint"+str(checkpoint)+".log" - runCommand="{\nvsim -c < ${OUTDIR} :: ${OUTLOG}" - - mkdir -p ${OUTDIR} - vsim -c -do "do wally-imperas.do rv64gc" - mv transcript ${OUTLOG} -done diff --git a/sim/test b/sim/test deleted file mode 100644 index 9daeafb98..000000000 --- a/sim/test +++ /dev/null @@ -1 +0,0 @@ -test diff --git a/sim/verilator/sim-wally-batch b/sim/verilator/sim-wally-batch deleted file mode 100755 index 63b4a4cba..000000000 --- a/sim/verilator/sim-wally-batch +++ /dev/null @@ -1 +0,0 @@ -wsim -s verilator rv64gc arch64i diff --git a/sim/xcelium/README.md b/sim/xcelium/README.md new file mode 100644 index 000000000..094a939e3 --- /dev/null +++ b/sim/xcelium/README.md @@ -0,0 +1,3 @@ +## Xcelium Simulation with CVW + +NOTE: Xcelium is not regularly tested and may not work correctly. It is also not integrated with the `wsim` command used for CVW, so the config and testsuite must be manually modified in `wally.xrun` and it does not support all of the other options provided by `wsim `. diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv index 9130dc3d4..85796f060 100644 --- a/src/mmu/mmu.sv +++ b/src/mmu/mmu.sv @@ -138,8 +138,8 @@ module mmu import cvw::*; #(parameter cvw_t P, 2'b11: DataMisalignedM = |VAdr[2:0]; // ld, sd, fld, fsd endcase // When ZiCCLSM_SUPPORTED, misalgined cachable loads and stores are handled in hardware so they do not throw a misaligned fault - assign LoadMisalignedFaultM = DataMisalignedM & ReadNoAmoAccessM & ~(P.ZICCLSM_SUPPORTED & Cacheable); - assign StoreAmoMisalignedFaultM = DataMisalignedM & WriteAccessM & ~(P.ZICCLSM_SUPPORTED & Cacheable); // Store and AMO both assert WriteAccess + assign LoadMisalignedFaultM = DataMisalignedM & ReadNoAmoAccessM & ~(P.ZICCLSM_SUPPORTED & Cacheable) & ~TLBMiss; + assign StoreAmoMisalignedFaultM = DataMisalignedM & WriteAccessM & ~(P.ZICCLSM_SUPPORTED & Cacheable) & ~TLBMiss; // Store and AMO both assert WriteAccess // Access faults // If TLB miss and translating we want to not have faults from the PMA and PMP checkers. diff --git a/src/mmu/pmachecker.sv b/src/mmu/pmachecker.sv index f2a2e984b..021f448b2 100644 --- a/src/mmu/pmachecker.sv +++ b/src/mmu/pmachecker.sv @@ -75,6 +75,6 @@ module pmachecker import cvw::*; #(parameter cvw_t P) ( // Detect access faults assign PMAAccessFault = SelRegions[0] & AccessRWXC | AtomicAccessM & ~AtomicAllowed; assign PMAInstrAccessFaultF = ExecuteAccessF & PMAAccessFault; - assign PMALoadAccessFaultM = ReadAccessM & PMAAccessFault; + assign PMALoadAccessFaultM = ReadAccessM & ~WriteAccessM & PMAAccessFault; assign PMAStoreAmoAccessFaultM = (WriteAccessM | (|CMOpM)) & PMAAccessFault; endmodule diff --git a/src/mmu/pmpchecker.sv b/src/mmu/pmpchecker.sv index a97b7ff2e..a55e137ef 100644 --- a/src/mmu/pmpchecker.sv +++ b/src/mmu/pmpchecker.sv @@ -79,5 +79,5 @@ module pmpchecker import cvw::*; #(parameter cvw_t P) ( assign PMPInstrAccessFaultF = EnforcePMP & ExecuteAccessF & ~|(X & FirstMatch) ; assign PMPStoreAmoAccessFaultM = (EnforcePMP & WriteAccessM & ~|(W & FirstMatch)) | PMPCMOAccessFault; // exclusion-tag: immu-pmpstoreamoaccessfault - assign PMPLoadAccessFaultM = EnforcePMP & ReadAccessM & ~|(R & FirstMatch) ; + assign PMPLoadAccessFaultM = EnforcePMP & ReadAccessM & ~WriteAccessM & ~|(R & FirstMatch) ; endmodule diff --git a/studies/testgen/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py b/studies/testgen/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py deleted file mode 100755 index 7a5b824b5..000000000 --- a/studies/testgen/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py +++ /dev/null @@ -1,158 +0,0 @@ -#!/usr/bin/env python3 -################################## -# testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py -# -# David_Harris@hmc.edu 19 January 2021 -# -# Generate directed and random test vectors for RISC-V Design Validation. -################################## - -################################## -# libraries -################################## -from datetime import datetime -from random import randint -from random import seed -from random import getrandbits - -################################## -# functions -################################## - -def twoscomp(a): - amsb = a >> (xlen-1) - alsbs = ((1 << (xlen-1)) - 1) & a - if (amsb): - asigned = a - (1<> 32) + "\n" - r.write(line) - testnum = testnum+1 - -################################## -# main body -################################## - -# change these to suite your tests -tests = ["ADD", "SUB", "SLT", "SLTU", "XOR", "OR", "AND"] -author = "David_Harris@hmc.edu & Katherine Parry" -xlens = [32, 64] -numrand = 100; - -# setup -seed(0) # make tests reproducible - -# generate files for each test -for xlen in xlens: - formatstrlen = str(int(xlen/4)) - formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number - formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x - if (xlen == 32): - storecmd = "sw" - wordsize = 4 - else: - storecmd = "sd" - wordsize = 8 - for test in tests: - corners = [0, 1, 2, 0xFF, 0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1, - 2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1] - imperaspath = "../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "i/" - basename = "WALLY-" + test - fname = imperaspath + "src/" + basename + ".S" - refname = imperaspath + "references/" + basename + ".reference_output" - testnum = 0 - - # print custom header part - f = open(fname, "w") - r = open(refname, "w") - line = "///////////////////////////////////////////\n" - f.write(line) - lines="// "+fname+ "\n// " + author + "\n" - f.write(lines) - line ="// Created " + str(datetime.now()) - f.write(line) - - # insert generic header - h = open("testgen_header.S", "r") - for line in h: - f.write(line) - - # print directed and random test vectors - for a in corners: - for b in corners: - writeVector(a, b, storecmd, xlen) - for i in range(0,numrand): - a = getrandbits(xlen) - b = getrandbits(xlen) - writeVector(a, b, storecmd, xlen) - - - # print footer - h = open("testgen_footer.S", "r") - for line in h: - f.write(line) - - # Finish - lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n" - lines = lines + "\nRV_COMPLIANCE_DATA_END\n" - f.write(lines) - f.close() - r.close() - - - - diff --git a/studies/testgen/testgen-ADDI-XORI-ORI-ANDI-SLTI.py b/studies/testgen/testgen-ADDI-XORI-ORI-ANDI-SLTI.py deleted file mode 100644 index a25958552..000000000 --- a/studies/testgen/testgen-ADDI-XORI-ORI-ANDI-SLTI.py +++ /dev/null @@ -1,161 +0,0 @@ -#!/usr/bin/env python3 -################################## -# testgen-ADD-SUB.py -# -# David_Harris@hmc.edu 19 January 2021 -# -# Generate directed and random test vectors for RISC-V Design Validation. -################################## - -################################## -# libraries -################################## -from datetime import datetime -from random import randint -from random import seed -from random import getrandbits - -################################## -# functions -################################## - -def computeExpected(a, b, test): - if (test == "ADDI"): - return a + b - elif (test == "XORI"): - return a ^ b - elif (test == "ORI"): - return a | b - elif (test == "ANDI"): - return a & b - elif (test == "SLTI"): - return a < b - else: - die("bad test name ", test) - # exit(1) - - -def evaluateTwoComplement(b, bits): - if (b & (1 << (bits -1))!= 0): - b = b - (1 << bits) - return b - - -def randRegs(): - reg1 = randint(1,31) - reg3 = randint(1,31) - if (reg1 == 6 or reg3 == 6): - return randRegs() - else: - return reg1, reg3 - -def writeVector(a, b, storecmd): - global testnum - - - - expected = computeExpected(evaluateTwoComplement(a,xlen), evaluateTwoComplement(b, 12), test) - expected = expected % 2**xlen # drop carry if necessary - if (expected < 0): # take twos complement - expected = 2**xlen + expected - - - - reg1, reg3 = randRegs() - lines = "\n# Testcase " + str(testnum) + ": rs1:x" + str(reg1) + "(" + formatstr.format(a) - lines = lines + "), imm12:" + "(" +formatstrimm12.format(b) - lines = lines + "), result rd:x" + str(reg3) + "(" + formatstr.format(expected) +")\n" - lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n" - lines = lines + test + " x" + str(reg3) + ", x" + str(reg1) + ", SEXT_IMM(" + formatstrimm12.format(b) + ")\n" - # lines = lines + test + " x" + str(reg3) + ", x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(b) + ")\n" - lines = lines + storecmd + " x" + str(reg3) + ", " + str(wordsize*testnum) + "(x6)\n" - lines = lines + "RVTEST_IO_ASSERT_GPR_EQ(x7, " +"x" + str(reg3) +", "+formatstr.format(expected)+")\n" - f.write(lines) - if (xlen == 32): - line = formatrefstr.format(expected)+"\n" - else: - line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n" - r.write(line) - testnum = testnum+1 - -################################## -# main body -################################## - -# change these to suite your tests -tests = ["ADDI", "XORI", "ORI", "ANDI", "SLTI"] -author = "Shriya Nadgauda & Ethan Falicov" -xlens = [32, 64] -numrand = 100 - - -# setup -seed(0) # make tests reproducible - -# generate files for each test -for xlen in xlens: - formatstrlen = str(int(xlen/4)) - formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number - formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x - - formatstrimm12 = "0x{:03x}" # format as 3-bit hexadecimal number - if (xlen == 32): - storecmd = "sw" - wordsize = 4 - else: - storecmd = "sd" - wordsize = 8 - - for test in tests: - corners1 = [0, 1, 2, 0xFF, 0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1, - 2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1] - - immBitSize = 12 - corners2 = [0, 1, 2, 0xFF, 0x624 % 2**immBitSize, 2**(immBitSize-1)-2, 2**(immBitSize-1)-1, - 2**(immBitSize-1), 2**(immBitSize-1)+1, 0xC36 % 2**immBitSize, 2**(immBitSize)-2, 2**(immBitSize)-1] - - imperaspath = "../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "i/" - basename = "WALLY-" + test - fname = imperaspath + "src/" + basename + ".S" - refname = imperaspath + "references/" + basename + ".reference_output" - testnum = 0 - - # print custom header part - f = open(fname, "w") - r = open(refname, "w") - line = "///////////////////////////////////////////\n" - f.write(line) - lines="// "+fname+ "\n// " + author + "\n" - f.write(lines) - line ="// Created " + str(datetime.now()) - f.write(line) - - # insert generic header - h = open("testgen_header.S", "r") - for line in h: - f.write(line) - - # print directed and random test vectors - for a in corners1: - for b in corners2: - writeVector(a, b, storecmd) - for i in range(0,numrand): - a = getrandbits(xlen) - b = getrandbits(12) - writeVector(a, b, storecmd) - - - # print footer - h = open("testgen_footer.S", "r") - for line in h: - f.write(line) - - # Finish - lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n" - lines = lines + "\nRV_COMPLIANCE_DATA_END\n" - f.write(lines) - f.close() - r.close() - - - diff --git a/studies/testgen/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py b/studies/testgen/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py deleted file mode 100755 index 55cffb3db..000000000 --- a/studies/testgen/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py +++ /dev/null @@ -1,182 +0,0 @@ -#!/usr/bin/env python3 -################################## -# testgen-ADDIW-SLLIW-SRLIW-SRAIW.py -# -# ehedenberg@hmc.edu 4 February 2021 -# heavily influenced by Prof Harris Code -# -# Generate directed and random test vectors for RISC-V Design Validation. -################################## - -################################## -# libraries -################################## -from datetime import datetime -from random import randint -from random import seed -from random import getrandbits -import sys - -################################## -# functions -################################## -def logical_rshift(signed_integer, places): - unsigned_integer=signed_integer%(1<<32) - return unsigned_integer >> places - -def toSigned12bit(n): - n=n & 0xfff - if (n&(1<<11)): - n=n|0xfffffffffffff000 - return n - -def toSigned32bit(n): - n=n & 0xffffffff - if (n&(1<<31)): - n=n|0xffffffff00000000 - return n - - -def computeExpected(a, b, test): - if (test == "ADDIW"): - b=toSigned12bit(b) - return a + b - elif (test == "SLLIW"): - return (a << b) - elif (test == "SRLIW"): - return logical_rshift(a, b) - elif(test == "SRAIW"): - a= toSigned32bit(a) - return a >> b - else: - die("bad test name ", test) - # exit(1) - -def randRegs(): - reg1 = randint(1,31) - reg2 = randint(1,31) - reg3 = randint(1,31) - if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2): - return randRegs() - else: - return reg1, reg2, reg3 - -def writeVector(a, b, storecmd): - global testnum - expected = computeExpected(a, b, test) - expected = expected % 2**64 # drop carry if necessary - if (expected < 0): # take twos complement - expected = 2**64 + expected - #expected=expected+2^32<<32 - if (expected >= (2**32)): - expected=expected%(2**32) - expected=toSigned32bit(expected) - reg1, reg2, reg3 = randRegs() - lines = "\n# Testcase " + str(testnum) + ": rs1:x" + str(reg1) + "(" + formatstr.format(a) - lines = lines + "), imm:"+formatstr.format(b) - lines = lines + ", result rd:x" + str(reg3) + "(" + formatstr.format(expected) +")\n" - lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n" - #lines = lines + "li x" + str(reg2) + ", MASK_XLEN(" + formatstr.format(b) + ")\n" - lines = lines + test + " x" + str(reg3) + ", x" + str(reg1) + ", SEXT_IMM(" + formatstr.format(b) + ")\n" - lines = lines + storecmd + " x" + str(reg3) + ", " + str(wordsize*testnum) + "(x6)\n" - lines = lines + "RVTEST_IO_ASSERT_GPR_EQ(x7, x" + str(reg3) +", "+formatstr.format(expected)+")\n" - #lines = lines + str(b)+"\n" - f.write(lines) - if (xlen == 32): - line = formatrefstr.format(expected)+"\n" - else: - line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n" - r.write(line) - testnum = testnum+1 - -################################## -# main body -################################## - -# change these to suite your tests -tests = ["ADDIW", "SLLIW", "SRLIW", "SRAIW"] -author = "Eizabeth Hedenberg" -xlens = [64] -shiftlen=5 -addlen=12 -numrand = 100 - -# setup -seed(0) # make tests reproducible - -# generate files for each test -for xlen in xlens: - formatstrlen = str(int(xlen/4)) - #formatstrlen6=str(int()) - formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number - #formatstr6 = "0x{:0" + "2" + "x}" # format as xlen-bit hexadecimal number - formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x - if (xlen == 32): - storecmd = "sw" - wordsize = 4 - else: - storecmd = "sd" - wordsize = 8 - for test in tests: - cornersa = [0, 1, 2, 0xFF, 0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1, - 2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1] - #test both confined to top 32 and not - cornersshift=[0, 1, 2, 2**(shiftlen)-1, 2**(shiftlen)-2, 0b00101, 0b01110] - #6 bits: 0, 1, 2, largest, largest -1, largest -2, 21, 46 - cornersadd=[0, 1, 2, 2**(addlen-1), 2**(addlen-1)-1, 2**(addlen-1)-2, 2**(addlen-1)+1, 2**(addlen)-2, 2**(addlen)-1, 0b001010010101, 0b101011101111] - #12 bit, 0, 1, 2 argest positive, largest -1, largest -2, largest negative number, -2, -1, random - imperaspath = "../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "i/" - basename = "WALLY-" + test - fname = imperaspath + "src/" + basename + ".S" - refname = imperaspath + "references/" + basename + ".reference_output" - testnum = 0 - - # print custom header part - f = open(fname, "w") - r = open(refname, "w") - line = "///////////////////////////////////////////\n" - f.write(line) - lines="// "+fname+ "\n// " + author + "\n" - f.write(lines) - line ="// Created " + str(datetime.now()) - f.write(line) - - # insert generic header - h = open("testgen_header.S", "r") - for line in h: - f.write(line) - - # print directed and random test vectors - if test=="ADDIW": - for a in cornersa: - for b in cornersadd: - writeVector(a, b, storecmd) - for i in range(0,numrand): - a = getrandbits(xlen) - b = getrandbits(12) - writeVector(a, b, storecmd) - else: - for a in cornersa: - for b in cornersshift: - writeVector(a, b, storecmd) - for i in range(0,numrand): - a = getrandbits(xlen) - b = getrandbits(5) - writeVector(a, b, storecmd) - - - # print footer - h = open("testgen_footer.S", "r") - for line in h: - f.write(line) - - # Finish - lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n" - lines = lines + "\nRV_COMPLIANCE_DATA_END\n" - f.write(lines) - f.close() - r.close() - - - - diff --git a/studies/testgen/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py b/studies/testgen/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py deleted file mode 100755 index f57b95315..000000000 --- a/studies/testgen/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py +++ /dev/null @@ -1,174 +0,0 @@ -#!/usr/bin/env python3 -################################## -# testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py -# -# trao@g.hmc.edu 11 February 2021 -# Based on testgen-ADD-SUB.py by Prof. David Harris -# -# Generate directed and random test vectors for RISC-V Design Validation. -################################## - -################################## -# libraries -################################## -from datetime import datetime -from random import randint -from random import seed -from random import getrandbits -import sys - -################################## -# functions -################################## -def logical_rshift(signed_integer, places): - unsigned_integer=signed_integer%(1<<32) - return unsigned_integer >> places - -def toSigned12bit(n): - n=n & 0xfff - if (n&(1<<11)): - n=n|0xfffffffffffff000 - return n - -def toSigned32bit(n): - n=n & 0xffffffff - if (n&(1<<31)): - n=n|0xffffffff00000000 - return n - - -def computeExpected(a, b, test): - if (test == "ADDW"): - return toSigned32bit(a + b) - elif (test == "SUBW"): - return toSigned32bit(a - b) - elif (test == "SLLW"): - b = b & 0x1F - return toSigned32bit(a << b) - elif (test == "SRLW"): - b = b & 0x1F - return toSigned32bit(logical_rshift(a, b)) - elif(test == "SRAW"): - a= toSigned32bit(a) - b = b & 0x1F - return toSigned32bit(a >> b) - else: - die("bad test name ", test) - # exit(1) - -def randRegs(): - reg1 = randint(1,31) - reg2 = randint(1,31) - reg3 = randint(1,31) - if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2): - return randRegs() - else: - return reg1, reg2, reg3 - -def writeVector(a, b, storecmd): - global testnum - expected = computeExpected(a, b, test) - expected = expected % 2**xlen # drop carry if necessary - if (expected < 0): # take twos complement - expected = 2**xlen + expected - reg1, reg2, reg3 = randRegs() - lines = "\n# Testcase " + str(testnum) + ": rs1:x" + str(reg1) + "(" + formatstr.format(a) - lines = lines + "), rs2:x" + str(reg2) + "(" +formatstr.format(b) - lines = lines + "), result rd:x" + str(reg3) + "(" + formatstr.format(expected) +")\n" - lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n" - lines = lines + "li x" + str(reg2) + ", MASK_XLEN(" + formatstr.format(b) + ")\n" - lines = lines + test + " x" + str(reg3) + ", x" + str(reg1) + ", x" + str(reg2) + "\n" - lines = lines + storecmd + " x" + str(reg3) + ", " + str(wordsize*testnum) + "(x6)\n" - lines = lines + "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg3) +", "+formatstr.format(expected)+")\n" - f.write(lines) - line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n" - r.write(line) - testnum = testnum+1 - -################################## -# main body -################################## - -# change these to suite your tests -tests = ["ADDW", "SUBW", "SLLW", "SRLW", "SRAW"] -author = "Tejus Rao" -xlens = [64] -shiftlen=5 -addlen=32 -numrand = 100 - -# setup -seed(0) # make tests reproducible - -# generate files for each test -for xlen in xlens: - formatstrlen = str(int(xlen/4)) - #formatstrlen6=str(int()) - formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number - #formatstr6 = "0x{:0" + "2" + "x}" # format as xlen-bit hexadecimal number - formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x - storecmd = "sd" - wordsize = 8 - for test in tests: - cornersa = [0, 1, 2, 0xFF, 0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1, - 2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1] - #test both confined to top 32 and not - cornersshift=[0, 1, 2, 2**(shiftlen)-1, 2**(shiftlen)-2, 0b00101, 0b01110] - #6 bits: 0, 1, 2, largest, largest -1, largest -2, 21, 46 - cornersadd=[0, 1, 2, 2**(addlen-1), 2**(addlen-1)-1, 2**(addlen-1)-2, 2**(addlen-1)+1, 2**(addlen)-2, 2**(addlen)-1, 0b001010010101, 0b101011101111] - #12 bit, 0, 1, 2 argest positive, largest -1, largest -2, largest negative number, -2, -1, random - imperaspath = "../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "i/" - basename = "WALLY-" + test - fname = imperaspath + "src/" + basename + ".S" - refname = imperaspath + "references/" + basename + ".reference_output" - testnum = 0 - - # print custom header part - f = open(fname, "w") - r = open(refname, "w") - line = "///////////////////////////////////////////\n" - f.write(line) - lines="// "+fname+ "\n// " + author + "\n" - f.write(lines) - line ="// Created " + str(datetime.now()) - f.write(line) - - # insert generic header - h = open("testgen_header.S", "r") - for line in h: - f.write(line) - - # print directed and random test vectors - if test=="ADDW" or test == "SUBW": - for a in cornersa: - for b in cornersadd: - writeVector(a, b, storecmd) - for i in range(0,numrand): - a = getrandbits(xlen) - b = getrandbits(xlen) - writeVector(a, b, storecmd) - else: - for a in cornersa: - for b in cornersshift: - writeVector(a, b, storecmd) - for i in range(0,numrand): - a = getrandbits(xlen) - b = getrandbits(5) - writeVector(a, b, storecmd) - - - # print footer - h = open("testgen_footer.S", "r") - for line in h: - f.write(line) - - # Finish - lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n" - lines = lines + "\nRV_COMPLIANCE_DATA_END\n" - f.write(lines) - f.close() - r.close() - - - - diff --git a/studies/testgen/testgen-BRANCH.py b/studies/testgen/testgen-BRANCH.py deleted file mode 100755 index cf5236ad9..000000000 --- a/studies/testgen/testgen-BRANCH.py +++ /dev/null @@ -1,155 +0,0 @@ -#!/usr/bin/env python3 -################################## -# testgen-branch.py -# -# ssanghai@hmc.edu 13th Feb 2021 -# -# Generate directed and random test vectors for RISC-V Design Validation. -################################## - -################################## -# libraries -################################## -from datetime import datetime -from random import randint -from random import seed -from random import getrandbits - -################################## -# functions -################################## -def computeExpected(a, b, test): - if (test == "BEQ"): - return 0xcccc if a==b else 0xeeee - elif (test == "BNE"): - return 0xeeee if a==b else 0xcccc - elif (test == "BGEU"): - return 0xcccc if a>=b else 0xeeee - elif (test == "BLT"): - if (1<<(xlen-1)) & a: - a = a -(2**xlen) - if (1<<(xlen-1)) & b: - b = b - (2**xlen) - return 0xcccc if a=b else 0xeeee - else: - die("bad test name ", test) - # exit(1) - -def randRegs(): - reg1 = randint(2,31) - reg2 = randint(2,31) - if (reg1 == 6 or reg2 == 6 or reg1 == reg2): - return randRegs() - else: - return reg1, reg2 - -label = 0 - -def writeVector(a, b, storecmd): - global testnum - global label - expected = computeExpected(a, b, test) - expected = expected % 2**xlen # drop carry if necessary - if (expected < 0): # take twos complement - expected = 2**xlen + expected - reg1, reg2 = randRegs() - lines = "\n# Testcase " + str(testnum) + ": rs1:x" + str(reg1) + "(" + formatstr.format(a) - lines = lines + "), rs2:x" + str(reg2) + "(" +formatstr.format(b) + "\n" - lines = lines + "li x1, MASK_XLEN(0xcccc)\n" - lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n" - lines = lines + "li x" + str(reg2) + ", MASK_XLEN(" + formatstr.format(b) + ")\n" - lines = lines + test + " x" + str(reg1) + ", x" + str(reg2) + ", " + str(label) + "f\n" - lines = lines + "li x1, MASK_XLEN(0xeeee)\n" - lines = lines + str(label) + ":\n" - lines = lines + storecmd + " x1, " + str(wordsize*testnum) + "(x6)\n" - lines = lines + "RVTEST_IO_ASSERT_GPR_EQ(x7, x1, "+formatstr.format(expected)+")\n" - f.write(lines) - if (xlen == 32): - line = formatrefstr.format(expected)+"\n" - else: - line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n" - r.write(line) - label += 1 - testnum = testnum+1 - -################################## -# main body -################################## - -# change these to suite your tests -tests = ["BEQ", "BNE", "BLT", "BGE", "BGEU", "BLTU"] -author = "Shreya Sanghai" -xlens = [32, 64] -numrand = 100 - -# setup -seed(0) # make tests reproducible - -# generate files for each test -for xlen in xlens: - formatstrlen = str(int(xlen/4)) - formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number - formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x - if (xlen == 32): - storecmd = "sw" - wordsize = 4 - else: - storecmd = "sd" - wordsize = 8 - for test in tests: - corners = [0, 1, 2, 0xFF, 0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1, - 2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1] - imperaspath = "../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "i/" - basename = "WALLY-" + test - fname = imperaspath + "src/" + basename + ".S" - refname = imperaspath + "references/" + basename + ".reference_output" - testnum = 0 - - # print custom header part - f = open(fname, "w") - r = open(refname, "w") - line = "///////////////////////////////////////////\n" - f.write(line) - lines="// "+fname+ "\n// " + author + "\n" - f.write(lines) - line ="// Created " + str(datetime.now()) - f.write(line) - - # insert generic header - h = open("testgen_header.S", "r") - for line in h: - f.write(line) - - # print directed and random test vectors - for a in corners: - for b in corners: - writeVector(a, b, storecmd) - for i in range(0,numrand): - a = getrandbits(xlen) - b = getrandbits(xlen) - writeVector(a, b, storecmd) - - - # print footer - h = open("testgen_footer.S", "r") - for line in h: - f.write(line) - - # Finish - lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n" - lines = lines + "\nRV_COMPLIANCE_DATA_END\n" - f.write(lines) - f.close() - r.close() - - - - diff --git a/studies/testgen/testgen-CSR.py b/studies/testgen/testgen-CSR.py deleted file mode 100644 index 7f74b1658..000000000 --- a/studies/testgen/testgen-CSR.py +++ /dev/null @@ -1,218 +0,0 @@ -#!/usr/bin/env python3 -################################## -# testgen-ADD-SUB.py -# -# ushakya@hmc.edu & dottolia@hmc.edu 14 Feb 2021 -# Modified: ushakya@hmc.edu 21 April 2021 -# -# Generate directed and random test vectors for RISC-V Design Validation. -################################## - -################################## -# libraries -################################## -from datetime import datetime -from random import randint -from random import seed -from random import getrandbits - -################################## -# functions -################################## - -def randRegs(): - reg1 = randint(1,31) - reg2 = randint(1,31) - reg3 = randint(1,31) - if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2): - return randRegs() - else: - return reg1, reg2, reg3 - -def writeVector(a, b, storecmd): - global testnum - csr = "mscratch" - - reg1, reg2, reg3 = randRegs() - lines = "\n# Testcase " + str(testnum) + ": " + csr + "\n" - lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n" - lines = lines + "li x" + str(reg2) + ", MASK_XLEN(0)\n" - - # Page 6 of unpriviledged spec - # For both CSRRS and CSRRC, if rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects - - expected = a - - if test == "csrrw": - if testnum == 0: - # this is a corner case (reading and writing same register) - expected = 4 - lines += "li x" + str(reg2) + ", MASK_XLEN(" + formatstr.format(0x8) + ")\n" - lines += "la x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(0x4) + ")\n" - lines += "csrrw x" + str(reg3) + ", mtvec, x" + str(reg1) + "\n" - lines += test + " x" + str(reg2) + ", mtvec, x" + str(reg2) + "\n" - lines += "csrrw x0, mtvec, x" + str(reg3) + "\n" - else: - lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n" - lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n" - - elif test == "csrrs": # at some point, try writing a non-zero value first - lines += "csrrw x0, " + csr + ", x0\n" # set csr to 0 - - lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n" - lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n" - elif test == "csrrc": # at some point, try writing a non-one value first - allOnes = "0xFFFFFFFF" if xlen == 32 else "0xFFFFFFFFFFFFFFFF" - - lines += "li x" + str(reg1) + ", MASK_XLEN(" + allOnes + ")\n" - lines += "csrrw x0, " + csr + ", x" + str(reg1) + "\n" # set csr to all ones - - lines += "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n" - - lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n" - lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n" - - expected = a ^ 0xFFFFFFFF if xlen == 32 else a ^ 0xFFFFFFFFFFFFFFFF - elif test == "csrrwi": - a = a & 0x1F # imm is only 5 bits - - lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n" - lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n" - - expected = a - elif test == "csrrsi": # at some point, try writing a non-zero value first - a = a & 0x1F - - lines += "csrrw x0, " + csr + ", x0\n" # set csr to 0 - - lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n" - lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n" - - expected = a - elif test == "csrrci": # at some point, try writing a non-one value first - a = a & 0x1F - allOnes = "0xFFFFFFFF" if xlen == 32 else "0xFFFFFFFFFFFFFFFF" - - lines += "li x" + str(reg1) + ", MASK_XLEN(" + allOnes + ")\n" - lines += "csrrw x0, " + csr + ", x" + str(reg1) + "\n" # set csr to all ones - - lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n" - lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n" - - expected = a ^ 0xFFFFFFFF if xlen == 32 else a ^ 0xFFFFFFFFFFFFFFFF - - - lines += storecmd + " x" + str(reg2) + ", " + str(wordsize*testnum) + "(x6)\n" - lines += "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg2) +", "+formatstr.format(expected)+")\n" - f.write(lines) - if (xlen == 32): - line = formatrefstr.format(expected)+"\n" - else: - line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n" - r.write(line) - testnum = testnum+1 - -def writeSpec(a, storecmd): - global testnum - csr = "mscratch" - reg1 = 3 - reg2 = 3 - - lines = "\n# Testcase " + str(testnum) + ": " + csr + "\n" - lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n" - expected = a - - lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n" - lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n" - - lines += storecmd + " x" + str(reg2) + ", " + str(wordsize*testnum) + "(x6)\n" - lines += "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg2) +", "+formatstr.format(expected)+")\n" - f.write(lines) - if (xlen == 32): - line = formatrefstr.format(expected)+"\n" - else: - line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n" - r.write(line) - testnum = testnum+1 - -################################## -# main body -################################## - -# change these to suite your tests -# csrrw, csrrs, csrrc, csrrwi, csrrsi, csrrci -tests = ["csrrw", "csrrs", "csrrc", "csrrwi", "csrrsi", "csrrci"] -author = "ushakya@hmc.edu & dottolia@hmc.edu" -xlens = [32, 64] -numrand = 60; - -# setup -seed(0xC365DDEB9173AB42) # make tests reproducible - -# generate files for each test -for xlen in xlens: - formatstrlen = str(int(xlen/4)) - formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number - formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x - if (xlen == 32): - storecmd = "sw" - wordsize = 4 - else: - storecmd = "sd" - wordsize = 8 - for test in tests: - corners = [ - 0, 1, 2, 0x1E, 0x1F, 0xFF, - 0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1, - 2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1 - ] - imperaspath = "../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "i/" - basename = "WALLY-" + test.upper() - fname = imperaspath + "src/" + basename + ".S" - refname = imperaspath + "references/" + basename + ".reference_output" - testnum = 0 - - # print custom header part - f = open(fname, "w") - r = open(refname, "w") - line = "///////////////////////////////////////////\n" - f.write(line) - lines="// "+fname+ "\n// " + author + "\n" - f.write(lines) - line ="// Created " + str(datetime.now()) - f.write(line) - - # insert generic header - h = open("testgen_header.S", "r") - for line in h: - f.write(line) - - # print directed and random test vectors - # test that reading and writing from same register work - if test == "csrrw": - a = getrandbits(xlen) - #writeSpec(a, storecmd) - for a in corners: - for b in corners: - writeVector(a, b, storecmd) - for i in range(0,numrand): - a = getrandbits(xlen) - b = getrandbits(xlen) - writeVector(a, b, storecmd) - - - # print footer - h = open("testgen_footer.S", "r") - for line in h: - f.write(line) - - # Finish - lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -4\n" - lines = lines + "\nRV_COMPLIANCE_DATA_END\n" - f.write(lines) - f.close() - r.close() - - - - diff --git a/studies/testgen/testgen-JAL-JALR.py b/studies/testgen/testgen-JAL-JALR.py deleted file mode 100755 index 7ce482bd5..000000000 --- a/studies/testgen/testgen-JAL-JALR.py +++ /dev/null @@ -1,286 +0,0 @@ -#!/usr/bin/env python3 -################################## -# testgen-JAL.py -# -# Ben Bracker (bbracker@hmc.edu) 19 January 2021 -# Based on testgen-ADD-SUB.py by David Harris -# -# Generate directed and random test vectors for RISC-V Design Validation. -################################## - -################################## -# libraries -################################## -from datetime import datetime -from random import randint -from random import choice -from random import seed -from random import getrandbits -from copy import deepcopy - -################################## -# helper functions -################################## -def InitTestGroup(): - global TestGroup,TestGroupSizes,AllRegs,UnusedRegs,StoreAdrReg - TestGroup += 1 - TestGroupSizes.append(0) - UnusedRegs = deepcopy(AllRegs) - oldStoreAdrReg = StoreAdrReg - while ((StoreAdrReg == oldStoreAdrReg) or (StoreAdrReg == 0) or (StoreAdrReg == 31)): - StoreAdrReg = choice(UnusedRegs) - UnusedRegs.remove(StoreAdrReg) - f.write("\n # ---------------------------------------------------------------------------------------------\n") - f.write(" # new register for address of test results\n") - addInst(" la x"+str(StoreAdrReg)+", test_1_res\n") - f.write(" # ---------------------------------------------------------------------------------------------\n") - -def registerSelect(): - # ensures that rd experiences all possible registers - # *** does not yet ensure that rs experiences all possible registers - # ensures that at least once rd = rs - global UnusedRegs - if len(UnusedRegs)==0: - InitTestGroup() - rd = choice(UnusedRegs) - UnusedRegs.remove(rd) - OtherRegs = deepcopy(UnusedRegs) - if 0 in OtherRegs: - OtherRegs.remove(0) - if len(OtherRegs) == 0: - OtherRegs = deepcopy(AllRegs) - OtherRegs.remove(0) - rs = choice(OtherRegs) - OtherRegs = deepcopy(AllRegs) - OtherRegs.remove(StoreAdrReg) - OtherRegs.remove(rd) - if 0 in OtherRegs: - OtherRegs.remove(0) - if rs in OtherRegs: - OtherRegs.remove(rs) - DataReg = choice(OtherRegs) - OtherRegs.remove(DataReg) - OtherRd = choice(OtherRegs) - return (rd,rs,DataReg,OtherRd) - -def addInst(line): - global CurrAdr - f.write(line) - if ("li x" in line) and ("slli x" not in line): - CurrAdr += 8 if (xlen == 32) else 20 - elif ("la x" in line): - CurrAdr += 8 - else: - CurrAdr += 4 - -def expectValue(expectReg, expectVal, sigOffset): - global TestGroupSizes - TestGroupSizes[TestGroup-1] += 1 - addInst(" "+storecmd+" x"+str(expectReg)+", "+str(wordsize*sigOffset)+"(x"+str(StoreAdrReg)+")\n") - f.write(" RVTEST_IO_ASSERT_GPR_EQ(x"+str(StoreAdrReg+1)+", x"+str(expectReg)+", "+formatstr.format(expectVal)+")\n") - if (xlen == 32): - r.write(formatrefstr.format(expectVal)+"\n") - else: - r.write(formatrefstr.format(expectVal % 2**32)+"\n" + formatrefstr.format(expectVal >> 32)+"\n") - -def addJalr(rs,rd,dist): - target = CurrAdr + 20 + dist - target31_12 = CurrAdr >> 12 # 20 bits for lui - target11_0 = target - (target31_12 << 12) # 12 remaining bits - target31_16 = target31_12 >> 4 # lui sign extends, so shift in a leading 0 - target15_12 = target31_12 - (target31_16 << 4) # the nibble we just lost - if target11_0 > 0: - offset = randint(-(1<<11)-1,(1<<11)-2-target11_0) - else: - offset = randint(-(1<<11)-1-target11_0,(1<<11)-2) - addInst(" lui x"+str(rs)+", 0x"+imm20formatstr.format(target31_16)+"\n") - addInst(" addi x"+str(rs)+", x"+str(rs)+", SEXT_IMM(0x0"+imm12formatstr.format(target15_12 << 8)+")\n") - addInst(" slli x"+str(rs)+", x"+str(rs)+", SEXT_IMM(4)\n") - addInst(" addi x"+str(rs)+", x"+str(rs)+", SEXT_IMM(0x"+imm12formatstr.format(0xfff&(offset+target11_0+randint(0,1)))+")\n") - addInst(" JALR x"+str(rd)+", x"+str(rs)+", SEXT_IMM(0x"+imm12formatstr.format(0xfff&(-offset))+")\n") - -################################## -# test functions -################################## -def writeForwardsJumpVector(spacers,instr): - global TestNum - TestNum += 1 - rd, rs, DataReg, OtherRd = registerSelect() - # Header - f.write("\n") - f.write(" # Testcase "+str(TestNum)+"\n") - # Test Code - addInst(" li x"+str(DataReg)+", "+formatstr.format(expected)+"\n") - if (instr=="JAL"): - addInst(" JAL x"+str(rd)+", 1f\n") - elif (instr=="JALR"): - dist = spacers*(8 if (xlen == 32) else 20) # Compute distance from linked adr to target adr - addJalr(rs,rd,dist); - else: - exit("invalid instruction") - LinkAdr = CurrAdr if (rd!=0) else 0 # rd's expected value - for i in range(spacers): - addInst(" li x"+str(DataReg)+", "+formatstr.format(unexpected)+"\n") - f.write("1:\n") - # Store values to be verified - expectValue(rd, LinkAdr, 2*TestNum+0) - expectValue(DataReg, expected, 2*TestNum+1) - -def writeBackwardsJumpVector(spacers,instr): - global TestNum - TestNum += 1 - rd, rs, DataReg, OtherRd = registerSelect() - # Header - f.write("\n") - f.write(" # Testcase "+str(TestNum)+"\n") - # Test Code - addInst(" JAL x"+str(OtherRd)+", 2f\n") - f.write("1:\n") - addInst(" li x"+str(DataReg)+", "+formatstr.format(expected)+"\n") - addInst(" JAL x"+str(OtherRd)+", 3f\n") - f.write("2:\n") - for i in range(spacers): - addInst(" li x"+str(DataReg)+", "+formatstr.format(unexpected)+"\n") - if (instr=="JAL"): - addInst(" JAL x"+str(rd)+", 1b\n") - elif (instr=="JALR"): - dist = -20 - 4 - (1+spacers)*(8 if (xlen == 32) else 20) # Compute distance from linked adr to target adr - addJalr(rs,rd,dist); - else: - exit("invalid instruction") - LinkAdr = CurrAdr if (rd!=0) else 0 # rd's expected value - f.write("3:\n") - # Store values to be verified - expectValue(rd, LinkAdr, 2*TestNum+0) - expectValue(DataReg, expected, 2*TestNum+1) - -def writeChainVector(repetitions,spacers): - global TestNum - TestNum += 1 - rd, rs, DataReg,OtherRd = registerSelect() - # Header - f.write("\n") - f.write(" # Testcase "+str(TestNum)+"\n") - # Test Code - addInst(" li x"+str(DataReg)+", "+formatstr.format(expected)+"\n") - for i in range(repetitions): - addInst(" JAL x"+str(OtherRd)+", "+str(3*i+2)+"f\n") - if spacers: - for j in range(i): - addInst(" li x"+str(DataReg)+", "+formatstr.format(unexpected)+"\n") - f.write(str(3*i+1)+":\n") - addInst(" JAL x"+str(OtherRd)+", "+str(3*i+3)+"f\n") - if spacers: - for j in range(i): - addInst(" li x"+str(DataReg)+", "+formatstr.format(unexpected)+"\n") - f.write(str(3*i+2)+":\n") - addInst(" JAL x"+str(rd)+", "+str(3*i+1)+"b\n") - LinkAdr = CurrAdr if (rd!=0) else 0 # rd's expected value - if spacers: - for j in range(i): - addInst(" li x"+str(DataReg)+", "+formatstr.format(unexpected)+"\n") - f.write(str(3*i+3)+":\n") - # Store values to be verified - expectValue(rd, LinkAdr, 2*TestNum+0) - expectValue(DataReg, expected, 2*TestNum+1) - -################################## -# main body -################################## - -# change these to suite your tests -test = 0 -tests = ["JAL","JALR"] -author = "Ben Bracker (bbracker@hmc.edu)" -xlens = [32,64] -numtests = 100 - -# setup -seed(0) # make tests reproducible - -# generate files for each test -for test in tests: - for xlen in xlens: - print(test+" "+str(xlen)) - CurrAdr = int("80000108",16) - TestNum = -1 - TestGroup = 1 - TestGroupSizes = [0] - AllRegs = list(range(0,32)) - UnusedRegs = deepcopy(AllRegs) - StoreAdrReg = 6 # matches what's in header script - UnusedRegs.remove(6) - if (xlen==64): - expected = int("fedbca9876540000",16) - unexpected = int("ffff0000ffff0000",16) - else: - expected = int("fedbca98",16) - unexpected = int("ff00ff00",16) - - formatstrlen = str(int(xlen/4)) - formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number - formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x - imm20formatstr = "{:05x}" - imm12formatstr = "{:03x}" - - if (xlen == 32): - storecmd = "sw" - wordsize = 4 - else: - storecmd = "sd" - wordsize = 8 - - imperaspath = "../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "i/" - basename = "WALLY-" + test - fname = imperaspath + "src/" + basename + ".S" - refname = imperaspath + "references/" + basename + ".reference_output" - - # print custom header part - f = open(fname, "w") - r = open(refname, "w") - f.write("///////////////////////////////////////////\n") - f.write("// "+fname+ "\n") - f.write("//\n") - f.write("// This file can be used to test the RISC-V JAL(R) instruction.\n") - f.write("// But be warned that altering the test environment may break this test!\n") - f.write("// In order to work, this test expects that the first instruction (la)\n") - f.write("// be allocated at 0x80000100.\n") - f.write("//\n") - f.write("// " + author + "\n") - f.write("// Created "+str(datetime.now())+"\n") - - # insert generic header - h = open("testgen_header.S", "r") - for line in h: - f.write(line) - - # print directed test vectors - if test == "JAL": - for i in range(0,31): - writeForwardsJumpVector(randint(0,4),"JAL") - for i in range(0,31): - writeBackwardsJumpVector(randint(0,4),"JAL") - writeForwardsJumpVector(100,"JAL") - writeBackwardsJumpVector(100,"JAL") - writeChainVector(6,True) - writeChainVector(16,False) - elif test == "JALR": - for i in range(0,31): - writeForwardsJumpVector(randint(0,4),"JALR") - for i in range(0,31): - writeBackwardsJumpVector(randint(0,4),"JALR") - # can't make these latter two too long else 12 bit immediate overflows - # (would need to lui or slli rs to achieve longer ranges) - writeForwardsJumpVector(15,"JALR") - writeBackwardsJumpVector(15,"JALR") - - # print footer - h = open("testgen_footer.S", "r") - for line in h: - f.write(line) - - # Finish - f.write(".fill "+str(sum(TestGroupSizes))+", "+str(wordsize)+", -1\n") - f.write("\nRV_COMPLIANCE_DATA_END\n") - f.close() - r.close() diff --git a/studies/testgen/testgen-LOAD.py b/studies/testgen/testgen-LOAD.py deleted file mode 100755 index 736b8e05b..000000000 --- a/studies/testgen/testgen-LOAD.py +++ /dev/null @@ -1,227 +0,0 @@ -#!/usr/bin/env python3 -################################## -# testgen-LOAD.py -# -# Jarred Allen 02 February 2021 -# -# Generate directed and random test vectors for RISC-V Design Validation. -################################## - -################################## -# libraries -################################## -from datetime import datetime -from random import randint, seed, getrandbits - -################################## -# functions -################################## - -def rand_reg(): - """Produce a random register (skipping 6 and 31, since they're used for other things)""" - r = randint(1,29) - if r >= 6: - r += 1 - return r - -def rand_value(width): - """Generate a random value which fits in the given width""" - return randint(0, (1 << width) - 1) - -def rand_offset(): - """Generate a random offset""" - ret = rand_value(12) - # print("Random offset: %d" % ret) - return ret - -def rand_source(): - """Generate a random value for the source register, such that the load address is in the test data""" - ret = randint(1 << 12, (1 << 12) + (1 << 10)) - # print("Random source: %d" % ret) - return ret - -def add_offset_to_source(source, offset): - """Find the address from the given source value and offset""" - if offset & 0x800: - offset -= 0x1000 - return source + offset - -def insert_into_data(test_data, source, offset, value, width, xlen): - """Insert the given value into the given location of the test data""" - address = add_offset_to_source(source, offset) - # print("Test #%d" % testcase_num) - # print(f"Source: {source}, Offset: {offset}, Value: {value}, Width: {width}, xlen: {xlen}, Addr: {address}") - if address < 0: - return False - word_offset = address % (xlen // 8) - word_address = address - word_offset - if word_address in test_data: - return False - test_data[word_address] = value * (1 << (word_offset*8)) + ((~(((1 << width)-1) << (word_offset*8))) & rand_value(xlen)) - # print(f"Word: {hex(test_data[word_address])}") - return True - -def align(address, width): - """Align the address to the given width, in bits""" - return address - (address % (width // 8)) - -testcase_num = 0 -def generate_case(xlen, instruction, load_register, source_register, source_register_value, offset, expected): - """Produce the specified test case and return it as a pair of strings, where the first is the test case and the second is the output""" - global testcase_num - if xlen == 64: - store = "sd" - elif xlen == 32: - if instruction in ["lwu", "ld"]: - raise Exception("Instruction %s not supported in RV32I" % instruction) - store = "sw" - else: - raise Exception("Unknown xlen value: %s" % xlen) - if offset >= 0x800: - offset -= 0x1000 - if widths[instruction] != xlen: - expected = expected % (1 << widths[instruction]) - if 'u' not in instruction: - if expected & (1 << (widths[instruction] - 1)): - expected = (expected + ~((1 << widths[instruction]) - 1)) & ((1 << xlen) - 1) - data = f"""# Testcase {testcase_num}: source {offset}(x{source_register} == {source_register_value}), result: x{load_register} == {expected} - la x31, test_data - lui x{source_register}, {source_register_value // (1 << 12)} - addi x{source_register}, x{source_register}, {source_register_value % (1 << 12)} - add x{source_register}, x{source_register}, x31 - {instruction} x{load_register}, {offset}(x{source_register}) - {store} x{load_register}, {(testcase_num*xlen//8) % 0x800}(x6) - RVTEST_IO_ASSERT_GPR_EQ(x8, x{load_register}, {expected}) - - """ - testcase_num += 1 - if testcase_num*xlen//8 % 0x800 == 0: - data += "# Adjust x6 because we're storing too many things\naddi x6, x6, 1024\naddi x6, x6, 1024\n\n" - if xlen == 32: - reference_output = "{:08x}\n".format(expected) - elif xlen == 64: - reference_output = "{:08x}\n{:08x}\n".format(expected % (1 << 32), expected >> 32) - return (data, reference_output) - -def write_header(outfile): - outfile.write(f"""/////////////////////////////////////////// -// -// WALLY-LOAD -// -// Author: {author} -// -// Created {str(datetime.now())} -// -""") - outfile.write(open("testgen_header.S", "r").read()) - -def write_test_data(outfile, test_data, xlen): - # print("Begin writing test data:") - # print("{} entries, from address {} to {}".format(len(test_data), min(test_data.keys()), max(test_data.keys()))) - # print(test_data) - outfile.write(""" - .align 16 -test_data: - - """) - if xlen == 32: - data_word = ".word" - elif xlen == 64: - data_word = ".dword" - else: - raise Exception("Unknown xlen: %d" % xlen) - byte_width = xlen // 8 - for addr in [0] + sorted(test_data.keys()): - if addr in test_data: - word = f" {data_word} {hex(test_data[addr] % (1 << xlen))} # test_data+{hex(addr)}\n" - else: - word = "" - try: - fill_len = (min(k for k in test_data.keys() if k > addr) - addr) // byte_width - 1 - if word == "": - fill_len += 1 - fill = f" .fill {fill_len}, {byte_width}, 0x0\n" - except: - fill = "" - case = word+fill - outfile.write(case) - -################################## -# main body -################################## - -widths = { - "lb": 8, - "lbu": 8, - "lh": 16, - "lhu": 16, - "lw": 32, - "lwu": 32, - "ld": 64, -} -instructions = [i for i in widths] -author = "Jarred Allen" -xlens = [32, 64] -numrand = 100; - -# setup -seed(0) # make tests reproducible - -for xlen in xlens: - testcase_num = 0 - fname = "../../imperas-riscv-tests/riscv-test-suite/rv{}i/src/WALLY-LOAD.S".format(xlen) - refname = "../../imperas-riscv-tests/riscv-test-suite/rv{}i/references/WALLY-LOAD.reference_output".format(xlen) - f = open(fname, "w") - r = open(refname, "w") - write_header(f) - test_data = dict() - corner_values = [0x00, 0xFFFFFFFF, 0x7F, 0x7FFF, 0x7FFFFFFF] - if xlen == 64: - corner_values += [0xFFFFFFFFFFFFFFFF, 0x7FFFFFFFFFFFFFF] - corner_offsets = [0x800, 0x000, 0x7FF] - for instruction in instructions: - print("Running xlen: %d, instruction: %s" % (xlen, instruction)) - if xlen == 32: - if instruction in ["lwu", "ld"]: - continue - for value in corner_values + [rand_value(widths[instruction]) for _ in range(3)]: - value = value % (1 << widths[instruction]) - source_reg = rand_source() - for offset in corner_offsets + [rand_offset() for _ in range(3)]: - offset = align(offset, widths[instruction]) - source_reg = align(source_reg, widths[instruction]) - if insert_into_data(test_data, source_reg, offset, value, widths[instruction], xlen): - data, output = generate_case(xlen, instruction, rand_reg(), rand_reg(), source_reg, offset, value) - f.write(data) - r.write(output) - while testcase_num % 4: - source = rand_source() - offset = rand_offset() - value = rand_value(widths[instruction]) - if insert_into_data(test_data, source, offset, value, widths['lb'], xlen): - data, output = generate_case(xlen, 'lb', rand_reg(), rand_reg(), source, offset, value) - f.write(data) - r.write(output) - f.write("""# --------------------------------------------------------------------------------------------- - - RVTEST_IO_WRITE_STR(x31, "Test End\\n") - - # --------------------------------------------------------------------------------------------- - - RV_COMPLIANCE_HALT - -RV_COMPLIANCE_CODE_END - - .data - # Input data section -""") - write_test_data(f, test_data, xlen) - f.write("""# Output data section. -RV_COMPLIANCE_DATA_BEGIN - -test_1_res: -""") - f.write(f".fill {testcase_num}, {xlen//8}, -1\n") - f.write("\nRV_COMPLIANCE_DATA_END\n") - f.close() - r.close() diff --git a/studies/testgen/testgen-PIPELINE.py b/studies/testgen/testgen-PIPELINE.py deleted file mode 100755 index 0a2a66491..000000000 --- a/studies/testgen/testgen-PIPELINE.py +++ /dev/null @@ -1,1917 +0,0 @@ -#!/usr/bin/env python3 -################################################################################################### -# testgen-PIPELINE.py -# -# Shriya Nadgauda: snadgauda@hmc.edu & Ethan Falicov: efalicov@hmc.edu -# Created: Feb 2, 2021 -# -# Generate random assembly code for RISC-V Processor Design Validation. -################################################################################################### - -# Many Functions Based On: https://github.com/wallento/riscv-python-model (MIT License) - - -################################################################################################### -# Libraries -################################################################################################### -from random import seed -from random import randint -from enum import Enum -import numpy as np - -import re - -from datetime import datetime - -MEMSTART = 'testdata' -################################################################################################### -# Main Body -################################################################################################### - -class InvalidImmediateValueException(Exception): - pass - -class InvalidRegisterNumberException(Exception): - pass - -class InvalidRegisterValueException(Exception): - pass - -class WriteToImmutableRegisterException(Exception): - pass - -class ReadFromUninitializedMemoryException(Exception): - pass - -class InvalidMemoryWriteLocation(Exception): - pass - -def zeroExtend(inputBits, resultNumBits): - numDigitsToAppend = resultNumBits - len(inputBits) - newBits = inputBits - if numDigitsToAppend > 0: - newBits = ('0' * numDigitsToAppend) + inputBits - return newBits - -def oneExtend(inputBits, resultNumBits): - numDigitsToAppend = resultNumBits - len(inputBits) - newBits = inputBits - if numDigitsToAppend > 0: - newBits = ('1' * numDigitsToAppend) + inputBits - return newBits - -def signExtend(inputBits, resultNumBits): - if inputBits[0] == '1': - return oneExtend(inputBits = inputBits, resultNumBits = resultNumBits) - return zeroExtend(inputBits = inputBits, resultNumBits = resultNumBits) - -def binToDec(inputBits): - if inputBits[0] == '0': - return int(inputBits, 2) - - numBits = len(inputBits) - twoCompMask = (1 << (numBits - 1)) - 1 - msbMask = (1 << (numBits -1)) - - return int((-1 * (msbMask * int(inputBits[0], 2))) + (twoCompMask & int(inputBits, 2))) - -def randBinary(signed, numBits, valueAlignment): - # use this for corners: xlen = 32 here - # corners = [0, 1, 2, 0xFF, 0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1, - # 2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1] - # when not biased don't gen numbers from (|2^(n-2) to 2^(n-2)|) - biased = np.random.randint(0, 3) # on 2 generate random edge case - returnVal = 0 - sign = 0 - if biased < 2: - # print("unbiased") - if not(signed): - returnVal = np.random.randint(0, 2**(numBits - 2)) - - else: - returnVal = np.random.randint(-2**(numBits - 2), 2**(numBits - 2)) - - else: - # print("corner") - if not(signed): - returnVal = np.random.randint(2**(numBits - 2)+1, 2**(numBits - 1)-2) - - else: - sign = np.random.randint(0, 2) # 0 is pos, 1 is neg - if sign: - returnVal = np.random.randint(2**(numBits - 2)+1, 2**(numBits - 1)-2) - else: - returnVal = np.random.randint(-2**(numBits - 1), -2**(numBits - 2)-1) - - binReturnVal = bin(returnVal) #remove "0b" - if returnVal >= 0: - binReturnVal = binReturnVal[2:] - - #make binary correct length - while(len(binReturnVal) < numBits): - binReturnVal = "0" + binReturnVal - else: - binReturnVal = binReturnVal[3:] - #two's compliment - flipped = ''.join('1' if x == '0' else '0' for x in binReturnVal) - added = bin(int(flipped, 2) + 1)[2:] - - while(len(added) < len(flipped)): - added = "0" + added - while(len(added) < numBits): - added = "1" + added - - binReturnVal = added - - # ensure correct value assignment - if valueAlignment == 1: - return binReturnVal - - indexVal = valueAlignment // 2 - returnValue = binReturnVal[:-indexVal] + "0"*indexVal - return returnValue - -def randHex(sign, numBits, divisibleByValue): - val = hex(int(randBinary(sign, numBits*4, divisibleByValue), 2)) - return val - -def randDec(valueRangeMin, valueRangeMax, divisibleByValue): - valRange = (valueRangeMax - valueRangeMin)//divisibleByValue - return (np.random.randint(0, valRange + 1) * divisibleByValue + valueRangeMin) - -class Label: - def __init__(self, name, pcValue): - self.name = name - self.pcValue = pcValue - -class Immediate: - def __init__(self, xlen, numBits = None, signed = 1): - self.xlen = int(xlen) - if numBits == None: - numBits = self.xlen - self.numBits = int(numBits) - self.signed = signed - self.bits = '0'*self.numBits - self.twoCompMask = (1 << (self.numBits - 1)) - 1 - self.msbMask = (1 << (self.numBits -1)) - - self.value = self.getDecValue() - - self.maxValue = self.getMaxValue() - self.minValue = self.getMinValue() - - def getDecValue(self): - if self.signed == 1: - return self.getValueSigned() - return self.getValueUnsigned() - - def getMaxValue(self): - if self.signed == 1: - return ((2**(self.numBits - 1)) - 1) - return ((2**self.numBits) - 1) - - def getMinValue(self): - if self.signed == 1: - return (-1 * 2**(self.numBits - 1)) - return 0 - - def signExtend(self, inputBits = None): - if inputBits == None: - inputBits = self.bits - - return signExtend(inputBits, self.numBits) - - def oneExtend(self, inputBits = None): - if inputBits == None: - inputBits = self.bits - - return oneExtend(inputBits, self.numBits) - - def zeroExtend(self, inputBits = None): - if inputBits == None: - inputBits = self.bits - - return zeroExtend(inputBits, self.numBits) - - def setValue(self, newValue, signed = None): - if signed != None: - self.signed = signed - self.maxValue = self.getMaxValue() - self.minValue = self.getMinValue() - - if newValue > self.maxValue: - errStr = 'Attempted: {}, Max: {}'.format(newValue, self.maxValue) - raise InvalidImmediateValueException(errStr) - newValue = self.maxValue - - elif newValue < self.minValue: - errStr = 'Attempted: {}, Min: {}'.format(newValue, self.minValue) - raise InvalidImmediateValueException(errStr) - newValue = self.minValue - - self.value = newValue - - bitValue = '' - if (self.signed == 1) and (newValue < 0): - bitValue = bin(self.value)[3:] # Remove the -0b - flipped = ''.join('1' if x == '0' else '0' for x in bitValue) - bitValue = bin(int(flipped, 2) + 1)[2:] - - if len(bitValue) < len(flipped): # Correction for removing sig figs - bitValue = '0'*(len(flipped)-len(bitValue)) + bitValue - - bitValue = self.oneExtend(bitValue) - elif self.signed == 1 and newValue >= 0: - bitValue = bin(self.value)[2:] # Remove the 0b - bitValue = self.zeroExtend(bitValue) - else: - bitValue = bitValue = bin(self.value)[2:] # Remove the 0b - bitValue = self.zeroExtend(bitValue) - - self.bits = bitValue - - def setBits(self, newBits, signed = None): - if signed != None: - self.signed = signed - - if len(newBits) != self.numBits: - errStr = 'Attempted to write {} bits into {} bit immediate'.format(len(newBits), self.numBits) - raise InvalidImmediateValueException(errStr) - - self.bits = newBits - self.value = self.getDecValue() - - def randomize(self, signed = None, minVal = None, maxVal = None, granularity = None): - if signed != None: - self.signed = signed - self.maxValue = self.getMaxValue() - self.minValue = self.getMinValue() - - if minVal == None: - minVal = self.minValue - if maxVal == None: - maxVal = self.maxValue - if granularity == None: - granularity = GRANULARITY.BYTE - - granularityNum = 1 - if granularity == GRANULARITY.HALFWORD: - granularityNum = self.xlen // 16 - elif granularity == GRANULARITY.WORD: - granularityNum = self.xlen // 8 - - minVal = int(np.ceil(minVal / granularityNum) * granularityNum) - maxVal = int(np.floor(maxVal / granularityNum) * granularityNum) - - - valRange = (maxVal - minVal)//granularityNum - randValue = randint(0, valRange) * granularityNum + minVal - - self.setValue(randValue, signed=self.signed) - - def getValueSigned(self): - if self.bits[0] == '0': - return int(self.bits, 2) - else: - return int((-1 * (self.msbMask * int(self.bits[0], 2))) + (self.twoCompMask & int(self.bits, 2))) - - def getValueUnsigned(self): - return int(self.bits, 2) - - def __str__(self): - infoStr = '' - if self.signed == 1: - infoStr = 'Signed {} bit value: {}'.format(self.numBits, self.value) - infoStr = 'Unsigned {} bit value: {}'.format(self.numBits, self.value) - return 'Immediate bits {} ({})'.format(self.bits, infoStr) - - @classmethod - def randImm12(cls, xlen, signed = 1): - imm = cls(xlen = xlen, numBits = 12, signed = signed) - imm.randomize() - return imm - - @classmethod - def setImm12(cls, xlen, value, signed = 1): - imm = cls(xlen = xlen, numBits = 12, signed = signed) - imm.setValue(newValue = value) - return imm - - @classmethod - def setImm20(cls, xlen, value, signed = 1): - imm = cls(xlen = xlen, numBits = 20, signed = signed) - imm.setValue(newValue = value, signed=1) - return imm - - @classmethod - def randZImm5(cls, xlen, signed = 0): - imm = cls(xlen = xlen, numBits = 5, signed = signed) - imm.randomize() - return imm - - @classmethod - def randImm13(cls, xlen, signed = 1): - imm = cls(xlen = xlen, numBits = 13, signed = signed) - imm.randomize() - return imm - - @classmethod - def randImm20(cls, xlen, signed = 1): - imm = cls(xlen = xlen, numBits = 20, signed = signed) - imm.randomize() - return imm - -class Register: - def __init__(self, xlen, signed = 1): - self.xlen = int(xlen) - self.numBits = self.xlen - self.signed = signed - self.bits = '0'*self.numBits - self.twoCompMask = (1 << (self.numBits - 1)) - 1 - self.msbMask = (1 << (self.numBits -1)) - - self.value = self.getDecValue() - self.immutable = False - self.regName = None - - self.maxValue = self.getMaxValue() - self.minValue = self.getMinValue() - - def getRegName(self): - return self.regName - - def setRegName(self, newName): - self.regName = newName - - def setImmutable(self, immutable): - self.immutable = immutable - - def getDecValue(self): - if self.signed == 1: - return self.getValueSigned() - return self.getValueUnsigned() - - def getMaxValue(self): - if self.signed == 1: - return (2**(self.numBits - 1) - 1) - return (2**(self.numBits) - 1) - - def getMinValue(self): - if self.signed == 1: - return (-1 * 2**(self.numBits - 1)) - return 0 - - def signExtend(self, inputBits = None): - if inputBits == None: - inputBits = self.bits - - return signExtend(inputBits, self.numBits) - - def oneExtend(self, inputBits = None): - if inputBits == None: - inputBits = self.bits - - return oneExtend(inputBits, self.numBits) - - def zeroExtend(self, inputBits = None): - if inputBits == None: - inputBits = self.bits - - return zeroExtend(inputBits, self.numBits) - - def setValue(self, newValue, signed = None): - if self.immutable: - raise(WriteToImmutableRegisterException) - else: - if signed != None: - self.signed = signed - self.maxValue = self.getMaxValue() - self.minValue = self.getMinValue() - - if newValue > self.maxValue: - errStr = 'Attempted: {}, Max: {}'.format(newValue, self.maxValue) - raise InvalidRegisterValueException(errStr) - newValue = self.maxValue - - elif newValue < self.minValue: - errStr = 'Attempted: {}, Min: {}'.format(newValue, self.minValue) - raise InvalidRegisterValueException(errStr) - newValue = self.minValue - - self.value = newValue - - bitValue = '' - if signed == 1 and newValue < 0: - bitValue = bin(self.value)[3:] # Remove the -0b - flipped = ''.join('1' if x == '0' else '0' for x in bitValue) - bitValue = bin(int(flipped, 2) + 1)[2:] - - if len(bitValue) < len(flipped): # Correction for removing sig figs - bitValue = '0'*(len(flipped)-len(bitValue)) + bitValue - - bitValue = self.oneExtend(bitValue) - elif signed == 1 and newValue >= 0: - bitValue = bin(self.value)[2:] # Remove the 0b - bitValue = self.zeroExtend(bitValue) - else: - bitValue = bitValue = bin(self.value)[2:] # Remove the 0b - bitValue = self.zeroExtend(bitValue) - - self.bits = bitValue - - def setBits(self, newBits, signed = None): - if self.immutable: - raise(WriteToImmutableRegisterException) - else: - if signed != None: - self.signed = signed - - if len(newBits) != self.numBits: - errStr = 'Attempted to write {} bits into {} bit register'.format(len(newBits), self.numBits) - raise InvalidRegisterValueException(errStr) - - self.bits = newBits - self.value = self.getDecValue() - - def randomize(self, signed = None, minVal = None, maxVal = None, granularity = None): - if self.immutable: - raise(WriteToImmutableRegisterException) - else: - if signed != None: - self.signed = signed - self.maxValue = self.getMaxValue() - self.minValue = self.getMinValue() - - if minVal == None: - minVal = self.minValue - if maxVal == None: - maxVal = self.maxValue - if granularity == None: - granularity = GRANULARITY.BYTE - - granularityNum = 1 - if granularity == GRANULARITY.HALFWORD: - granularityNum = self.xlen // 16 - elif granularity == GRANULARITY.WORD: - granularityNum = self.xlen // 8 - - minVal = int(np.ceil(minVal / granularityNum) * granularityNum) - maxVal = int(np.floor(maxVal / granularityNum) * granularityNum) - - - valRange = (maxVal - minVal)//granularityNum - randValue = randint(0, valRange) * granularityNum + minVal - - self.setValue(randValue, signed=self.signed) - - def getValueSigned(self): - if self.bits[0] == 0: - return int(self.bits, 2) - else: - return int((-1 * (self.msbMask * int(self.bits[0], 2))) + (self.twoCompMask & int(self.bits, 2))) - - def getValueUnsigned(self): - return int(self.bits, 2) - - def __str__(self): - infoStr = '' - if self.signed == 1: - infoStr += 'Signed' - else: - infoStr += 'Unsigned' - - if self.immutable == True: - infoStr += ' Immutable' - - - return('Register {} bits: {} ({} value: {})'.format(self.regName, self.bits, infoStr, self.value)) - - def __add__(self, other): - self.setValue(self.value + int(other)) - return self - - @classmethod - def immutableRegister(cls, xlen, value, signed = 1): - reg = cls(xlen = xlen) - reg.setValue(newValue = value, signed = signed) - reg.setImmutable(immutable = True) - return reg - -class RegFile(): - def __init__(self, xlen, numRegs = 32, immutableRegsDict = {0 : 0}, prefix = 'x'): - self.xlen = xlen - self.numRegs = numRegs - self.regs = [] - self.immutableRegsList = [] - self.prefix = prefix - - for i in range(0, numRegs): - self.regs.append(Register(xlen)) - self.regs[-1].setRegName('{}{}'.format(prefix, i)) - - - for immutableRegKey, immutableRegVal in immutableRegsDict.items(): - self.regs[immutableRegKey].setValue(newValue = immutableRegVal, signed = 1) - self.immutableRegsList.append(immutableRegKey) - - def getRandReg(self): - reg = randint(1, len(self.regs)-1) - while(reg in self.immutableRegsList): - reg = randint(1, len(self.regs)-1) - return self.regs[reg] - - # def getRandMemReg(self): - # reg = randint(1, len(self.memoryreg)-1) - # while(reg in self.immutableRegsList): - # reg = randint(1, len(self.memoryreg)-1) - # return str(reg) - - def randomize(self): - for regNum in range(0, self.numRegs): - if regNum not in self.immutableRegsList: - self.regs[regNum].randomize() - - def setRegValue(self, regNum, newValue, signed = None): - if regNum in self.immutableRegsList: - errStr = 'Write to x{} not allowed'.format(regNum) - raise WriteToImmutableRegisterException(errStr) - if regNum > self.numRegs - 1: - errStr = 'Write to x{} exceeds number of registers: {}'.format(regNum, self.numRegs) - raise InvalidRegisterNumberException(errStr) - - - self.regs[regNum].setValue(newValue = newValue, signed = signed) - - def setRegBits(self, regNum, newBits, signed = None): - if regNum in self.immutableRegsList: - errStr = 'Write to x{} not allowed'.format(regNum) - raise WriteToImmutableRegisterException(errStr) - - if regNum > self.numRegs - 1: - errStr = 'Write to x{} exceeds number of registers: {}'.format(regNum, self.numRegs) - raise InvalidRegisterNumberException(errStr) - - self.regs[regNum].setBits(newBits = newBits, signed = signed) - - def __str__(self): - formattedString = '' - for x in range(0, len(self.regs)): - formattedString += 'x{}:\t{}\n'.format(str(x), str(self.regs[x])) - return formattedString - -class Memory(): - def __init__(self, xlen): - self.memDict = {} #keys: strings, values: binary strings - self.xlen = int(xlen) - self.minVal = 0 - self.maxVal = 2047 - def populateMemory(self, memDict): - # add all values of memDict to self.memDict - # overwrites any values that already exist - for key in memDict.keys(): - self.memDict[key] = memDict[key] - - def updateMemory(self, addr, granularity, value): - # sign extend value to 32 bits - if addr > self.maxVal: - errStr = 'Tried to write to invalid memory location {} max {}'.format(value, self.maxVal) - raise InvalidMemoryWriteLocation(errStr) - exValue = signExtend(value, self.xlen) - self.memDict[addr] = exValue - - def readMemory(self, addr, granularity): - # check if memory is unitilaized - if addr not in self.memDict.keys(): - errStr = 'Tried to read from uninitialized address: {}'.format(addr) - raise ReadFromUninitializedMemoryException(errStr) - - val = self.memDict[addr] - if granularity == GRANULARITY.WORD: - val = val - elif granularity == GRANULARITY.HALFWORD: - val = val[-(self.xlen//2):] - else: - val = val[-(self.xlen//4):] - if val == "": - return '0' - return val - - def genRandMemoryValue(self): - - #generate a random value - minVal = self.minVal - maxVal = self.maxVal - randValue = randint(0, self.maxVal + 1) - - # #convert to binary string - # bitValue = '' - # bitValue = bitValue = bin(randValue)[2:] # Remove the 0b - # bitValue = signExtend(bitValue, self.xlen) - - return randValue - -class Model(): - def __init__(self, xlen, numRegs, immutableRegsDict, initPc = 0): - self.xlen = int(xlen) - self.memory = Memory(xlen=self.xlen) - self.regFile = RegFile(xlen=self.xlen, immutableRegsDict = immutableRegsDict) - self.pc = Register(xlen=self.xlen, signed=0) - self.pc.setValue(newValue=initPc) - self.pc.setRegName(newName = 'PC') - self.memStart = 0x8000400 - self.memoryImmediateCounter = 0 - self.resultImmediateCounter = 0 - self.totalStoreCount = 0 - -class TestGen(): - def __init__(self, numInstr, immutableRegsDict, instrSet, imperasPath): - self.numInstr = numInstr - self.instrSet = instrSet - self.xlen = int((re.search(r'\d+', instrSet)).group()) - self.model = Model(xlen=self.xlen, numRegs=16, immutableRegsDict = immutableRegsDict) - - self.prevLabel = 0 - self.test_count = 0 - - self.imperasPath = imperasPath + instrSet.lower() + '/' - self.exportTestName = 'PIPELINE' - if (self.numInstr == 100000): - self.exportTestName += "-100K" - elif (self.numInstr == 1000000): - self.exportTestName += "-1M" - self.basename = 'WALLY-'+ self.exportTestName - self.fname = self.imperasPath + "src/" + self.basename + ".S" - self.refname = self.imperasPath + "references/" + self.basename + ".reference_output" - - def genTestInstr(self, reg): - imm = Immediate.setImm12(xlen = self.xlen, value = self.model.resultImmediateCounter) - reg6 = self.model.regFile.regs[6] - out = [Instr.issue(model = self.model, instrName = "sw", rs2 = reg, imm = imm, rs1 = reg6)] - self.model.resultImmediateCounter += 4 - if (self.model.resultImmediateCounter == 2040): - # Reset - imm2 = Immediate.setImm12(xlen = self.xlen, value = 2040) - reg6.setImmutable(False) - wreset = Instr.issue(model = self.model, instrName = "addi", rd = reg6, imm = imm2, rs1 = reg6) - reg6.setImmutable(True) - self.model.resultImmediateCounter = 0 - out.append(wreset) - out.append('\n') - self.model.totalStoreCount += 1 - return out - - def branchInstruction(self, instr): - # get field and granularity of instruction - - # randomly determine forward or back branch direction - fwd = np.random.randint(0, 2) #fwd on 1, bwd on 0 - taken = np.random.randint(0,2) #not taken on 0, taken on 1 - - # pick 2 registers for branch comparison - reg1 = self.model.regFile.getRandReg() - reg2 = reg1 - reg0 = self.model.regFile.regs[0] - while(reg2 == reg1): - reg2 = self.model.regFile.getRandReg() - - instructions = [] - - - if (fwd == 1): - # set r1 and r2 to what they should be to do the branching we want - if (instr == "beq" and taken==1) or (instr == "bne" and taken==0) or \ - (instr == "blt" and taken==0) or (instr == "bge" and taken==1) or \ - (instr == "bltu" and taken==0) or (instr == "bgeu" and taken==1): #r1 = r2 - newInstr = Instr.issue(model = self.model, instrName="add", rd = reg1, rs1 = reg2, rs2 = reg0) - instructions.append(newInstr) - - elif (instr == "beq" and taken==0) or (instr == "bne" and taken==1) or \ - (instr == "blt" and taken==1) or (instr == "bltu" and taken==1): #r2 = r1 + 1 - imm = Immediate.setImm12(xlen = self.xlen, value = 1) - newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1 = reg1, imm = imm) - instructions.append(newInstr) - - else: #r2 = r1 - 1 - imm = Immediate.setImm12(xlen = self.xlen, value = -1) - newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1 = reg1, imm = imm) - instructions.append(newInstr) - - # add branching instruction - label = Label(name = self.prevLabel, pcValue = self.model.pc.getValueUnsigned()) - branch = Instr.issue(model = self.model, instrName = instr, rs1 = reg2, rs2 = reg1, label = label, dir = 'f') - instructions.append(branch) - numInstr = np.random.randint(0, 6) - # add random alu instructions after branching before branch point - for i in range(0, numInstr): - curr = "RAND ALU INSTRUCTION" - rd = self.model.regFile.getRandReg() - r1 = self.model.regFile.getRandReg() - r2 = self.model.regFile.getRandReg() - instr = "add" - if (taken == 0): - instructions.append('add {}, {}, {}'.format(rd.getRegName(), r1.getRegName(), r2.getRegName())) - else: - instructions.append(Instr.issue(model = self.model, instrName = instr, rd = rd, rs1 = r1, rs2 = r2)) - - instructions.append(str(self.prevLabel) + ":") - self.prevLabel += 1 - return instructions - else: - if (not taken): - if instr == "beq": - randImm = np.random.randint(1, 10) - imm = Immediate.setImm12(xlen = self.xlen, value = randImm) - newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1 = reg1, imm = imm) - instructions.append(newInstr) - - elif instr == "bne": - imm = Immediate.setImm12(xlen = self.xlen, value = 0) - newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1 = reg1, imm = imm) - instructions.append(newInstr) - - elif instr == "bltu": - # deals with overflow - imm2 = Immediate.setImm12(xlen = self.xlen, value = 2) - newInstr = Instr.issue(model = self.model, instrName="srli", rd = reg1, rs1 = reg1, imm = imm2) - instructions.append(newInstr) - - randImm = np.random.randint(1, 11) - imm = Immediate.setImm12(xlen = self.xlen, value = randImm) - newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1 = reg1, imm = imm) - instructions.append(newInstr) - - elif instr == "blt": - # deals with overflow - imm2 = Immediate.setImm12(xlen = self.xlen, value = 2) - newInstr = Instr.issue(model = self.model, instrName="srli", rd = reg1, rs1 = reg1, imm = imm2) - instructions.append(newInstr) - - randImm = np.random.randint(1, 11) - imm = Immediate.setImm12(xlen = self.xlen, value = randImm) - newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1 = reg1, imm = imm) - instructions.append(newInstr) - - elif instr == "bgeu": - # deals with overflow - imm2 = Immediate.setImm12(xlen = self.xlen, value = 2) - newInstr = Instr.issue(model = self.model, instrName="srli", rd = reg1, rs1 = reg1, imm = imm2) - instructions.append(newInstr) - - imm2 = Immediate.setImm12(xlen = self.xlen, value = 15) - newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg1, rs1 = reg1, imm = imm2) - instructions.append(newInstr) - - randImm = np.random.randint(-10, 0) - imm = Immediate.setImm12(xlen = self.xlen, value = randImm) - newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1 = reg1, imm = imm) - instructions.append(newInstr) - - elif instr == "bge": - imm2 = Immediate.setImm12(xlen = self.xlen, value = 15) - newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg1, rs1 = reg1, imm = imm2) - instructions.append(newInstr) - - randImm = np.random.randint(-10, 0) - imm = Immediate.setImm12(xlen = self.xlen, value = randImm) - newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1 = reg1, imm = imm) - instructions.append(newInstr) - - label = Label(name = self.prevLabel, pcValue = self.model.pc.getValueUnsigned()) - instructions.append(str(self.prevLabel) + ":") - numInstr = np.random.randint(0, 6) - # add random alu instructions after branching before branch point - for i in range(0, numInstr): - curr = "RAND ALU INSTRUCTION" - rd = self.model.regFile.getRandReg() - while(rd == reg2 or rd == reg1): - rd = self.model.regFile.getRandReg() - r1 = self.model.regFile.getRandReg() - r2 = self.model.regFile.getRandReg() - instrJunk = "add" - instructions.append('add {}, {}, {}'.format(rd.getRegName(), r1.getRegName(), r2.getRegName())) - branch = Instr.issue(model = self.model, instrName = instr, rs1 = reg2, rs2 = reg1, label = label, dir = 'b') - instructions.append(branch) - else: - #setup reg instructions before any branching stuff - if instr == "beq": - numTimesRepeat = 1 #can only be repeated once with the way we are doing this - imm = Immediate.setImm12(xlen = self.xlen, value = numTimesRepeat) - newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1 = reg1, imm = imm) - instructions.append(newInstr) - - label = Label(name = self.prevLabel, pcValue = self.model.pc.getValueUnsigned()) - instructions.append(str(self.prevLabel) + ":") - - imm = Immediate.setImm12(xlen = self.xlen, value = -1) - newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1 = reg2, imm = imm) - instructions.append(newInstr) - - elif instr == "bne": - numTimesRepeat = np.random.randint(2, 6) - imm = Immediate.setImm12(xlen = self.xlen, value = numTimesRepeat) - newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1 = reg1, imm = imm) - instructions.append(newInstr) - - label = Label(name = self.prevLabel, pcValue = self.model.pc.getValueUnsigned()) - instructions.append(str(self.prevLabel) + ":") - - imm = Immediate.setImm12(xlen = self.xlen, value = -1) - newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1 = reg2, imm = imm) - instructions.append(newInstr) - - elif instr == "bltu": - numTimesRepeat = np.random.randint(2, 6)*(-1) - # deals with overflow - imm2 = Immediate.setImm12(xlen = self.xlen, value = 2) - newInstr = Instr.issue(model = self.model, instrName="srli", rd = reg1, rs1 = reg1, imm = imm2) - instructions.append(newInstr) - - imm = Immediate.setImm12(xlen = self.xlen, value = numTimesRepeat) - newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1 = reg1, imm = imm) - instructions.append(newInstr) - - label = Label(name = self.prevLabel, pcValue = self.model.pc.getValueUnsigned()) - instructions.append(str(self.prevLabel) + ":") - - imm = Immediate.setImm12(xlen = self.xlen, value = 1) - newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1 = reg2, imm = imm) - instructions.append(newInstr) - - elif instr == "blt": - # deals with overflow - imm2 = Immediate.setImm12(xlen = self.xlen, value = 2) - newInstr = Instr.issue(model = self.model, instrName="srli", rd = reg1, rs1 = reg1, imm = imm2) - instructions.append(newInstr) - - numTimesRepeat = np.random.randint(2, 6)*(-1) - imm = Immediate.setImm12(xlen = self.xlen, value = numTimesRepeat) - newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1 = reg1, imm = imm) - instructions.append(newInstr) - - label = Label(name = self.prevLabel, pcValue = self.model.pc.getValueUnsigned()) - instructions.append(str(self.prevLabel) + ":") - - imm = Immediate.setImm12(xlen = self.xlen, value = 1) - newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1 = reg2, imm = imm) - instructions.append(newInstr) - - elif instr == "bgeu": - numTimesRepeat = np.random.randint(2, 6) - imm = Immediate.setImm12(xlen = self.xlen, value = numTimesRepeat) - - # deals with overflow - imm1 = Immediate.setImm12(xlen = self.xlen, value = 2) - newInstr1 = Instr.issue(model = self.model, instrName="srli", rd = reg1, rs1 = reg1, imm = imm1) - instructions.append(newInstr1) - - imm2 = Immediate.setImm12(xlen = self.xlen, value = 15) - newInstr2 = Instr.issue(model = self.model, instrName="addi", rd = reg1, rs1 = reg1, imm = imm2) - instructions.append(newInstr2) - - newInstr3 = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1 = reg1, imm = imm) - instructions.append(newInstr3) - - label = Label(name = self.prevLabel, pcValue = self.model.pc.getValueUnsigned()) - instructions.append(str(self.prevLabel) + ":") - - imm = Immediate.setImm12(xlen = self.xlen, value = -1) - newInstr4 = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1 = reg2, imm = imm) - instructions.append(newInstr4) - - elif instr == "bge": - imm2 = Immediate.setImm12(xlen = self.xlen, value = 15) - newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg1, rs1 = reg1, imm = imm2) - instructions.append(newInstr) - - numTimesRepeat = np.random.randint(2, 6) - imm = Immediate.setImm12(xlen = self.xlen, value = numTimesRepeat) - newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1 = reg1, imm = imm) - instructions.append(newInstr) - - label = Label(name = self.prevLabel, pcValue = self.model.pc.getValueUnsigned()) - instructions.append(str(self.prevLabel) + ":") - - imm = Immediate.setImm12(xlen = self.xlen, value = -1) - newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1 = reg2, imm = imm) - instructions.append(newInstr) - - numInstr = np.random.randint(0, 5) - for i in range(0, numInstr): - curr = "RAND ALU INSTRUCTION" - rd = self.model.regFile.getRandReg() - while(rd == reg2) or (rd == reg1): - rd = self.model.regFile.getRandReg() - r1 = self.model.regFile.getRandReg() - r2 = self.model.regFile.getRandReg() - instrJunk = "add" - instructions.append(Instr.issue(model = self.model, instrName = instrJunk, rd = rd, rs1 = r1, rs2 = r2)) - - branch = Instr.issue(model = self.model, instrName = instr, rs1 = reg2, rs2 = reg1, label = label, dir = 'b') - instructions.append(branch) - self.prevLabel += 1 - return instructions - - - def getForwardingInstructions(self, instr): - ld_instr = instr - divBy = 1 - - granularity = None - if (instr == "lw"): - granularity = GRANULARITY.WORD - elif (instr == "lh") | (instr == 'lhu'): - divBy = self.xlen//2 - granularity = GRANULARITY.HALFWORD - else: - divBy = self.xlen//4 - granularity = GRANULARITY.BYTE - - instructions = [] - - rd = self.model.regFile.getRandReg() - reg1 = self.model.regFile.regs[7] - - memVal = self.model.memoryImmediateCounter - self.model.memoryImmediateCounter += 4 - if instr == "ld": - if ((memVal + reg1.getValueUnsigned()) % 8) != 0: - memVal -= 4 - self.model.memoryImmediateCounter -= 4 # we haven't read from a new location - - - - if (self.model.memoryImmediateCounter == 2040): - self.model.memoryImmediateCounter = 0 - immMem = Immediate.setImm12(xlen = self.model.xlen, value = 2040) - instructions.append(Instr.issue(model = self.model, instrName = "addi" , rd = reg1, rs1 = reg1, imm = immMem)) - - - imm1 = Immediate.setImm12(xlen = self.model.xlen, value = memVal) - - reg2 = self.model.regFile.getRandReg() - instructions.append(Instr.issue(model = self.model, instrName = "sw" , rs2 = reg2, rs1 = reg1, imm = imm1)) - - - while (rd == reg1): - rd = self.model.regFile.getRandReg() - instructions.append(Instr.issue(model = self.model, instrName = ld_instr, rd = rd, rs1 = reg1, imm = imm1)) - - return instructions - - def jumpInstruction(self, instr): - # fields, alignment = self.instrDict.instr[instr] - granularity = GRANULARITY.BYTE - divBy = 1 - - # randomly determine forward or back branch direction - fwd = np.random.randint(0, 2) #fwd on 1, bwd on 0 - taken = np.random.randint(0,2) #not taken on 0, taken on 1 - - reg_pc = self.model.regFile.getRandReg() - instructions = [] - - label1 = Label(name = 1, pcValue = self.model.pc.getValueUnsigned()) - label2 = Label(name = 2, pcValue = self.model.pc.getValueUnsigned()) - label3 = Label(name = 3, pcValue = self.model.pc.getValueUnsigned()) - - if fwd == 1: - newInstr = Instr.issue(model = self.model, instrName=instr, rd = reg_pc, label = label1, dir = "f") - instructions.append(newInstr) - - numInstr = np.random.randint(0, 6) - # add random alu instructions after jumping before jump point - reg_check = self.model.regFile.getRandReg() - for i in range(0, numInstr): - rd = self.model.regFile.getRandReg() - while (rd == reg_pc): - rd = self.model.regFile.getRandReg() - reg_check = rd - r1 = self.model.regFile.getRandReg() - r2 = self.model.regFile.getRandReg() - instructions.append(Instr.issue(model = self.model, instrName = "and", rd = rd, rs1 = r1, rs2 = r2)) - instructions.append("1:") - self.model.pc += 4 - - # #make sure jump was taken - check_instr = self.genTestInstr(reg_check) - for check in check_instr: - instructions.append(check) - - # #check value in pc + 4 reg - check_instr = self.genTestInstr(reg_pc) - for check in check_instr: - instructions.append(check) - else: - reg1 = self.model.regFile.getRandReg() - reg2 = self.model.regFile.getRandReg() - while reg2 == reg1: - reg2 = self.model.regFile.getRandReg() - - newInstr = Instr.issue(model = self.model, instrName=instr, rd = reg1, label = label1, dir = "f") - instructions.append(newInstr) - # instructions.append("jal x" + reg1 + ", 1f") - - instructions.append("2:") - self.model.pc += 4 - newInstr = Instr.issue(model = self.model, instrName=instr, rd = reg2, label = label3, dir = "f") - instructions.append(newInstr) - # instructions.append("jal x" + reg2 + ", 3f") - - instructions.append("1:") - self.model.pc += 4 - - numInstr = np.random.randint(0,6) - for i in range(0, numInstr): - rd = self.model.regFile.getRandReg() - r1 = self.model.regFile.getRandReg() - r2 = self.model.regFile.getRandReg() - instructions.append(Instr.issue(model = self.model, instrName = 'and', rd = rd, rs1 = r1, rs2 = r2)) - - #test case here - newInstr = Instr.issue(model = self.model, instrName=instr, rd = reg2, label = label2, dir = "b") - instructions.append(newInstr) - # instructions.append("jal x" + reg2 + ", 2b") - instructions.append("3:") - self.model.pc += 4 - - check_instr = self.genTestInstr(reg1) - for check in check_instr: - instructions.append(check) - - # jump to 1 - # #2 - # jump to 3 - # #1 - # junk here - # test: jump to 2 - # #3 - # check answer from 1 - return instructions - - - def jumpRInstruction(self, instr): - # fields, alignment = self.instrDict.instr[instr] - granularity = GRANULARITY.BYTE - divBy = 1 - - # randomly determine forward or back branch direction - fwd = np.random.randint(0, 2) #fwd on 1, bwd on 0 - - reg_pc = self.model.regFile.getRandReg() - instructions = [] - - label1 = Label(name = 1, pcValue = self.model.pc.getValueUnsigned()) - label2 = Label(name = 2, pcValue = self.model.pc.getValueUnsigned()) - label3 = Label(name = 3, pcValue = self.model.pc.getValueUnsigned()) - - if fwd == 1: - numInstr = np.random.randint(0, 6) - - rs1 = self.model.regFile.getRandReg() - while (rs1 == reg_pc): - rs1 = self.model.regFile.getRandReg() - - # TODO fix the value of rs1 - should be pc location of "1f" - rs1.setValue(newValue = 0) - - imm = Immediate.setImm12(xlen = self.model.xlen, value = 0) - - instructions.append('la {}, {}'.format(rs1.regName , "1f")) - self.model.pc += 8 - - newInstr = Instr.issue(model = self.model, instrName=instr, rd = reg_pc, rs1 = rs1, imm = imm) - instructions.append(newInstr) - - # add random alu instructions after jumping before jump point - reg_check = self.model.regFile.getRandReg() - for i in range(0, numInstr): - rd = self.model.regFile.getRandReg() - while (rd == reg_pc): - rd = self.model.regFile.getRandReg() - reg_check = rd - r1 = self.model.regFile.getRandReg() - r2 = self.model.regFile.getRandReg() - instructions.append(Instr.issue(model = self.model, instrName = "and", rd = rd, rs1 = r1, rs2 = r2)) - - instructions.append("1:") - self.model.pc += 4 - - #make sure jump was taken - check_instr = self.genTestInstr(reg_check) - for check in check_instr: - instructions.append(check) - - #check value in pc + 4 reg - check_instr = self.genTestInstr(reg_pc) - for check in check_instr: - instructions.append(check) - else: - reg1 = self.model.regFile.getRandReg() - reg2 = self.model.regFile.getRandReg() - while reg2 == reg1: - reg2 = self.model.regFile.getRandReg() - - jumpDestVal = self.model.pc.value + 4 - newInstr = Instr.issue(model = self.model, instrName='jal', rd = reg1, label = label1, dir = "f") - instructions.append(newInstr) - # instructions.append("jal x" + reg1 + ", 1f") - - instructions.append("2:") - self.model.pc += 4 - - newInstr = Instr.issue(model = self.model, instrName='jal', rd = reg2, label = label3, dir = "f") - instructions.append(newInstr) - # instructions.append("jal x" + reg2 + ", 3f") - - instructions.append("1:") - self.model.pc += 4 - - - rs1 = self.model.regFile.getRandReg() - while (rs1 == reg_pc): - rs1 = self.model.regFile.getRandReg() - - imm = Immediate.setImm12(xlen = self.model.xlen, value = 0) - - - instructions.append('la {}, {}'.format(rs1.regName ,"2b")) - self.model.pc += 8 - - - rs1.setValue(newValue = 0) #TODO: this value is wrong, should be address of label - imm = Immediate.setImm12(xlen = self.model.xlen, value = 0) - - - numInstr = np.random.randint(0,6) - for i in range(0, numInstr): - rd = self.model.regFile.getRandReg() - while(rd == rs1) or (rd == reg_pc): - rd = self.model.regFile.getRandReg() - r1 = self.model.regFile.getRandReg() - r2 = self.model.regFile.getRandReg() - instructions.append(Instr.issue(model = self.model, instrName = 'and', rd = rd, rs1 = r1, rs2 = r2)) - - #test case here - newInstr = Instr.issue(model = self.model, instrName=instr, rd = reg_pc, rs1 = rs1, imm = imm) - instructions.append(newInstr) - # instructions.append("jal x" + reg2 + ", 2b") - instructions.append("3:") - self.model.pc += 4 - - check_instr = self.genTestInstr(reg1) - for check in check_instr: - instructions.append(check) - - check_instr = self.genTestInstr(reg_pc) - for check in check_instr: - instructions.append(check) - - # jump to 1 - # #2 - # jump to 3 - # #1 - # junk instructions - # ... - # ... - # test instruction to 2 - # #3 - # check answer from 1 - return instructions - - def generateASM(self, instrSet, instrTypes): - generatedInstructions = [] - - # for memLocation in self.model.memory.memDict.keys(): - # memData = self.model.memory.readMemory(addr = memLocation, granularity = GRANULARITY.WORD) - # memDataVal = hex(int(memData, 2)) - # generatedInstructions.append('li x2, MASK_XLEN({})'.format(memDataVal)) - # self.model.pc += 8 - # generatedInstructions.append('li x3, MASK_XLEN({})'.format(memLocation)) - # self.model.pc += 8 - # generatedInstructions.append('sw x2, 0(x3)') - # self.model.pc += 4 - - generatedInstructions.append('la x7, test_data') - self.model.pc += 8 - - for reg in self.model.regFile.regs: - if (int(reg.regName[-1:]) not in self.model.regFile.immutableRegsList) : - immHex = randHex(False, 5, 1) - imm = int(immHex, 16) - reg.setValue(imm) - generatedInstructions.append('li {}, MASK_XLEN({})'.format(reg.getRegName(), immHex)) - self.model.pc += 8 - elif (reg == self.model.regFile.regs[0]): - immHex = 0 - imm = 0 - reg.setValue(imm) - generatedInstructions.append('li {}, MASK_XLEN({})'.format(reg.getRegName(), immHex)) - self.model.pc += 8 - elif (reg == self.model.regFile.regs[6]): - # immHex = 0 - # imm = 0 - # reg.setValue(imm) - # generatedInstructions.append('la {}, {}'.format(reg.getRegName(), "test_1_res")) - # self.model.pc += 8 - pass - for i in range(0, self.numInstr): - # decide which instruction to issue - randInstr = instrSet[randint(0, len(instrSet)-1)] - - randNum = randint(0, 2) - if randInstr in InstrTypes['B']: - newInstr = self.branchInstruction(instr = randInstr) - for i in newInstr: - generatedInstructions.append(i) - elif randInstr in InstrTypes['J']: - newInstr = self.jumpInstruction(instr = randInstr) - for i in newInstr: - generatedInstructions.append(i) - elif randInstr[0] == 'l' and randNum == 0 and randInstr != "lui": - newInstr = self.getForwardingInstructions(instr = randInstr) - for i in newInstr: - generatedInstructions.append(i) - else: - if randInstr in InstrTypes['R']: - rd = self.model.regFile.getRandReg() - rs1 = self.model.regFile.getRandReg() - rs2 = self.model.regFile.getRandReg() - instr = Instr.issue(model = self.model, instrName = randInstr, rd = rd, rs1 = rs1, rs2 = rs2) - generatedInstructions.append(instr) - - testInstrs = self.genTestInstr(rd) - for testInstr in testInstrs: - generatedInstructions.append(testInstr) - - elif randInstr in InstrTypes['I']: - if randInstr == "jalr": - newInstr = self.jumpRInstruction(instr = randInstr) - for i in newInstr: - generatedInstructions.append(i) - # memory instruction - elif randInstr[0] == 'l': - rs1 = self.model.regFile.regs[7] - - memLocation = list(self.model.memory.memDict.keys())[randint(0, len(self.model.memory.memDict.keys()) -1)] - if randInstr == "ld": - if ((memLocation + rs1.getValueUnsigned()) % 8) != 0: - if (memLocation != 0): - memLocation -=4 - else: - memLocation = 4 - - rd = self.model.regFile.getRandReg() - - imm12 = Immediate.setImm12(xlen = self.model.xlen, value = memLocation) - instr = Instr.issue(model = self.model, instrName = randInstr, rd = rd, rs1 = rs1, imm = imm12) - generatedInstructions.append(instr) - - testInstrs = self.genTestInstr(rd) - for testInstr in testInstrs: - generatedInstructions.append(testInstr) - else: - rd = self.model.regFile.getRandReg() - rs1 = self.model.regFile.getRandReg() - imm12 = Immediate.randImm12(xlen = self.model.xlen) - - instr = Instr.issue(model = self.model, instrName = randInstr, rd = rd, rs1 = rs1, imm = imm12) - generatedInstructions.append(instr) - - testInstrs = self.genTestInstr(rd) - for testInstr in testInstrs: - generatedInstructions.append(testInstr) - - elif randInstr in InstrTypes['S']: - rs1 = self.model.regFile.regs[7] - - immValue = self.model.memoryImmediateCounter - self.model.memoryImmediateCounter += 4 - if randInstr == 'Sd': - if ((immValue + rs1.getValueUnsigned()) % 8) != 0: - immValue -= 4 - self.model.memoryImmediateCounter -= 4 #haven't put a value in a new mem locatoin - - rs2 = self.model.regFile.getRandReg() - - - immMem = Immediate.setImm12(xlen = self.model.xlen, value = 2040) - if (self.model.memoryImmediateCounter == 2040): - self.model.memoryImmediateCounter = 0 - generatedInstructions.append(Instr.issue(model = self.model, instrName = "addi" , rd = rs1, rs1 = rs1, imm = immMem)) - - imm12 = Immediate.setImm12(xlen = self.model.xlen, value = immValue) - instr = Instr.issue(model = self.model, instrName = randInstr, rs1 = rs1, rs2 = rs2, imm = imm12) - generatedInstructions.append(instr) - - elif randInstr in InstrTypes['U']: - rd = self.model.regFile.getRandReg() - imm20 = Immediate.randImm20(xlen = self.model.xlen, signed = 0) - instr = Instr.issue(model = self.model, instrName = randInstr, rd = rd, imm = imm20) - generatedInstructions.append(instr) - - testInstrs = self.genTestInstr(rd) - for testInstr in testInstrs: - generatedInstructions.append(testInstr) - - elif randInstr in InstrTypes['R4']: - continue - else: - # INVALID INSTR - print(randInstr) - print("You made a typo") - return generatedInstructions - - def exportASM(self, instrSet, instrTypes): - asmFile = open(self.fname, 'w') - refFile = open(self.refname, 'w') - - # Custom Header - line = "///////////////////////////////////////////\n" - asmFile.write(line) - line ="// "+self.fname+ "\n// " + "Ethan Falicov & Shriya Nadgauda" + "\n" - asmFile.write(line) - line ="// Created " + str(datetime.now()) + "\n" + "\n" - asmFile.write(line) - line = "// Begin Tests" + "\n" - asmFile.write(line) - - # Generic Header - headerFile = open("testgen_header.S", "r") - for line in headerFile: - asmFile.write(line) - asmFile.write("\n") - - - # Write Instructions - generatedInstructions = self.generateASM(instrSet = INSTRSETS[instrSet], instrTypes = instrType) - for generatedInstr in generatedInstructions: - asmFile.write("\t" + generatedInstr + "\n") - if ("RVTEST_IO_ASSERT_GPR_EQ" in generatedInstr): - asmFile.write("\n") - - # Footer - footerFile = open("testgen_footer.S", "r") - lineNum = 0 - for line in footerFile: - asmFile.write(line) - if lineNum == 14: - asmFile.write('test_data:\n') - memList = list(self.model.memory.memDict.keys()) - memList.sort() - paddingSize = 0 - for memLoc in memList: - hexVal = int(self.model.memory.memDict[memLoc],2) - hexDigitSize = self.model.xlen / 4 - formattedStr = '0x{0:0{1}x}'.format(hexVal, hexDigitSize) - if self.model.xlen == 64: - asmFile.write('\t.dword {}\n'.format(formattedStr)) - else: - asmFile.write('\t.word {}\n'.format(formattedStr)) - lineNum += 1 - - asmFile.write("\n") - line = "\t.fill " + str(self.model.totalStoreCount) + ", " + str(self.xlen//8) + ", -1\n" - asmFile.write(line) - asmFile.write("\n") - - line = "\nRV_COMPLIANCE_DATA_END\n" - asmFile.write(line) - - asmFile.close() - refFile.close() - -class Instr(): - @classmethod - def issue(self, model, instrName, **kwargs): - funcName = 'Instr_' + str(instrName) - return getattr(Instr, funcName)(model = model, **kwargs) - - @classmethod - def Instr_label(self, model, label = None): - label.pcValue = model.pc.value - model.pc += 4 - return '{}:'.format(label.name) - - ############################################################################################### - # RV32I Instructions - ############################################################################################### - @classmethod - def Instr_lb(self, model, rd = None, rs1 = None, imm = None): - addr = imm.getDecValue() - rd.setBits(newBits = signExtend(model.memory.readMemory(addr = addr, granularity = GRANULARITY.BYTE), \ - resultNumBits = model.xlen)) - model.pc += 4 - return 'lb {}, {}({})'.format(rd.getRegName(), imm.getDecValue(), rs1.getRegName()) - - @classmethod - def Instr_lh(self, model, rd = None, rs1 = None, imm = None): - addr = imm.getDecValue() - rd.setBits(newBits = signExtend(model.memory.readMemory(addr = addr, granularity = GRANULARITY.HALFWORD), \ - resultNumBits = model.xlen)) - model.pc += 4 - return 'lh {}, {}({})'.format(rd.getRegName(), imm.getDecValue(), rs1.getRegName()) - - @classmethod - def Instr_lw(self, model, rd = None, rs1 = None, imm = None): - addr = imm.getDecValue() - rd.setBits(newBits = signExtend(model.memory.readMemory(addr = addr, granularity = GRANULARITY.WORD), \ - resultNumBits = model.xlen)) - model.pc += 4 - return 'lw {}, {}({})'.format(rd.getRegName(), imm.getDecValue(), rs1.getRegName()) - - @classmethod - def Instr_lbu(self, model, rd = None, rs1 = None, imm = None): - addr = imm.getDecValue() - rd.setBits(newBits = zeroExtend(model.memory.readMemory(addr = addr, granularity = GRANULARITY.BYTE), \ - resultNumBits = model.xlen)) - model.pc += 4 - return 'lbu {}, {}({})'.format(rd.getRegName(), imm.getDecValue(), rs1.getRegName()) - - @classmethod - def Instr_lhu(self, model, rd = None, rs1 = None, imm = None): - addr = imm.getDecValue() - rd.setBits(newBits = zeroExtend(model.memory.readMemory(addr = addr, granularity = GRANULARITY.HALFWORD), \ - resultNumBits = model.xlen)) - model.pc += 4 - return 'lhu {}, {}({})'.format(rd.getRegName(), imm.getDecValue(), rs1.getRegName()) - - @classmethod - def Instr_addi(self, model, rd = None, rs1 = None, imm = None): - newValue = rs1.getDecValue() + imm.getDecValue() - newValueBin = 0 - if newValue > 0: - newValueBin = bin(newValue)[2:] - elif newValue == 0: - newValueBin = "0" * model.xlen - else: - newValueBin = bin(newValue)[3:] - newValueBinTrunk = newValueBin[-model.xlen:] - rd.setBits(newBits = signExtend(inputBits = newValueBinTrunk, resultNumBits = model.xlen), signed = 1) - model.pc += 4 - return 'addi {}, {}, MASK_XLEN({})'.format(rd.getRegName(), rs1.getRegName(), imm.getDecValue()) - - @classmethod - def Instr_slli(self, model, rd = None, rs1 = None, imm = None): - bits = rs1.bits - immBits = imm.bits[-5:] - immShift = int(immBits, 2) - shifted = bits[-(len(bits) - immShift):] - shiftedExt = binToDec(inputBits = shifted + '0'*(model.xlen - len(shifted))) - rd.setValue(newValue = shiftedExt, signed = 1) - model.pc += 4 - return 'slli {}, {}, 0b{}'.format(rd.getRegName(), rs1.getRegName(), immBits) - - @classmethod - def Instr_slti(self, model, rd = None, rs1 = None, imm = None): - if (rs1.getValueSigned() < imm.getValueSigned()): - rd.setValue(newValue = 1, signed = 1) - else: - rd.setValue(newValue = 0, signed = 1) - model.pc += 4 - return 'slti {}, {}, SEXT_IMM({})'.format(rd.getRegName(), rs1.getRegName(), imm.getDecValue()) - - @classmethod - def Instr_sltiu(self, model, rd = None, rs1 = None, imm = None): - if (rs1.getValueUnsigned() < imm.getValueUnsigned()): - rd.setValue(newValue = 1, signed = 1) - else: - rd.setValue(newValue = 0, signed = 1) - model.pc += 4 - return 'slti {}, {}, SEXT_IMM({})'.format(rd.getRegName(),rs1.getRegName(), imm.getDecValue()) - - @classmethod - def Instr_xori(self, model, rd = None, rs1 = None, imm = None): - newValue = rs1.getDecValue() ^ imm.getDecValue() - rd.setValue(newValue = newValue, signed = rs1.signed) - model.pc += 4 - return 'xori {}, {}, SEXT_IMM({})'.format(rd.getRegName(), rs1.getRegName(), imm.getDecValue()) - - @classmethod - def Instr_srli(self, model, rd = None, rs1 = None, imm = None): - bits = rs1.bits - immBits = imm.bits[-5:] - immShift = int(immBits, 2) - shifted = bits[0:len(bits) - immShift] - extShifted = zeroExtend(inputBits = shifted, resultNumBits = model.xlen) - rd.setBits(newBits = extShifted, signed = 1) - model.pc += 4 - return 'srli {}, {}, 0b{}'.format(rd.getRegName(), rs1.getRegName(), immBits) - - @classmethod - def Instr_srai(self, model, rd = None, rs1 = None, imm = None): - bits = rs1.bits - immBits = imm.bits[-5:] - immShift = int(immBits, 2) - shifted = bits[0:len(bits) - immShift] - extShifted = signExtend(inputBits = shifted, resultNumBits = model.xlen) - rd.setBits(newBits = extShifted, signed = 1) - model.pc += 4 - return 'srai {}, {}, 0b{}'.format(rd.getRegName(), rs1.getRegName(), immBits) - - @classmethod - def Instr_ori(self, model, rd = None, rs1 = None, imm = None): - rd.setValue(newValue = (rs1.getDecValue() | imm.getDecValue()), signed = rs1.signed) - return 'ori {}, {}, SEXT_IMM({})'.format(rd.getRegName(), rs1.getRegName(), imm.getDecValue()) - - @classmethod - def Instr_andi(self, model, rd = None, rs1 = None, imm = None): - rd.setValue(newValue = (rs1.getDecValue() & imm.getDecValue()), signed = rs1.signed) - return 'andi {}, {}, SEXT_IMM({})'.format(rd.getRegName(), rs1.getRegName(), imm.getDecValue()) - - @classmethod - def Instr_auipc(self, model, rd = None, imm = None): - rd.setValue(newValue = binToDec(inputBits = imm.bits[:-12] + '0'*12) + model.pc.getDecValue(), signed = 1) - return 'auipc {}, MASK_XLEN({})'.format(rd.getRegName(), imm.getDecValue()) - - @classmethod - def Instr_sb(self, model, rs1 = None, rs2 = None, imm = None): - addr = imm.getDecValue() - if addr in model.memory.memDict.keys(): - originalMem = model.memory.readMemory(addr = addr, granularity = GRANULARITY.WORD) - model.memory.updateMemory(addr = addr, value = originalMem[:-8] + rs2.bits[-8:], granularity = GRANULARITY.WORD) - else: - model.memory.updateMemory(addr = addr, value = '0'*(model.xlen - 8) + rs2.bits[-8:], granularity = GRANULARITY.WORD) - model.pc += 4 - return 'sb {}, {}({})'.format(rs2.getRegName(), imm.getDecValue(), rs1.getRegName()) - - @classmethod - def Instr_sh(self, model, rs1 = None, rs2 = None, imm = None): - addr = imm.getDecValue() - if addr in model.memory.memDict.keys(): - originalMem = model.memory.readMemory(addr = addr, granularity = GRANULARITY.WORD) - model.memory.updateMemory(addr = addr, value = originalMem[:-16] + rs2.bits[-16:], granularity = GRANULARITY.WORD) - else: - model.memory.updateMemory(addr = addr, value = '0'*(model.xlen - 16) + rs2.bits[-16:], granularity = GRANULARITY.WORD) - model.pc += 4 - return 'sh {}, {}({})'.format(rs2.getRegName(), imm.getDecValue(), rs1.getRegName()) - - @classmethod - def Instr_sw(self, model, rs1 = None, rs2 = None, imm = None): - addr = imm.getDecValue() - model.memory.updateMemory(addr = addr, value = rs2.bits, granularity = GRANULARITY.WORD) - model.pc += 4 - return 'sw {}, {}({})'.format(rs2.getRegName(), imm.getDecValue(), rs1.getRegName()) - - @classmethod - def Instr_add(self, model, rd = None, rs1 = None, rs2 = None): - newValue = rs1.getDecValue() + rs2.getDecValue() - newValueBin = 0 - if newValue > 0: - newValueBin = bin(newValue)[2:] - elif newValue == 0: - newValueBin = "0" * model.xlen - else: - newValueBin = bin(newValue)[3:] - newValueBinTrunk = newValueBin[-model.xlen:] - rd.setBits(newBits = signExtend(inputBits = newValueBinTrunk, resultNumBits = model.xlen), signed = 1) - model.pc += 4 - return 'add {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName()) - - @classmethod - def Instr_sub(self, model, rd = None, rs1 = None, rs2 = None): - newValue = rs1.getDecValue() - rs2.getDecValue() - newValueBin = 0 - if newValue > 0: - newValueBin = bin(newValue)[2:] - elif newValue == 0: - newValueBin = "0" * model.xlen - else: - newValueBin = bin(newValue)[3:] - newValueBinTrunk = newValueBin[-model.xlen:] - rd.setBits(newBits = signExtend(inputBits = newValueBinTrunk, resultNumBits = model.xlen), signed = 1) - model.pc += 4 - return 'sub {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName()) - - @classmethod - def Instr_sll(self, model, rd = None, rs1 = None, rs2 = None): - bits = rs1.bits - rs2Bin = rs2.bits[-5:] - rs2Shift = int(rs2Bin,2) - shifted = bits[-(len(bits) - rs2Shift):] - shiftedExt = binToDec(inputBits = shifted + '0'*(model.xlen - len(shifted))) - rd.setValue(newValue = shiftedExt, signed = 1) - model.pc += 4 - return 'sll {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName()) - - @classmethod - def Instr_slt(self, model, rd = None, rs1 = None, rs2 = None): - if (rs1.getDecValue() < rs2.getDecValue()): - rd.setValue(newValue = 1, signed = 1) - else: - rd.setValue(newValue = 0, signed = 1) - model.pc += 4 - return 'slt {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName()) - - - @classmethod - def Instr_sltu(self, model, rd = None, rs1 = None, rs2 = None): - if (rs1.getValueUnsigned() < rs2.getValueUnsigned()): - rd.setValue(newValue = 1, signed = 1) - else: - rd.setValue(newValue = 0, signed = 1) - model.pc += 4 - return 'sltu {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName()) - - @classmethod - def Instr_xor(self, model, rd = None, rs1 = None, rs2 = None): - rd.setValue(newValue = (rs1.getDecValue() ^ rs2.getDecValue()), signed = rs1.signed) - model.pc += 4 - return 'xor {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName()) - - @classmethod - def Instr_srl(self, model, rd = None, rs1 = None, rs2 = None): - bits = rs1.bits - rs2Bin = rs2.bits[-5:] - rs2Shift = int(rs2Bin,2) - shifted = bits[0:len(bits) - rs2Shift] - extShifted = zeroExtend(inputBits = shifted, resultNumBits = model.xlen) - rd.setBits(newBits = extShifted, signed = 1) - model.pc += 4 - return 'srl {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName()) - - @classmethod - def Instr_sra(self, model, rd = None, rs1 = None, rs2 = None): - bits = rs1.bits - rs2Bin = rs2.bits[-5:] - rs2Shift = int(rs2Bin,2) - shifted = bits[0:len(bits) - rs2Shift] - extShifted = signExtend(inputBits = shifted, resultNumBits = model.xlen) - rd.setBits(newBits = extShifted, signed = 1) - model.pc += 4 - return 'sra {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName()) - - @classmethod - def Instr_or(self, model, rd = None, rs1 = None, rs2 = None): - rd.setValue(newValue = (rs1.getDecValue() | rs2.getDecValue()), signed = rs1.signed) - model.pc += 4 - return 'or {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName()) - - @classmethod - def Instr_and(self, model, rd = None, rs1 = None, rs2 = None): - rd.setValue(newValue = (rs1.getDecValue() & rs2.getDecValue()), signed = rs1.signed) - model.pc += 4 - return 'and {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName()) - - @classmethod - def Instr_lui(self, model, rd = None, imm = None): - rd.setValue(newValue = binToDec(inputBits = imm.bits[:20] + '0'*(model.xlen-20)) , signed = 1) - model.pc += 4 - return 'lui {}, {}'.format(rd.getRegName(), imm.getDecValue()) - - - @classmethod - def Instr_beq(self, model, rs1 = None, rs2 = None, label = None, dir = None): - if (rs1.getValueSigned() == rs2.getValueSigned()): - model.pc.setValue(label.pcValue) - else: - model.pc += 4 - return 'beq {}, {}, {}{}'.format(rs1.getRegName(), rs2.getRegName(), label.name, dir) - - @classmethod - def Instr_bne(self, model, rs1 = None, rs2 = None, label = None, dir = None): - if (rs1.getValueSigned() != rs2.getValueSigned()): - model.pc.setValue(label.pcValue) - else: - model.pc += 4 - return 'bne {}, {}, {}{}'.format(rs1.getRegName(), rs2.getRegName(), label.name, dir) - - @classmethod - def Instr_blt(self, model, rs1 = None, rs2 = None, label = None, dir = None): - if (rs1.getValueSigned() < rs2.getValueSigned()): - model.pc.setValue(label.pcValue) - else: - model.pc += 4 - return 'blt {}, {}, {}{}'.format(rs1.getRegName(), rs2.getRegName(), label.name, dir) - - @classmethod - def Instr_bge(self, model, rs1 = None, rs2 = None, label = None, dir = None): - if (rs1.getValueSigned() >= rs2.getValueSigned()): - model.pc.setValue(label.pcValue) - else: - model.pc += 4 - return 'bge {}, {}, {}{}'.format(rs1.getRegName(), rs2.getRegName(), label.name, dir) - - @classmethod - def Instr_bltu(self, model, rs1 = None, rs2 = None, label = None, dir = None): - if (rs1.getValueUnsigned() < rs2.getValueUnsigned()): - model.pc.setValue(label.pcValue) - else: - model.pc += 4 - return 'bltu {}, {}, {}{}'.format(rs1.getRegName(), rs2.getRegName(), label.name, dir) - - @classmethod - def Instr_bgeu(self, model, rs1 = None, rs2 = None, label = None, dir = None): - if (rs1.getValueUnsigned() >= rs2.getValueUnsigned()): - model.pc.setValue(label.pcValue) - else: - model.pc += 4 - return 'bgeu {}, {}, {}{}'.format(rs1.getRegName(), rs2.getRegName(), label.name, dir) - - @classmethod - def Instr_jalr(self, model, rd = None, rs1 = None, imm = None): - rd.setValue(newValue = model.pc.getDecValue() + 4, signed = 1) - model.pc.setValue(rs1.getDecValue() + imm.getDecValue()) - return 'jalr {}, {}, MASK_XLEN({})'.format(rd.getRegName(), rs1.getRegName(), imm.getDecValue()) - - @classmethod - def Instr_jal(self, model, rd = None, label = None, dir = None): - rd.setValue(newValue = model.pc.getDecValue() + 4, signed = 1) - model.pc.setValue(label.pcValue) - return 'jal {}, {}{}'.format(rd.getRegName(), label.name, dir) - - - - - ################################################################################################### - # RV 64I - ################################################################################################### - #TODO These may not keep the internal model consistent. You have been warned...sorry lol - - @classmethod - def Instr_ld(self, model, rd = None, rs1 = None, imm = None): - addr = imm.getDecValue() - rd.setBits(newBits = signExtend(model.memory.readMemory(addr = addr, granularity = GRANULARITY.WORD), \ - resultNumBits = model.xlen)) - model.pc += 4 - return 'ld {}, {}({})'.format(rd.getRegName(), imm.getDecValue(), rs1.getRegName()) - - @classmethod - def Instr_lwu(self, model, rd = None, rs1 = None, imm = None): - addr = imm.getDecValue() - rd.setBits(newBits = zeroExtend(model.memory.readMemory(addr = addr, granularity = GRANULARITY.BYTE), \ - resultNumBits = model.xlen)) - model.pc += 4 - return 'lwu {}, {}({})'.format(rd.getRegName(), imm.getDecValue(), rs1.getRegName()) - - @classmethod - def Instr_addiw(self, model, rd = None, rs1 = None, imm = None): - newValue = rs1.getDecValue() + imm.getDecValue() - newValueBin = 0 - if newValue > 0: - newValueBin = bin(newValue)[2:] - elif newValue == 0: - newValueBin = "0" * model.xlen - else: - newValueBin = bin(newValue)[3:] - newValueBinTrunk = newValueBin[-model.xlen:] - rd.setBits(newBits = signExtend(inputBits = newValueBinTrunk, resultNumBits = model.xlen), signed = 1) - model.pc += 4 - return 'addiw {}, {}, MASK_XLEN({})'.format(rd.getRegName(), rs1.getRegName(), imm.getDecValue()) - - @classmethod - def Instr_slliw(self, model, rd = None, rs1 = None, imm = None): - bits = rs1.bits - immBits = imm.bits[-5:] - immShift = int(immBits, 2) - shifted = bits[-(len(bits) - immShift):] - shiftedExt = binToDec(inputBits = shifted + '0'*(model.xlen - len(shifted))) - rd.setValue(newValue = shiftedExt, signed = 1) - model.pc += 4 - return 'slliw {}, {}, 0b{}'.format(rd.getRegName(), rs1.getRegName(), immBits) - - @classmethod - def Instr_srliw(self, model, rd = None, rs1 = None, imm = None): - bits = rs1.bits - immBits = imm.bits[-5:] - immShift = int(immBits, 2) - shifted = bits[0:len(bits) - immShift] - extShifted = zeroExtend(inputBits = shifted, resultNumBits = model.xlen) - rd.setBits(newBits = extShifted, signed = 1) - model.pc += 4 - return 'srliw {}, {}, 0b{}'.format(rd.getRegName(), rs1.getRegName(), immBits) - - @classmethod - def Instr_sraiw(self, model, rd = None, rs1 = None, imm = None): - bits = rs1.bits - immBits = imm.bits[-5:] - immShift = int(immBits, 2) - shifted = bits[0:len(bits) - immShift] - extShifted = signExtend(inputBits = shifted, resultNumBits = model.xlen) - rd.setBits(newBits = extShifted, signed = 1) - model.pc += 4 - return 'sraiw {}, {}, 0b{}'.format(rd.getRegName(), rs1.getRegName(), immBits) - - @classmethod - def Instr_Sd(self, model, rs1 = None, rs2 = None, imm = None): - addr = imm.getDecValue() - model.memory.updateMemory(addr = addr, value = rs2.bits, granularity = GRANULARITY.WORD) - model.pc += 4 - return 'Sd {}, {}({})'.format(rs2.getRegName(), imm.getDecValue(), rs1.getRegName()) - - @classmethod - def Instr_addw(self, model, rd = None, rs1 = None, rs2 = None): - newValue = rs1.getDecValue() + rs2.getDecValue() - newValueBin = 0 - if newValue > 0: - newValueBin = bin(newValue)[2:] - elif newValue == 0: - newValueBin = "0" * model.xlen - else: - newValueBin = bin(newValue)[3:] - newValueBinTrunk = newValueBin[-model.xlen:] - rd.setBits(newBits = signExtend(inputBits = newValueBinTrunk, resultNumBits = model.xlen), signed = 1) - model.pc += 4 - return 'addw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName()) - - @classmethod - def Instr_subw(self, model, rd = None, rs1 = None, rs2 = None): - newValue = rs1.getDecValue() - rs2.getDecValue() - newValueBin = 0 - if newValue > 0: - newValueBin = bin(newValue)[2:] - elif newValue == 0: - newValueBin = "0" * model.xlen - else: - newValueBin = bin(newValue)[3:] - newValueBinTrunk = newValueBin[-model.xlen:] - rd.setBits(newBits = signExtend(inputBits = newValueBinTrunk, resultNumBits = model.xlen), signed = 1) - model.pc += 4 - return 'subw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName()) - - @classmethod - def Instr_sllw(self, model, rd = None, rs1 = None, rs2 = None): - bits = rs1.bits - rs2Bin = rs2.bits[-5:] - rs2Shift = int(rs2Bin,2) - shifted = bits[-(len(bits) - rs2Shift):] - shiftedExt = binToDec(inputBits = shifted + '0'*(model.xlen - len(shifted))) - rd.setValue(newValue = shiftedExt, signed = 1) - model.pc += 4 - return 'sllw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName()) - - @classmethod - def Instr_srlw(self, model, rd = None, rs1 = None, rs2 = None): - bits = rs1.bits - rs2Bin = rs2.bits[-5:] - rs2Shift = int(rs2Bin,2) - shifted = bits[0:len(bits) - rs2Shift] - extShifted = zeroExtend(inputBits = shifted, resultNumBits = model.xlen) - rd.setBits(newBits = extShifted, signed = 1) - model.pc += 4 - return 'srlw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName()) - - @classmethod - def Instr_sraw(self, model, rd = None, rs1 = None, rs2 = None): - bits = rs1.bits - rs2Bin = rs2.bits[-5:] - rs2Shift = int(rs2Bin,2) - shifted = bits[0:len(bits) - rs2Shift] - extShifted = signExtend(inputBits = shifted, resultNumBits = model.xlen) - rd.setBits(newBits = extShifted, signed = 1) - model.pc += 4 - return 'sraw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName()) - - -################################################################################################### -# Global Constants -################################################################################################### -GRANULARITY = Enum('granularity', ['WORD', 'HALFWORD', 'BYTE']) -# 'jalr', -INSTRSETS = {'RV32I': ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti', 'sltiu', 'xori', \ - 'srli', 'srai', 'ori', 'andi', 'auipc', 'sb', 'sh', 'sw', 'add', 'sub', \ - 'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and', 'lui', 'beq', \ - 'bne', 'blt', 'bge', 'bltu', 'bgeu', 'jal', 'jalr'], \ - 'RV64I': ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti', 'sltiu', 'xori', \ - 'srli', 'srai', 'ori', 'andi', 'auipc', 'sb', 'sh', 'sw', 'add', 'sub', \ - 'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and', 'lui', 'beq', \ - 'bne', 'blt', 'bge', 'bltu', 'bgeu', 'jalr', 'jal', \ - 'ld', 'lwu', 'addiw', 'slliw', 'srliw', 'sraiw', 'Sd', 'addw', 'subw', \ - 'sllw', 'srlw', 'sraw'] \ - } - - -InstrTypes = { 'R' : ['add', 'sub', 'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and', \ - 'addw', 'subw', 'sllw', 'srlw', 'sraw'], \ - 'I' : ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti', 'sltiu', 'xori', 'srli', 'srai', 'ori', 'andi', 'jalr', \ - 'ld', 'lwu', 'addiw', 'slliw', 'srliw', 'sraiw'], \ - 'S' : ['sw', 'sh', 'sb', 'Sd'], \ - 'B' : ['beq', 'bne', 'blt', 'bge', 'bltu', 'bgeu'], \ - 'U' : ['lui', 'auipc'], \ - 'J' : ['jal'], \ - 'R4': []} -################################################################################################### -# Main Body -################################################################################################### - -XLEN = ['32', '64'] -INSTRUCTION_TYPE = ['I'] -NUMINSTR = [100000, 1000000] -IMPERASPATH = "../../imperas-riscv-tests/riscv-test-suite/" - -seed(42) -np.random.seed(42) -for num_instructions in NUMINSTR: - for xlen in XLEN: - memInit = {} - for i in range(0, 400, 4): - val = randBinary(signed = 0, numBits = int(xlen), valueAlignment = 1) - memInit[i] = val - for instrType in INSTRUCTION_TYPE: - instrSet = 'RV' + xlen + instrType - - print('Generating {} Assembly Instructions for {}'.format(num_instructions, instrSet)) - - dut = TestGen(numInstr=num_instructions, immutableRegsDict = {0 : 0, 6 : 0, 7 : 0}, instrSet=instrSet, imperasPath=IMPERASPATH) - # regFile = - dut.model.memory.populateMemory(memDict = memInit) - dut.exportASM(instrSet = instrSet, instrTypes = instrType) \ No newline at end of file diff --git a/studies/testgen/testgen-SLL-SRL-SRA.py b/studies/testgen/testgen-SLL-SRL-SRA.py deleted file mode 100755 index ede82af48..000000000 --- a/studies/testgen/testgen-SLL-SRL-SRA.py +++ /dev/null @@ -1,154 +0,0 @@ -#!/usr/bin/env python3 -################################## -# testgen-SLL-SRL-SRA.py -# -# David_Harris@hmc.edu 19 January 2021 -# -# Generate directed and random test vectors for RISC-V Design Validation. -################################## - -################################## -# libraries -################################## -from datetime import datetime -from random import randint -from random import seed -from random import getrandbits - -################################## -# functions -################################## - -def twoscomp(a): - amsb = a >> (xlen-1) - alsbs = ((1 << (xlen-1)) - 1) & a - if (amsb): - asigned = a - (1<> b - elif (test == "SRA"): - return asigned >> b - else: - die("bad test name ", test) - # exit(1) - -def randRegs(): - reg1 = randint(1,31) - reg2 = randint(1,31) - reg3 = randint(1,31) - if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2): - return randRegs() - else: - return reg1, reg2, reg3 - -def writeVector(a, b, storecmd, xlen): - global testnum - expected = computeExpected(a, b, test, xlen) - expected = expected % 2**xlen # drop carry if necessary - if (expected < 0): # take twos complement - expected = 2**xlen + expected - reg1, reg2, reg3 = randRegs() - lines = "\n# Testcase " + str(testnum) + ": rs1:x" + str(reg1) + "(" + formatstr.format(a) - lines = lines + "), rs2:x" + str(reg2) + "(" +formatstr.format(b) - lines = lines + "), result rd:x" + str(reg3) + "(" + formatstr.format(expected) +")\n" - lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n" - lines = lines + "li x" + str(reg2) + ", MASK_XLEN(" + formatstr.format(b) + ")\n" - lines = lines + test + " x" + str(reg3) + ", x" + str(reg1) + ", x" + str(reg2) + "\n" - lines = lines + storecmd + " x" + str(reg3) + ", " + str(wordsize*testnum) + "(x6)\n" - lines = lines + "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg3) +", "+formatstr.format(expected)+")\n" - f.write(lines) - if (xlen == 32): - line = formatrefstr.format(expected)+"\n" - else: - line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n" - r.write(line) - testnum = testnum+1 - -################################## -# main body -################################## - -# change these to suite your tests -tests = ["SLL", "SRL", "SRA"] -author = "David_Harris@hmc.edu" -xlens = [32, 64] -numrand = 48 - -# setup -seed(0) # make tests reproducible - -# generate files for each test -for xlen in xlens: - formatstrlen = str(int(xlen/4)) - formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number - formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x - if (xlen == 32): - storecmd = "sw" - wordsize = 4 - else: - storecmd = "sd" - wordsize = 8 - for test in tests: - corners = [0, 1, 2, 0xFF, 0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1, - 2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1] - if (xlen == 32): - shamt = [0, 1, 2, 3, 4, 8, 15, 16, 29, 30, 31] - else: - shamt = [0, 1, 3, 8, 15, 16, 29, 31, 32, 47, 48, 62, 63] - - imperaspath = "../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "i/" - basename = "WALLY-" + test - fname = imperaspath + "src/" + basename + ".S" - refname = imperaspath + "references/" + basename + ".reference_output" - testnum = 0 - - # print custom header part - f = open(fname, "w") - r = open(refname, "w") - line = "///////////////////////////////////////////\n" - f.write(line) - lines="// "+fname+ "\n// " + author + "\n" - f.write(lines) - line ="// Created " + str(datetime.now()) - f.write(line) - - # insert generic header - h = open("testgen_header.S", "r") - for line in h: - f.write(line) - - # print directed and random test vectors - for a in corners: - for b in shamt: - writeVector(a, b, storecmd, xlen) - for i in range(0,numrand): - a = getrandbits(xlen) - b = getrandbits(xlen) - writeVector(a, b, storecmd, xlen) - - - # print footer - h = open("testgen_footer.S", "r") - for line in h: - f.write(line) - - # Finish - lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n" - lines = lines + "\nRV_COMPLIANCE_DATA_END\n" - f.write(lines) - f.close() - r.close() - - - - diff --git a/studies/testgen/testgen-SLLI-SRLI-SRAI.py b/studies/testgen/testgen-SLLI-SRLI-SRAI.py deleted file mode 100644 index cc01f1eb8..000000000 --- a/studies/testgen/testgen-SLLI-SRLI-SRAI.py +++ /dev/null @@ -1,189 +0,0 @@ -#!/usr/bin/env python3 -################################## -# testgen-ADD-SUB.py -# -# David_Harris@hmc.edu 19 January 2021 -# -# Generate directed and random test vectors for RISC-V Design Validation. -################################## - -################################## -# libraries -################################## -from datetime import datetime -from random import randint -from random import seed -from random import getrandbits - -################################## -# functions -################################## - -def computeExpected(a, b, test): - if (test == "SLLI"): - return a << b - elif (test == "SRLI"): - return srli(a,b) - elif (test == "SRAI"): - return a >> b - else: - die("bad test name ", test) - # exit(1) - -def signExt(b, bits): - a_str = bin(b)[2::] - if (a_str[0] == "b"): - a_str = a_str[1:] - - if (len(a_str) < 12): - zeroPadding = "0" * (bits - len(a_str)) - a_str = zeroPadding + a_str - - print( "{:x}, {:s} ".format(b, a_str)) - padding = a_str[len(a_str)-1] * (bits - len(a_str)) - return int(padding + a_str, 2) - - -def evaluateTwoComplement(b, bits): - if (b & (1 << (bits -1))!= 0): - b = b - (1 << bits) - return b - - -def srli(a,b): - if (a < 0): - a = 2**xlen + a - if (b==0): - return a - a_str = bin(a)[2:] - if a_str[0]== "b": - a_str = a_str[1:] - # print(a_str) - numZeroPad = (len(a_str)-abs(b)) - out = a_str[:numZeroPad] - if (numZeroPad <= 0): - return 0 - print("a: {:b}, b: {:d}, out:{:b}".format(a, b, int(out,2))) - return int(out,2) - -def randRegs(): - reg1 = randint(1,31) - reg3 = randint(1,31) - if (reg1 == 6 or reg3 == 6): - return randRegs() - else: - return reg1, reg3 - -def writeVector(a, b, storecmd): - global testnum - - - - - expected = computeExpected(evaluateTwoComplement(a, xlen), b, test) -# print( "original {:x}, sign Extended {:x} ".format(b, signExt(b,xlen))) -# print (str(a) + "<" + str(signExt(b,xlen)) + " : " + str(expected)) - expected = expected % 2**xlen # drop carry if necessary - if (expected < 0): # take twos complement - expected = 2**xlen + expected - - - - reg1, reg3 = randRegs() - lines = "\n# Testcase " + str(testnum) + ": rs1:x" + str(reg1) + "(" + formatstr.format(a) - lines = lines + "), imm5:" + "(" +formatstrimm5.format(b) - lines = lines + "), result rd:x" + str(reg3) + "(" + formatstr.format(expected) +")\n" - lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n" - lines = lines + test + " x" + str(reg3) + ", x" + str(reg1) + ", " + formatstrimm5.format(b) + "\n" - # lines = lines + test + " x" + str(reg3) + ", x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(b) + ")\n" - lines = lines + storecmd + " x" + str(reg3) + ", " + str(wordsize*testnum) + "(x6)\n" - lines = lines + "RVTEST_IO_ASSERT_GPR_EQ(x7, " +"x" + str(reg3) +", "+formatstr.format(expected)+")\n" - f.write(lines) - if (xlen == 32): - line = formatrefstr.format(expected)+"\n" - else: - line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n" - r.write(line) - testnum = testnum+1 - -################################## -# main body -################################## - -# change these to suite your tests -tests = ["SLLI", "SRLI", "SRAI"] -author = "Shriya Nadgauda & Ethan Falicov" -xlens = [32, 64] -numrand = 100 - - -# setup -seed(0) # make tests reproducible - -# generate files for each test -for xlen in xlens: - formatstrlen = str(int(xlen/4)) - formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number - formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x - - formatstrimm5 = "0b{:05b}" # format as 5-bit binary number - if (xlen == 32): - storecmd = "sw" - wordsize = 4 - else: - storecmd = "sd" - wordsize = 8 - - for test in tests: - corners1 = [0, 1, 2, 0xFF, 0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1, - 2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1] - - immBitSize = 5 - corners2 = [0, 1, 2, 0x07, 0x14 % 2**immBitSize, 2**(immBitSize-1)-2, 2**(immBitSize-1)-1, - 2**(immBitSize-1), 2**(immBitSize-1)+1, 0x06 % 2**immBitSize, 2**(immBitSize)-2, 2**(immBitSize)-1] - - imperaspath = "../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "i/" - basename = "WALLY-" + test - fname = imperaspath + "src/" + basename + ".S" - refname = imperaspath + "references/" + basename + ".reference_output" - testnum = 0 - - # print custom header part - f = open(fname, "w") - r = open(refname, "w") - line = "///////////////////////////////////////////\n" - f.write(line) - lines="// "+fname+ "\n// " + author + "\n" - f.write(lines) - line ="// Created " + str(datetime.now()) - f.write(line) - - # insert generic header - h = open("testgen_header.S", "r") - for line in h: - f.write(line) - - # print directed and random test vectors - for a in corners1: - for b in corners2: - writeVector(a, b, storecmd) - for i in range(0,numrand): - a = getrandbits(xlen) - b = getrandbits(5) - writeVector(a, b, storecmd) - - - # print footer - h = open("testgen_footer.S", "r") - for line in h: - f.write(line) - - # Finish - lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n" - lines = lines + "\nRV_COMPLIANCE_DATA_END\n" - f.write(lines) - f.close() - r.close() - - - diff --git a/studies/testgen/testgen-SLTIU.py b/studies/testgen/testgen-SLTIU.py deleted file mode 100644 index 8642a7aec..000000000 --- a/studies/testgen/testgen-SLTIU.py +++ /dev/null @@ -1,173 +0,0 @@ -#!/usr/bin/env python3 -################################## -# testgen-ADD-SUB.py -# -# David_Harris@hmc.edu 19 January 2021 -# -# Generate directed and random test vectors for RISC-V Design Validation. -################################## - -################################## -# libraries -################################## -from datetime import datetime -from random import randint -from random import seed -from random import getrandbits - -################################## -# functions -################################## - -def computeExpected(a, b, test): - if (test == "SLTIU"): - return a < b - else: - die("bad test name ", test) - # exit(1) - -def signExt(b, bits): - a_str = bin(b)[2::] - if (a_str[0] == "b"): - a_str = a_str[1:] - - if (len(a_str) < 12): - zeroPadding = "0" * (12 - len(a_str)) - a_str = zeroPadding + a_str - - - padding = a_str[0] * (bits - len(a_str)) - print( "b {:x}, sign extended {:s} ".format(b, padding + a_str)) - return int(padding + a_str, 2) - - - -def evaluateTwoComplement(b, bits): - if (b & (1 << (bits -1))!= 0): - b = b - (1 << bits) - return b - - -def randRegs(): - reg1 = randint(1,31) - reg3 = randint(1,31) - if (reg1 == 6 or reg3 == 6): - return randRegs() - else: - return reg1, reg3 - -def writeVector(a, b, storecmd): - global testnum - - - - signExtImm = signExt(b,xlen) - if signExtImm < 0: - signExtImm = signExtImm + 2 ** xlen - expected = computeExpected(a, signExtImm, test) - # s - - expected = expected % 2**xlen # drop carry if necessary - if (expected < 0): # take twos complement - expected = 2**xlen + expected - - - - reg1, reg3 = randRegs() - lines = "\n# Testcase " + str(testnum) + ": rs1:x" + str(reg1) + "(" + formatstr.format(a) - lines = lines + "), imm12:" + "(" +formatstrimm12.format(b) - lines = lines + "), result rd:x" + str(reg3) + "(" + formatstr.format(expected) +")\n" - lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n" - lines = lines + test + " x" + str(reg3) + ", x" + str(reg1) + ", SEXT_IMM(" + formatstrimm12.format(b) + ")\n" - # lines = lines + test + " x" + str(reg3) + ", x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(b) + ")\n" - lines = lines + storecmd + " x" + str(reg3) + ", " + str(wordsize*testnum) + "(x6)\n" - lines = lines + "RVTEST_IO_ASSERT_GPR_EQ(x7, " +"x" + str(reg3) +", "+formatstr.format(expected)+")\n" - f.write(lines) - if (xlen == 32): - line = formatrefstr.format(expected)+"\n" - else: - line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n" - r.write(line) - testnum = testnum+1 - -################################## -# main body -################################## - -# change these to suite your tests -tests = ["SLTIU"] -author = "Shriya Nadgauda & Ethan Falicov" -xlens = [32, 64] -numrand = 100 - - -# setup -seed(0) # make tests reproducible - -# generate files for each test -for xlen in xlens: - formatstrlen = str(int(xlen/4)) - formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number - formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x - - formatstrimm12 = "0x{:03x}" # format as 3-bit hexadecimal number - if (xlen == 32): - storecmd = "sw" - wordsize = 4 - else: - storecmd = "sd" - wordsize = 8 - - for test in tests: - corners1 = [0, 1, 2, 0xFF, 0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1, - 2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1] - - immBitSize = 12 - corners2 = [0, 1, 2, 0xFF, 0x624 % 2**immBitSize, 2**(immBitSize-1)-2, 2**(immBitSize-1)-1, - 2**(immBitSize-1), 2**(immBitSize-1)+1, 0xC36 % 2**immBitSize, 2**(immBitSize)-2, 2**(immBitSize)-1] - - imperaspath = "../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "i/" - basename = "WALLY-" + test - fname = imperaspath + "src/" + basename + ".S" - refname = imperaspath + "references/" + basename + ".reference_output" - testnum = 0 - - # print custom header part - f = open(fname, "w") - r = open(refname, "w") - line = "///////////////////////////////////////////\n" - f.write(line) - lines="// "+fname+ "\n// " + author + "\n" - f.write(lines) - line ="// Created " + str(datetime.now()) - f.write(line) - - # insert generic header - h = open("testgen_header.S", "r") - for line in h: - f.write(line) - - # print directed and random test vectors - for a in corners1: - for b in corners2: - writeVector(a, b, storecmd) - for i in range(0,numrand): - a = getrandbits(xlen) - b = getrandbits(12) - writeVector(a, b, storecmd) - - - # print footer - h = open("testgen_footer.S", "r") - for line in h: - f.write(line) - - # Finish - lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n" - lines = lines + "\nRV_COMPLIANCE_DATA_END\n" - f.write(lines) - f.close() - r.close() - - - diff --git a/studies/testgen/testgen-STORE.py b/studies/testgen/testgen-STORE.py deleted file mode 100755 index 4f3944c70..000000000 --- a/studies/testgen/testgen-STORE.py +++ /dev/null @@ -1,282 +0,0 @@ -#!/usr/bin/env python3 -################################## -# testgen-STORE.py -# -# Jessica Torrey 03 February 2021 -# Thomas Fleming 03 February 2021 -# -# Generate directed and random test vectors for RISC-V Design Validation. -################################## - -################################## -# libraries -################################## -from datetime import datetime -from random import randint, seed, getrandbits -from textwrap import dedent - -################################## -# global structures -################################## -size_to_store = {8: "sd", 4: "sw", 2: "sh", 1: "sb"} -size_to_load = {8: "ld", 4: "lw", 2: "lh", 1: "lb"} -store_to_size = {"sd": 8, "sw": 4, "sh": 2, "sb": 1} -testcase_num = 0 -signature_len = 2000 -signature = [0xff for _ in range(signature_len)] - -################################## -# functions -################################## - -def rand_reg(): - """ - Produce a random register from 1 to 31 (skipping 6, since r6 is used for - other things). - """ - r = randint(1,30) - if r >= 6: - r += 1 - return r - -def rand_regs(): - """ - Generate two random, unequal register numbers (skipping x6). - """ - rs1 = rand_reg() - rs2 = rand_reg() - while rs1 == rs2: - rs2 = rand_reg() - - return rs1, rs2 - -def generate_case(xlen, instruction, value_register, value, addr_register, offset, base_delta): - """ - Create assembly code for a given STORE test case, returned as a string. - - Generates an `xlen`-bit test case for `instruction` (one of sb, sh, sw, or - sd) that loads `value` into `value_register`, then attempts to store that - value in memory at address (x6 + `base_delta`). The test case - assumes the current base address for the signature is in register x6. - - The form of the STORE instruction is as follows: - - `instruction` `value_register` `offset`(`addr_register`) - """ - global testcase_num - - hex_value = f"{value:0{xlen // 4}x}" - - data = f"""# Testcase {testcase_num}: source: x{value_register} (value 0x{hex_value}), destination: {offset}(x{addr_register}) ({base_delta} bytes into signature) - addi x{addr_register}, x6, {base_delta} - li x{value_register}, MASK_XLEN({-offset}) - add x{addr_register}, x{addr_register}, x{value_register} - li x{value_register}, 0x{hex_value} - {instruction} x{value_register}, {offset}(x{addr_register}) - """ - - update_signature(store_to_size[instruction], value, base_delta) - - testcase_num += 1 - return data - -def validate_memory(scratch_register, value_register, value, base_delta, length): - """ - Create assembly code to verify that `length` bytes at mem[x6 + `base_delta`] - store `value`. - - Assumes x6 stores the current base address for the signature. - """ - truncated_value = value & (2**(length * 8) - 1) - hex_value = f"{truncated_value:0{length * 2}x}" - - load = size_to_load[length] - data = f"""addi x{scratch_register}, x6, {base_delta} - {load} x{value_register}, 0(x{scratch_register}) - RVTEST_IO_ASSERT_GPR_EQ(x{scratch_register}, x{value_register}, 0x{hex_value}) - - """ - return data - -def update_signature(length, value, base_delta): - """ - Write the lower `length` bytes of `value` to the little-endian signature - array, starting at byte `base_delta`. - """ - truncated_value = value & (2**(length * 8) - 1) - value_bytes = truncated_value.to_bytes(length, 'little') - #print("n: {}, value: {:x}, trunc: {:x}, length: {}, bd: {:x}".format(testcase_num, value, truncated_value, length, base_delta)) - for i in range(length): - signature[base_delta + i] = value_bytes[i] - -def write_signature(outfile): - """ - Writes successive 32-bit words from the signature array into a given file. - """ - for i in range(0, signature_len, 4): - word = list(reversed(signature[i:i+4])) - hexword = bytearray(word).hex() - outfile.write(f"{hexword}\n") - -def write_header(outfile): - """ - Write the name of the test file, authors, and creation date. - """ - outfile.write(dedent(f"""\ - /////////////////////////////////////////// - // - // WALLY-STORE - // - // Author: {author} - // - // Created {str(datetime.now())} - """)) - outfile.write(open("testgen_header.S", "r").read()) - -def write_footer(outfile): - """ - Write necessary closing code, including a data section for the signature. - """ - outfile.write(open("testgen_footer.S", 'r').read()) - data_section = dedent(f"""\ - \t.fill {signature_len}, 1, -1 - RV_COMPLIANCE_DATA_END - """) - outfile.write(data_section) - -################################## -# test cases -################################## - -def write_basic_tests(outfile, xlen, instr_len, num, base_delta): - """ - Test basic functionality of STORE, using random registers, offsets, and - values. - - Creates `num` tests for a single store instruction of length `instr_len`, - writing to memory at consecutive locations, starting `base_delta` bytes from - the start of the signature. - - Returns the number of bytes from the start of the signature where testing - ended. - """ - instruction = size_to_store[instr_len] - for i in range(num): - value_register, addr_register = rand_regs() - offset = randint(-2**(12 - 1), 2**(12 - 1) - 1) - value = randint(0, 2**(instr_len * 8) - 1) - test = generate_case(xlen, instruction, value_register, value, addr_register, offset, base_delta) - validate = validate_memory(addr_register, value_register, value, base_delta, instr_len) - outfile.write(test) - outfile.write(validate) - base_delta += instr_len - return base_delta - -def write_random_store_tests(outfile, xlen, instr_len, num, min_base_delta): - """ - Test random access of STORE, using random registers, offsets, values, and - memory locations. - - Creates `num` tests for a single store instruction of length `instr_len`, - writing to memory at random locations between `min_base_delta` bytes past - the start of the signature to the end of the signature. - """ - instruction = size_to_store[instr_len] - for i in range(num): - base_delta = randint(min_base_delta, signature_len - 1) - base_delta -= (base_delta % instr_len) - value_register, addr_register = rand_regs() - offset = randint(-2**(12 - 1), 2**(12 - 1) - 1) - value = randint(0, 2**(instr_len * 8) - 1) - - test = generate_case(xlen, instruction, value_register, value, addr_register, offset, base_delta) - validate = validate_memory(addr_register, value_register, value, base_delta, instr_len) - outfile.write(test) - outfile.write(validate) - -def write_repeated_store_tests(outfile, xlen, instr_len, num, base_delta): - """ - Test repeated access of STORE, using random registers, offsets, values, and a - single memory location. - - Creates `num` tests for a single store instruction of length `instr_len`, - writing to memory `base_delta` bytes past the start of the signature. - """ - instruction = size_to_store[instr_len] - for i in range(num): - value_register, addr_register = rand_regs() - offset = 0 - value = (1 << ((2 * i) % xlen)) - - test = generate_case(xlen, instruction, value_register, value, addr_register, offset, base_delta) - validate = validate_memory(addr_register, value_register, value, base_delta, instr_len) - - outfile.write(test) - outfile.write(validate) - -def write_corner_case_tests(outfile, xlen, instr_len, base_delta): - instruction = size_to_store[instr_len] - - corner_cases_32 = [0x0, 0x10000001, 0x01111111] - corner_cases_64 = [0x1000000000000001, 0x0111111111111111] - corner_cases = corner_cases_32 - if xlen == 64: - corner_cases += corner_cases_64 - - for offset in corner_cases: - for value in corner_cases: - value_register, addr_register = rand_regs() - test = generate_case(xlen, instruction, value_register, value, addr_register, offset, base_delta) - validate = validate_memory(addr_register, value_register, value, base_delta, instr_len) - - outfile.write(test) - outfile.write(validate) - - base_delta += instr_len - - return base_delta - -################################## -# main body -################################## - -instructions = ["sd", "sw", "sh", "sb"] -author = "Jessica Torrey & Thomas Fleming " -xlens = [32, 64] -numrand = 100 - -# setup -seed(0) # make tests reproducible - -for xlen in xlens: - if (xlen == 32): - wordsize = 4 - else: - wordsize = 8 - - fname = f"../../imperas-riscv-tests/riscv-test-suite/rv{xlen}i/src/WALLY-STORE.S" - refname = f"../../imperas-riscv-tests/riscv-test-suite/rv{xlen}i/references/WALLY-STORE.reference_output" - f = open(fname, "w") - r = open(refname, "w") - - write_header(f) - - base_delta = 0 - - for instruction in instructions: - if xlen == 32 and instruction == 'sd': - continue - instr_len = store_to_size[instruction] - base_delta = write_basic_tests(f, xlen, instr_len, 5, base_delta) - write_repeated_store_tests(f, xlen, instr_len, 32, base_delta) - write_random_store_tests(f, xlen, instr_len, 5, base_delta + wordsize) - - write_footer(f) - - write_signature(r) - f.close() - r.close() - - # Reset testcase_num and signature - testcase_num = 0 - signature = [0xff for _ in range(signature_len)] diff --git a/studies/testgen/testgen-VIRTUALMEMORY.py b/studies/testgen/testgen-VIRTUALMEMORY.py deleted file mode 100644 index 310e96b3c..000000000 --- a/studies/testgen/testgen-VIRTUALMEMORY.py +++ /dev/null @@ -1,285 +0,0 @@ -#!/usr/bin/env python3 -################################## -# testgen-VIRTUALMEMORY.py -# -# Jessica Torrey 01 March 2021 -# Thomas Fleming 01 March 2021 -# -# Generate an ad-hoc test program for RISC-V Design Validation. Tests the -# functionality of the memory management unit (MMU). -################################## - -################################## -# libraries -################################## -from datetime import datetime -from random import randint, seed, getrandbits -from textwrap import dedent -from virtual_memory_util import * - -################################## -# global structures -################################## - -testcase_num = 0 -signature_len = 2000 -signature = [0xff for _ in range(signature_len)] - -################################## -# functions -################################## - -def rand_reg(): - """ - Produce a random register from 1 to 31 (skipping 6, since r6 is used for - other things). - """ - r = randint(1,30) - if r >= 6: - r += 1 - return r - -def rand_regs(): - """ - Generate two random, unequal register numbers (skipping x6). - """ - rs1 = rand_reg() - rs2 = rand_reg() - while rs1 == rs2: - rs2 = rand_reg() - - return rs1, rs2 - -def initialize_page_directory() - -def generate_case(xlen, instruction, value_register, value, addr_register, offset, base_delta): - """ - Create assembly code for a given STORE test case, returned as a string. - - Generates an `xlen`-bit test case for `instruction` (one of sb, sh, sw, or - sd) that loads `value` into `value_register`, then attempts to store that - value in memory at address (x6 + `base_delta`). The test case - assumes the current base address for the signature is in register x6. - - The form of the STORE instruction is as follows: - - `instruction` `value_register` `offset`(`addr_register`) - """ - global testcase_num - - hex_value = f"{value:0{xlen // 4}x}" - - data = f"""# Testcase {testcase_num}: source: x{value_register} (value 0x{hex_value}), destination: {offset}(x{addr_register}) ({base_delta} bytes into signature) - addi x{addr_register}, x6, {base_delta} - li x{value_register}, MASK_XLEN({-offset}) - add x{addr_register}, x{addr_register}, x{value_register} - li x{value_register}, 0x{hex_value} - {instruction} x{value_register}, {offset}(x{addr_register}) - """ - - #update_signature(store_to_size[instruction], value, base_delta) - - testcase_num += 1 - return data - -def validate_memory(scratch_register, value_register, value, base_delta, length): - """ - Create assembly code to verify that `length` bytes at mem[x6 + `base_delta`] - store `value`. - - Assumes x6 stores the current base address for the signature. - """ - truncated_value = value & (2**(length * 8) - 1) - hex_value = f"{truncated_value:0{length * 2}x}" - - load = size_to_load[length] - data = f"""addi x{scratch_register}, x6, {base_delta} - {load} x{value_register}, 0(x{scratch_register}) - RVTEST_IO_ASSERT_GPR_EQ(x{scratch_register}, x{value_register}, 0x{hex_value}) - - """ - return data - -def update_signature(length, value, base_delta): - """ - Write the lower `length` bytes of `value` to the little-endian signature - array, starting at byte `base_delta`. - """ - truncated_value = value & (2**(length * 8) - 1) - value_bytes = truncated_value.to_bytes(length, 'little') - #print("n: {}, value: {:x}, trunc: {:x}, length: {}, bd: {:x}".format(testcase_num, value, truncated_value, length, base_delta)) - for i in range(length): - signature[base_delta + i] = value_bytes[i] - -def write_signature(outfile): - """ - Writes successive 32-bit words from the signature array into a given file. - """ - for i in range(0, signature_len, 4): - word = list(reversed(signature[i:i+4])) - hexword = bytearray(word).hex() - outfile.write(f"{hexword}\n") - -def write_header(outfile): - """ - Write the name of the test file, authors, and creation date. - """ - outfile.write(dedent(f"""\ - /////////////////////////////////////////// - // - // WALLY-STORE - // - // Author: {author} - // - // Created {str(datetime.now())} - """)) - outfile.write(open("testgen_header.S", "r").read()) - -def write_footer(outfile): - """ - Write necessary closing code, including a data section for the signature. - """ - outfile.write(open("testgen_footer.S", 'r').read()) - data_section = dedent(f"""\ - \t.fill {signature_len}, 1, -1 - RV_COMPLIANCE_DATA_END - """) - outfile.write(data_section) - -################################## -# test cases -################################## - -def write_basic_tests(outfile, xlen, instr_len, num, base_delta): - """ - Test basic functionality of STORE, using random registers, offsets, and - values. - - Creates `num` tests for a single store instruction of length `instr_len`, - writing to memory at consecutive locations, starting `base_delta` bytes from - the start of the signature. - - Returns the number of bytes from the start of the signature where testing - ended. - """ - instruction = size_to_store[instr_len] - for i in range(num): - value_register, addr_register = rand_regs() - offset = randint(-2**(12 - 1), 2**(12 - 1) - 1) - value = randint(0, 2**(instr_len * 8) - 1) - test = generate_case(xlen, instruction, value_register, value, addr_register, offset, base_delta) - validate = validate_memory(addr_register, value_register, value, base_delta, instr_len) - outfile.write(test) - outfile.write(validate) - base_delta += instr_len - return base_delta - -def write_random_store_tests(outfile, xlen, instr_len, num, min_base_delta): - """ - Test random access of STORE, using random registers, offsets, values, and - memory locations. - - Creates `num` tests for a single store instruction of length `instr_len`, - writing to memory at random locations between `min_base_delta` bytes past - the start of the signature to the end of the signature. - """ - instruction = size_to_store[instr_len] - for i in range(num): - base_delta = randint(min_base_delta, signature_len - 1) - base_delta -= (base_delta % instr_len) - value_register, addr_register = rand_regs() - offset = randint(-2**(12 - 1), 2**(12 - 1) - 1) - value = randint(0, 2**(instr_len * 8) - 1) - - test = generate_case(xlen, instruction, value_register, value, addr_register, offset, base_delta) - validate = validate_memory(addr_register, value_register, value, base_delta, instr_len) - outfile.write(test) - outfile.write(validate) - -def write_repeated_store_tests(outfile, xlen, instr_len, num, base_delta): - """ - Test repeated access of STORE, using random registers, offsets, values, and a - single memory location. - - Creates `num` tests for a single store instruction of length `instr_len`, - writing to memory `base_delta` bytes past the start of the signature. - """ - instruction = size_to_store[instr_len] - for i in range(num): - value_register, addr_register = rand_regs() - offset = 0 - value = (1 << ((2 * i) % xlen)) - - test = generate_case(xlen, instruction, value_register, value, addr_register, offset, base_delta) - validate = validate_memory(addr_register, value_register, value, base_delta, instr_len) - - outfile.write(test) - outfile.write(validate) - -def write_corner_case_tests(outfile, xlen, instr_len, base_delta): - instruction = size_to_store[instr_len] - - corner_cases_32 = [0x0, 0x10000001, 0x01111111] - corner_cases_64 = [0x1000000000000001, 0x0111111111111111] - corner_cases = corner_cases_32 - if xlen == 64: - corner_cases += corner_cases_64 - - for offset in corner_cases: - for value in corner_cases: - value_register, addr_register = rand_regs() - test = generate_case(xlen, instruction, value_register, value, addr_register, offset, base_delta) - validate = validate_memory(addr_register, value_register, value, base_delta, instr_len) - - outfile.write(test) - outfile.write(validate) - - base_delta += instr_len - - return base_delta - -################################## -# main body -################################## - -if __name__ == "__main__": - instructions = ["sd", "sw", "sh", "sb"] - author = "Jessica Torrey & Thomas Fleming " - xlens = [32, 64] - numrand = 100 - - # setup - seed(0) # make tests reproducible - - for xlen in xlens: - if (xlen == 32): - wordsize = 4 - else: - wordsize = 8 - - fname = f"../../imperas-riscv-tests/riscv-test-suite/rv{xlen}i/src/WALLY-VIRTUALMEMORY.S" - refname = f"../../imperas-riscv-tests/riscv-test-suite/rv{xlen}i/references/WALLY-VIRTUALMEMORY.reference_output" - f = open(fname, "w") - r = open(refname, "w") - - write_header(f) - - base_delta = 0 - - for instruction in instructions: - if xlen == 32 and instruction == 'sd': - continue - instr_len = store_to_size[instruction] - base_delta = write_basic_tests(f, xlen, instr_len, 5, base_delta) - write_repeated_store_tests(f, xlen, instr_len, 32, base_delta) - write_random_store_tests(f, xlen, instr_len, 5, base_delta + wordsize) - - write_footer(f) - - write_signature(r) - f.close() - r.close() - - # Reset testcase_num and signature - testcase_num = 0 - signature = [0xff for _ in range(signature_len)] \ No newline at end of file diff --git a/tests/coverage/amoAccessFault.S b/tests/coverage/amoAccessFault.S new file mode 100644 index 000000000..a8ecf5f0d --- /dev/null +++ b/tests/coverage/amoAccessFault.S @@ -0,0 +1,53 @@ +/////////////////////////////////////////// +// hptwAccessFault.S +// +// Written: Rose Thompson rose@rosethompson.net +// +// Purpose: Checks that only Store/AMO access faults are generated on AMO operations +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate + +#include "WALLY-init-lib.h" + +# run-elf.bash find this in project description +main: + + la t1, data # first a valid AMO + li t2, 2 + li t3, 3 + amoadd.d t3, t2, (t1) + + li t1, 0x90000000 # invalid AMO address + li t2, 2 + li t3, 3 + amoadd.d t3, t2, (t1) + + fence.I + +finished: + j done + + .data + +.align 8 +data: + .8byte 0x1 diff --git a/tests/coverage/hptwAccessFault.S b/tests/coverage/hptwAccessFault.S new file mode 100644 index 000000000..7c1bc3be1 --- /dev/null +++ b/tests/coverage/hptwAccessFault.S @@ -0,0 +1,143 @@ +/////////////////////////////////////////// +// hptwAccessFault.S +// +// Written: Rose Thompson rose@rosethompson.net +// +// Purpose: Force the HPTW to walk a page table with invalid addresses so that the pma checker +// generate access faults. +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate + +#include "WALLY-init-lib.h" + +# run-elf.bash find this in project description +main: + + # Page table root address at 0x80010000 + li t5, 0x9000000000080010 + csrw satp, t5 + + # sfence.vma x0, x0 + + # switch to supervisor mode + li a0, 1 + ecall + li t5, 0 + li t2, 0x1000 + li t0, 0x8000001000 + + lw t1, 0(t0) # this load is a valid virtual address, but the page table will access an invalid address so it should cause a load access fault + li t1, 0x00008067 # this store is a valid virtual address, but the page table will access an invalid address so it should cause a store access fault + add t0, t0, t2 + sw t1, 0(t0) + + fence.I + +finished: + j done + +.data + +.align 16 +# Page table situated at 0x80010000 +pagetable: + .8byte 0x200044C1 + .8byte 0x300044C1 # point to invalid region of physical memory + +.align 12 + .8byte 0x00000040200048C1 + .8byte 0x00000000200048C1 + .8byte 0x00000000200048C1 + + +.align 12 + .8byte 0x0000000020004CC1 + +.align 12 + #80000000 + .8byte 0x200000CF + .8byte 0x200004CF + .8byte 0x200008CF + .8byte 0x20000CCF + + .8byte 0x200010CF + .8byte 0x200014CF + .8byte 0x200018CF + .8byte 0x20001CCF + + .8byte 0x200020CF + .8byte 0x200024CF + .8byte 0x200028CF + .8byte 0x20002CCF + + .8byte 0x200030CF + .8byte 0x200034CF + .8byte 0x200038CF + .8byte 0x20003CCF + + .8byte 0x200040CF + .8byte 0x200044CF + .8byte 0x200048CF + .8byte 0x20004CCF + + .8byte 0x200050CF + .8byte 0x200054CF + .8byte 0x200058CF + .8byte 0x20005CCF + + .8byte 0x200060CF + .8byte 0x200064CF + .8byte 0x200068CF + .8byte 0x20006CCF + + .8byte 0x200070CF + .8byte 0x200074CF + .8byte 0x200078CF + .8byte 0x20007CCF + + .8byte 0x200080CF + .8byte 0x200084CF + .8byte 0x200088CF + .8byte 0x20008CCF + + .8byte 0x200090CF + .8byte 0x200094CF + .8byte 0x200098CF + .8byte 0x20009CCF + + .8byte 0x2000A0CF + .8byte 0x2000A4CF + .8byte 0x2000A8CF + .8byte 0x2000ACCF + + .8byte 0x2000B0CF + .8byte 0x2000B4CF + .8byte 0x2000B8CF + .8byte 0x2000BCCF + + .8byte 0x2000C0CF + .8byte 0x2000C4CF + .8byte 0x2000C8CF + .8byte 0x2000CCCF + + .8byte 0x2000D0CF + .8byte 0x2000D4CF diff --git a/tests/coverage/tlbMisaligned.S b/tests/coverage/tlbMisaligned.S new file mode 100644 index 000000000..e683c9a86 --- /dev/null +++ b/tests/coverage/tlbMisaligned.S @@ -0,0 +1,152 @@ +/////////////////////////////////////////// +// tlbMisaligned.S +// +// Written: Rose Thompson rose@rosethompson.net +// +// Purpose: Create a page table with misaligned load and store access. Checks TLB misses prevent misaligned load/store fault. +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate + +#include "WALLY-init-lib.h" + +# run-elf.bash find this in project description +main: + li t5, 0x1 + slli t5, t5, 62 + ori t5, t5, 0xF0 + csrs menvcfg, t5 # menvcfg.PBMTE = 1, CBZE, CBCFE, CBIE all 1 + + # Page table root address at 0x80010000 + li t5, 0x9000000000080010 + csrw satp, t5 + + # sfence.vma x0, x0 + + # switch to supervisor mode + li a0, 1 + ecall + li t5, 0 + li t2, 0x1000 + li t0, 0x1000 // go to first gigapage + li t4, 0x40000000 // put this outside the loop. + + lw t1, 1(t0) # load a misaligned aligned cached address + li t1, 0x00008067 #load in jalr + add t0, t0, t2 # go to the next page + sw t1, 1(t0) # store to another misaligned cached address. + + add t0, t0, t2 # go to the next page + lw t1, 1(t0) # load a misaligned aligned uncached address should fault + add t0, t0, t2 # go to the next page + sw t1, 1(t0) # store to another misaligned uncached address should falt. + + fence.I + +finished: + j done + +.data + +.align 16 +# Page table situated at 0x80010000 +pagetable: + .8byte 0x200044C1 + +.align 12 + .8byte 0x00000000200048C1 + .8byte 0x00000000200048C1 + .8byte 0x00000000200048C1 + + +.align 12 + .8byte 0x0000000020004CC1 + //.8byte 0x00000200800CF// ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed? + +.align 12 + #80000000 + .8byte 0x200000CF + .8byte 0x200004CF # first page + .8byte 0x200008CF # second page + .8byte 0x2000000020000CCF # 3rd page + + .8byte 0x20000000200010CF # 4th page + .8byte 0x200014CF + .8byte 0x200018CF + .8byte 0x20001CCF + + .8byte 0x200020CF + .8byte 0x200024CF + .8byte 0x200028CF + .8byte 0x20002CCF + + .8byte 0x200030CF + .8byte 0x200034CF + .8byte 0x200038CF + .8byte 0x20003CCF + + .8byte 0x200040CF + .8byte 0x200044CF + .8byte 0x200048CF + .8byte 0x20004CCF + + .8byte 0x200050CF + .8byte 0x200054CF + .8byte 0x200058CF + .8byte 0x20005CCF + + .8byte 0x200060CF + .8byte 0x200064CF + .8byte 0x200068CF + .8byte 0x20006CCF + + .8byte 0x200070CF + .8byte 0x200074CF + .8byte 0x200078CF + .8byte 0x20007CCF + + .8byte 0x200080CF + .8byte 0x200084CF + .8byte 0x200088CF + .8byte 0x20008CCF + + .8byte 0x200090CF + .8byte 0x200094CF + .8byte 0x200098CF + .8byte 0x20009CCF + + .8byte 0x2000A0CF + .8byte 0x2000A4CF + .8byte 0x2000A8CF + .8byte 0x2000ACCF + + .8byte 0x2000B0CF + .8byte 0x2000B4CF + .8byte 0x2000B8CF + .8byte 0x2000BCCF + + .8byte 0x2000C0CF + .8byte 0x2000C4CF + .8byte 0x2000C8CF + .8byte 0x2000CCCF + + .8byte 0x2000D0CF + .8byte 0x2000D4CF diff --git a/tests/custom/boot/Makefile b/tests/custom/boot/Makefile deleted file mode 100644 index fb3b62c7e..000000000 --- a/tests/custom/boot/Makefile +++ /dev/null @@ -1,114 +0,0 @@ -CEXT := c -CPPEXT := cpp -AEXT := s -SEXT := S -SRCEXT := \([$(CEXT)$(AEXT)$(SEXT)]\|$(CPPEXT)\) -OBJEXT := o -DEPEXT := d -SRCDIR := . -BUILDDIR := OBJ - -SOURCES ?= $(shell find $(SRCDIR) -type f -regex ".*\.$(SRCEXT)" | sort) -OBJECTS := $(SOURCES:.$(CEXT)=.$(OBJEXT)) -OBJECTS := $(OBJECTS:.$(AEXT)=.$(OBJEXT)) -OBJECTS := $(OBJECTS:.$(SEXT)=.$(OBJEXT)) -OBJECTS := $(OBJECTS:.$(CPPEXT)=.$(OBJEXT)) -OBJECTS := $(patsubst $(SRCDIR)/%,$(BUILDDIR)/%,$(OBJECTS)) - -TARGETDIR := bin -TARGET := $(TARGETDIR)/boot -ROOT := .. -LIBRARY_DIRS := -LIBRARY_FILES := - -MARCH :=-march=rv64imfdc -MABI :=-mabi=lp64d -LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -L $(RISCV)/riscv64-unknown-elf/lib -LINKER :=$(ROOT)/linker1000.x - - -AFLAGS =$(MARCH) $(MABI) -W -# Override directive allows us to prepend other options on the command line -# e.g. $ make CFLAGS=-g -override CFLAGS +=$(MARCH) $(MABI) -mcmodel=medany -O2 -g -AS=riscv64-unknown-elf-as -CC=riscv64-unknown-elf-gcc -AR=riscv64-unknown-elf-ar - - -#Default Make -all: directories $(TARGET).memfile - -#Remake -remake: clean all - -#Make the Directories -directories: - @mkdir -p $(TARGETDIR) - @mkdir -p $(BUILDDIR) - -clean: - rm -rf $(BUILDDIR) $(TARGETDIR) *.memfile *.objdump - - -#Needed for building additional library projects -ifdef LIBRARY_DIRS -LIBS+=${LIBRARY_DIRS:%=-L%} ${LIBRARY_FILES:%=-l%} -INC+=${LIBRARY_DIRS:%=-I%} - -${LIBRARY_DIRS}: - $(MAKE) -C $@ -j 1 - -.PHONY: $(LIBRARY_DIRS) $(TARGET) -endif - - -#Pull in dependency info for *existing* .o files --include $(OBJECTS:.$(OBJEXT)=.$(DEPEXT)) - -#Link -$(TARGET): $(OBJECTS) $(LIBRARY_DIRS) - $(CC) $(LINK_FLAGS) -g -o $(TARGET) $(OBJECTS) ${LIBS} -T ${LINKER} - - -#Compile -$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(CEXT) - @mkdir -p $(dir $@) - $(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list - @$(CC) $(CFLAGS) $(INC) -MM $(SRCDIR)/$*.$(CEXT) > $(BUILDDIR)/$*.$(DEPEXT) - @cp -f $(BUILDDIR)/$*.$(DEPEXT) $(BUILDDIR)/$*.$(DEPEXT).tmp - @sed -e 's|.*:|$(BUILDDIR)/$*.$(OBJEXT):|' < $(BUILDDIR)/$*.$(DEPEXT).tmp > $(BUILDDIR)/$*.$(DEPEXT) - @sed -e 's/.*://' -e 's/\\$$//' < $(BUILDDIR)/$*.$(DEPEXT).tmp | fmt -1 | sed -e 's/^ *//' -e 's/$$/:/' >> $(BUILDDIR)/$*.$(DEPEXT) - @rm -f $(BUILDDIR)/$*.$(DEPEXT).tmp - -# gcc won't output dependencies for assembly files for some reason -# most asm files don't have dependencies so the echo will work for now. -$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(AEXT) - @mkdir -p $(dir $@) - $(CC) $(CFLAGS) -c -o $@ $< > $(BUILDDIR)/$*.list - @echo $@: $< > $(BUILDDIR)/$*.$(DEPEXT) - -$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(SEXT) - @mkdir -p $(dir $@) - $(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list - @echo $@: $< > $(BUILDDIR)/$*.$(DEPEXT) - -# C++ -$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(CPPEXT) - @mkdir -p $(dir $@) - $(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list - @$(CC) $(CFLAGS) $(INC) -MM $(SRCDIR)/$*.$(CPPEXT) > $(BUILDDIR)/$*.$(DEPEXT) - @cp -f $(BUILDDIR)/$*.$(DEPEXT) $(BUILDDIR)/$*.$(DEPEXT).tmp - @sed -e 's|.*:|$(BUILDDIR)/$*.$(OBJEXT):|' < $(BUILDDIR)/$*.$(DEPEXT).tmp > $(BUILDDIR)/$*.$(DEPEXT) - @sed -e 's/.*://' -e 's/\\$$//' < $(BUILDDIR)/$*.$(DEPEXT).tmp | fmt -1 | sed -e 's/^ *//' -e 's/$$/:/' >> $(BUILDDIR)/$*.$(DEPEXT) - @rm -f $(BUILDDIR)/$*.$(DEPEXT).tmp - -# convert to hex -$(TARGET).memfile: $(TARGET) - @echo 'Making object dump file.' - riscv64-unknown-elf-objdump -DS $< > $<.objdump - @echo 'Making memory file' - riscv64-unknown-elf-elf2hex --bit-width 64 --input $^ --output $@ - extractFunctionRadix.sh $<.objdump - mkdir -p ../../imperas-riscv-tests/work/rv64BP/ - cp -f $(TARGETDIR)/* ../../imperas-riscv-tests/work/rv64BP/ diff --git a/tests/custom/boot/bios.s b/tests/custom/boot/bios.s deleted file mode 100644 index 9a5d6e21f..000000000 --- a/tests/custom/boot/bios.s +++ /dev/null @@ -1,101 +0,0 @@ -PERIOD = 11000000 -#PERIOD = 20 - -.section .init -.global _start -.type _start, @function - - -_start: - # Initialize global pointer - .option push - .option norelax - 1:auipc gp, %pcrel_hi(__global_pointer$) - addi gp, gp, %pcrel_lo(1b) - .option pop - - li x1, 0 - li x2, 0 - li x4, 0 - li x5, 0 - li x6, 0 - li x7, 0 - li x8, 0 - li x9, 0 - li x10, 0 - li x11, 0 - li x12, 0 - li x13, 0 - li x14, 0 - li x15, 0 - li x16, 0 - li x17, 0 - li x18, 0 - li x19, 0 - li x20, 0 - li x21, 0 - li x22, 0 - li x23, 0 - li x24, 0 - li x25, 0 - li x26, 0 - li x27, 0 - li x28, 0 - li x29, 0 - li x30, 0 - li x31, 0 - - - # set the stack pointer to the top of memory - 8 bytes (pointer size) - li sp, 0x87FFFFF8 - - li a0, 0x00000000 - li a1, 0x80000000 - #li a2, 128*1024*1024/512 # copy 128MB - li a2, 127*1024*1024/512 # copy 127MB upper 1MB contains the return address (ra) - #li a2, 800 # copy 400KB - jal ra, copyFlash - - fence.i - # now toggle led so we know the copy completed. - - # write to gpio - li t2, 0xFF - la t3, 0x1006000C - li t4, 5 - -loop: - - # delay - li t0, PERIOD/2 -delay1: - addi t0, t0, -1 - bge t0, x0, delay1 - sw t2, 0x0(t3) - - li t0, PERIOD/2 -delay2: - addi t0, t0, -1 - bge t0, x0, delay2 - sw x0, 0x0(t3) - - addi t4, t4, -1 - bgt t4, x0, loop - - - # now that the card is copied and the led toggled we - # jump to the copied contents of the sd card. - -jumpToLinux: - csrrs a0, 0xF14, x0 # copy hart ID to a0 - li a1, 0x87000000 # end of memory? not 100% sure on this but it's 112MB - la a2, end_of_bios - li t0, 0x80000000 # start of code - - jalr x0, t0, 0 - -end_of_bios: - - - - diff --git a/tests/custom/boot/boot.c b/tests/custom/boot/boot.c deleted file mode 100644 index 6e4780f55..000000000 --- a/tests/custom/boot/boot.c +++ /dev/null @@ -1,422 +0,0 @@ -#include -#include "boot.h" -#include "gpt.h" - -/* Card type flags (card_type) */ -#define CT_MMC 0x01 /* MMC ver 3 */ -#define CT_SD1 0x02 /* SD ver 1 */ -#define CT_SD2 0x04 /* SD ver 2 */ -#define CT_SDC (CT_SD1|CT_SD2) /* SD */ -#define CT_BLOCK 0x08 /* Block addressing */ - -#define CMD0 (0) /* GO_IDLE_STATE */ -#define CMD1 (1) /* SEND_OP_COND */ -#define CMD2 (2) /* SEND_CID */ -#define CMD3 (3) /* RELATIVE_ADDR */ -#define CMD4 (4) -#define CMD5 (5) /* SLEEP_WAKE (SDC) */ -#define CMD6 (6) /* SWITCH_FUNC */ -#define CMD7 (7) /* SELECT */ -#define CMD8 (8) /* SEND_IF_COND */ -#define CMD9 (9) /* SEND_CSD */ -#define CMD10 (10) /* SEND_CID */ -#define CMD11 (11) -#define CMD12 (12) /* STOP_TRANSMISSION */ -#define CMD13 (13) -#define CMD15 (15) -#define CMD16 (16) /* SET_BLOCKLEN */ -#define CMD17 (17) /* READ_SINGLE_BLOCK */ -#define CMD18 (18) /* READ_MULTIPLE_BLOCK */ -#define CMD19 (19) -#define CMD20 (20) -#define CMD23 (23) -#define CMD24 (24) -#define CMD25 (25) -#define CMD27 (27) -#define CMD28 (28) -#define CMD29 (29) -#define CMD30 (30) -#define CMD32 (32) -#define CMD33 (33) -#define CMD38 (38) -#define CMD42 (42) -#define CMD55 (55) /* APP_CMD */ -#define CMD56 (56) -#define ACMD6 (0x80+6) /* define the data bus width */ -#define ACMD41 (0x80+41) /* SEND_OP_COND (ACMD) */ - -// Capability bits -#define SDC_CAPABILITY_SD_4BIT 0x0001 -#define SDC_CAPABILITY_SD_RESET 0x0002 -#define SDC_CAPABILITY_ADDR 0xff00 - -// Control bits -#define SDC_CONTROL_SD_4BIT 0x0001 -#define SDC_CONTROL_SD_RESET 0x0002 - -// Card detect bits -#define SDC_CARD_INSERT_INT_EN 0x0001 -#define SDC_CARD_INSERT_INT_REQ 0x0002 -#define SDC_CARD_REMOVE_INT_EN 0x0004 -#define SDC_CARD_REMOVE_INT_REQ 0x0008 - -// Command status bits -#define SDC_CMD_INT_STATUS_CC 0x0001 // Command complete -#define SDC_CMD_INT_STATUS_EI 0x0002 // Any error -#define SDC_CMD_INT_STATUS_CTE 0x0004 // Timeout -#define SDC_CMD_INT_STATUS_CCRC 0x0008 // CRC error -#define SDC_CMD_INT_STATUS_CIE 0x0010 // Command code check error - -// Data status bits -#define SDC_DAT_INT_STATUS_TRS 0x0001 // Transfer complete -#define SDC_DAT_INT_STATUS_ERR 0x0002 // Any error -#define SDC_DAT_INT_STATUS_CTE 0x0004 // Timeout -#define SDC_DAT_INT_STATUS_CRC 0x0008 // CRC error -#define SDC_DAT_INT_STATUS_CFE 0x0010 // Data FIFO underrun or overrun - - -#define ERR_EOF 30 -#define ERR_NOT_ELF 31 -#define ERR_ELF_BITS 32 -#define ERR_ELF_ENDIANNESS 33 -#define ERR_CMD_CRC 34 -#define ERR_CMD_CHECK 35 -#define ERR_DATA_CRC 36 -#define ERR_DATA_FIFO 37 -#define ERR_BUF_ALIGNMENT 38 -#define FR_DISK_ERR 39 -#define FR_TIMEOUT 40 - -struct sdc_regs { - volatile uint32_t argument; - volatile uint32_t command; - volatile uint32_t response1; - volatile uint32_t response2; - volatile uint32_t response3; - volatile uint32_t response4; - volatile uint32_t data_timeout; - volatile uint32_t control; - volatile uint32_t cmd_timeout; - volatile uint32_t clock_divider; - volatile uint32_t software_reset; - volatile uint32_t power_control; - volatile uint32_t capability; - volatile uint32_t cmd_int_status; - volatile uint32_t cmd_int_enable; - volatile uint32_t dat_int_status; - volatile uint32_t dat_int_enable; - volatile uint32_t block_size; - volatile uint32_t block_count; - volatile uint32_t card_detect; - volatile uint32_t res_50; - volatile uint32_t res_54; - volatile uint32_t res_58; - volatile uint32_t res_5c; - volatile uint64_t dma_addres; -}; - -#define MAX_BLOCK_CNT 0x1000 - -#define SDC 0x00013000; - -// static struct sdc_regs * const regs __attribute__((section(".rodata"))) = (struct sdc_regs *)0x00013000; - -// static int errno __attribute__((section(".bss"))); -// static DSTATUS drv_status __attribute__((section(".bss"))); -// static BYTE card_type __attribute__((section(".bss"))); -// static uint32_t response[4] __attribute__((section(".bss"))); -// static int alt_mem __attribute__((section(".bss"))); - -/*static const char * errno_to_str(void) { - switch (errno) { - case ERR_EOF: return "Unexpected EOF"; - case ERR_NOT_ELF: return "Not an ELF file"; - case ERR_ELF_BITS: return "Wrong ELF word size"; - case ERR_ELF_ENDIANNESS: return "Wrong ELF endianness"; - case ERR_CMD_CRC: return "Command CRC error"; - case ERR_CMD_CHECK: return "Command code check error"; - case ERR_DATA_CRC: return "Data CRC error"; - case ERR_DATA_FIFO: return "Data FIFO error"; - case ERR_BUF_ALIGNMENT: return "Bad buffer alignment"; - case FR_DISK_ERR: return "Disk error"; - case FR_TIMEOUT: return "Timeout"; - } - return "Unknown error code"; - }*/ - -static void usleep(unsigned us) { - uintptr_t cycles0; - uintptr_t cycles1; - asm volatile ("csrr %0, 0xB00" : "=r" (cycles0)); - for (;;) { - asm volatile ("csrr %0, 0xB00" : "=r" (cycles1)); - if (cycles1 - cycles0 >= us * 100) break; - } -} - -static int sdc_cmd_finish(unsigned cmd, uint32_t * response) { - struct sdc_regs * regs = (struct sdc_regs *)SDC; - - while (1) { - unsigned status = regs->cmd_int_status; - if (status) { - // clear interrupts - regs->cmd_int_status = 0; - while (regs->software_reset != 0) {} - if (status == SDC_CMD_INT_STATUS_CC) { - // get response - response[0] = regs->response1; - response[1] = regs->response2; - response[2] = regs->response3; - response[3] = regs->response4; - return 0; - } - /* errno = FR_DISK_ERR; - if (status & SDC_CMD_INT_STATUS_CTE) errno = FR_TIMEOUT; - if (status & SDC_CMD_INT_STATUS_CCRC) errno = ERR_CMD_CRC; - if (status & SDC_CMD_INT_STATUS_CIE) errno = ERR_CMD_CHECK;*/ - break; - } - } - return -1; -} - -static int sdc_data_finish(void) { - int status; - struct sdc_regs * regs = (struct sdc_regs *)SDC; - - while ((status = regs->dat_int_status) == 0) {} - regs->dat_int_status = 0; - while (regs->software_reset != 0) {} - - if (status == SDC_DAT_INT_STATUS_TRS) return 0; - /* errno = FR_DISK_ERR; - if (status & SDC_DAT_INT_STATUS_CTE) errno = FR_TIMEOUT; - if (status & SDC_DAT_INT_STATUS_CRC) errno = ERR_DATA_CRC; - if (status & SDC_DAT_INT_STATUS_CFE) errno = ERR_DATA_FIFO;*/ - return -1; -} - -static int send_data_cmd(unsigned cmd, unsigned arg, void * buf, unsigned blocks, uint32_t * response) { - struct sdc_regs * regs = (struct sdc_regs *)SDC; - - unsigned command = (cmd & 0x3f) << 8; - switch (cmd) { - case CMD0: - case CMD4: - case CMD15: - // No responce - break; - case CMD11: - case CMD13: - case CMD16: - case CMD17: - case CMD18: - case CMD19: - case CMD23: - case CMD24: - case CMD25: - case CMD27: - case CMD30: - case CMD32: - case CMD33: - case CMD42: - case CMD55: - case CMD56: - case ACMD6: - // R1 - command |= 1; // 48 bits - command |= 1 << 3; // resp CRC - command |= 1 << 4; // resp OPCODE - break; - case CMD7: - case CMD12: - case CMD20: - case CMD28: - case CMD29: - case CMD38: - // R1b - command |= 1; // 48 bits - command |= 1 << 2; // busy - command |= 1 << 3; // resp CRC - command |= 1 << 4; // resp OPCODE - break; - case CMD2: - case CMD9: - case CMD10: - // R2 - command |= 2; // 136 bits - command |= 1 << 3; // resp CRC - break; - case ACMD41: - // R3 - command |= 1; // 48 bits - break; - case CMD3: - // R6 - command |= 1; // 48 bits - command |= 1 << 2; // busy - command |= 1 << 3; // resp CRC - command |= 1 << 4; // resp OPCODE - break; - case CMD8: - // R7 - command |= 1; // 48 bits - command |= 1 << 3; // resp CRC - command |= 1 << 4; // resp OPCODE - break; - } - - if (blocks) { - command |= 1 << 5; - if ((intptr_t)buf & 3) { - // errno = ERR_BUF_ALIGNMENT; - return -1; - } - regs->dma_addres = (uint64_t)(intptr_t)buf; - regs->block_size = 511; - regs->block_count = blocks - 1; - regs->data_timeout = 0x1FFFFFF; - } - - regs->command = command; - regs->cmd_timeout = 0xFFFFF; - regs->argument = arg; - - if (sdc_cmd_finish(cmd, response) < 0) return -1; - if (blocks) return sdc_data_finish(); - - return 0; -} - -#define send_cmd(cmd, arg, response) send_data_cmd(cmd, arg, NULL, 0, response) - -static BYTE ini_sd(void) { - struct sdc_regs * regs = (struct sdc_regs *)SDC; - unsigned rca; - BYTE card_type; - uint32_t response[4]; - - /* Reset controller */ - regs->software_reset = 1; - while ((regs->software_reset & 1) == 0) {} - - // This clock divider is meant to initialize the card at - // 400kHz - - // 22MHz/400kHz = 55 (base 10) = 0x37 - 0x01 = 0x36 - regs->clock_divider = 0x36; - regs->software_reset = 0; - while (regs->software_reset) {} - usleep(5000); - - card_type = 0; - // drv_status = STA_NOINIT; - - if (regs->capability & SDC_CAPABILITY_SD_RESET) { - /* Power cycle SD card */ - regs->control |= SDC_CONTROL_SD_RESET; - usleep(1000000); - regs->control &= ~SDC_CONTROL_SD_RESET; - usleep(100000); - } - - /* Enter Idle state */ - send_cmd(CMD0, 0, response); - - card_type = CT_SD1; - if (send_cmd(CMD8, 0x1AA, response) == 0) { - if ((response[0] & 0xfff) != 0x1AA) { - // errno = ERR_CMD_CHECK; - return -1; - } - card_type = CT_SD2; - } - - /* Wait for leaving idle state (ACMD41 with HCS bit) */ - while (1) { - /* ACMD41, Set Operating Conditions: Host High Capacity & 3.3V */ - if (send_cmd(CMD55, 0, response) < 0 || send_cmd(ACMD41, 0x40300000, response) < 0) return -1; - if (response[0] & (1 << 31)) { - if (response[0] & (1 << 30)) card_type |= CT_BLOCK; - break; - } - } - - /* Enter Identification state */ - if (send_cmd(CMD2, 0, response) < 0) return -1; - - /* Get RCA (Relative Card Address) */ - rca = 0x1234; - if (send_cmd(CMD3, rca << 16, response) < 0) return -1; - rca = response[0] >> 16; - - /* Select card */ - if (send_cmd(CMD7, rca << 16, response) < 0) return -1; - - /* Clock 25MHz */ - // 22Mhz/2 = 11Mhz - regs->clock_divider = 1; - usleep(10000); - - /* Bus width 1-bit */ - regs->control = 0; - if (send_cmd(CMD55, rca << 16, response) < 0 || send_cmd(ACMD6, 0, response) < 0) return -1; - - /* Set R/W block length to 512 */ - if (send_cmd(CMD16, 512, response) < 0) return -1; - - // drv_status &= ~STA_NOINIT; - return card_type; -} - -int disk_read(BYTE * buf, LBA_t sector, UINT count, BYTE card_type) { - - /* This is not needed. This has everything to do with the FAT - filesystem stuff that I'm not including. All I need to do is - initialize the SD card and read from it. Anything in here that is - checking for potential errors, I'm going to have to temporarily - do without. - */ - // if (!count) return RES_PARERR; - /* if (drv_status & STA_NOINIT) return RES_NOTRDY; */ - - uint32_t response[4]; - struct sdc_regs * regs = (struct sdc_regs *)SDC; - - /* Convert LBA to byte address if needed */ - if (!(card_type & CT_BLOCK)) sector *= 512; - while (count > 0) { - UINT bcnt = count > MAX_BLOCK_CNT ? MAX_BLOCK_CNT : count; - unsigned bytes = bcnt * 512; - if (send_data_cmd(bcnt == 1 ? CMD17 : CMD18, sector, buf, bcnt, response) < 0) return 1; - if (bcnt > 1 && send_cmd(CMD12, 0, response) < 0) return 1; - sector += (card_type & CT_BLOCK) ? bcnt : bytes; - count -= bcnt; - buf += bytes; - } - - return 0;; -} - -void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) { - BYTE card_type; - int ret = 0; - - card_type = ini_sd(); - - // BYTE * buf = (BYTE *)Dst; - - // if (disk_read(buf, (LBA_t)address, (UINT)numBlocks, card_type) < 0) /* UART Print function?*/; - - ret = gpt_load_partitions(card_type); -} - -/* -int main() { - ini_sd(); - - - return 0; -} -*/ diff --git a/tests/custom/boot/boot.h b/tests/custom/boot/boot.h deleted file mode 100644 index 77d403145..000000000 --- a/tests/custom/boot/boot.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef WALLYBOOT -#define WALLYBOOT 10000 - -#include -typedef unsigned int UINT; /* int must be 16-bit or 32-bit */ -typedef unsigned char BYTE; /* char must be 8-bit */ -typedef uint16_t WORD; /* 16-bit unsigned integer */ -typedef uint32_t DWORD; /* 32-bit unsigned integer */ -typedef uint64_t QWORD; /* 64-bit unsigned integer */ -typedef WORD WCHAR; - -typedef QWORD LBA_t; - -// Define memory locations of boot images ===================== -// These locations are copied from the generic configuration -// of OpenSBI. These addresses can be found in: -// buildroot/output/build/opensbi-0.9/platform/generic/config.mk -#define FDT_ADDRESS 0x87000000 // FW_JUMP_FDT_ADDR -#define OPENSBI_ADDRESS 0x80000000 // FW_TEXT_START -#define KERNEL_ADDRESS 0x80200000 // FW_JUMP_ADDR - -// Export disk_read -int disk_read(BYTE * buf, LBA_t sector, UINT count, BYTE card_type); - -#endif // WALLYBOOT - diff --git a/tests/custom/boot/gpt.c b/tests/custom/boot/gpt.c deleted file mode 100644 index 97e3e4e46..000000000 --- a/tests/custom/boot/gpt.c +++ /dev/null @@ -1,46 +0,0 @@ -#include "gpt.h" -#include "boot.h" -#include - -/* PSUEDOCODE - - Need to load GPT LBA 1 and read through the partition entries. - I need to find each of the relevant partition entries, possibly - by their partition names. - -*/ - -int gpt_load_partitions(BYTE card_type) { - // In this version of the GPT partition code - // I'm going to assume that the SD card is already initialized. - - // size_t block_size = 512/8; - // long int lba1_buf[block_size]; - - BYTE lba1_buf[512]; - - int ret = 0; - //ret = disk_read(/* BYTE * buf, LBA_t sector, UINT count, BYTE card_type */); - ret = disk_read(lba1_buf, 1, 1, card_type); - - /* Possible error handling with UART message - if ( ret != 0 ) { - - }*/ - - gpt_pth_t *lba1 = (gpt_pth_t *)lba1_buf; - - BYTE lba2_buf[512]; - ret = disk_read(lba2_buf, (LBA_t)lba1->partition_entries_lba, 1, card_type); - - // Load parition entries for the relevant boot partitions. - partition_entries_t *fdt = (partition_entries_t *)(lba2_buf); - partition_entries_t *opensbi = (partition_entries_t *)(lba2_buf + 128); - partition_entries_t *kernel = (partition_entries_t *)(lba2_buf + 256); - - ret = disk_read((BYTE *)FDT_ADDRESS, fdt->first_lba, fdt->last_lba - fdt->first_lba + 1, card_type); - ret = disk_read((BYTE *)OPENSBI_ADDRESS, opensbi->first_lba, opensbi->last_lba - opensbi->first_lba + 1, card_type); - ret = disk_read((BYTE *)KERNEL_ADDRESS, kernel->first_lba,kernel->last_lba - kernel->first_lba + 1, card_type); - - return 0; -} diff --git a/tests/custom/boot/gpt.h b/tests/custom/boot/gpt.h deleted file mode 100644 index 4aefae229..000000000 --- a/tests/custom/boot/gpt.h +++ /dev/null @@ -1,40 +0,0 @@ -#pragma once - -#include -#include "boot.h" - -// LBA 0: Protective MBR -// ignored here - -// Partition Table Header (LBA 1) -typedef struct gpt_pth -{ - uint64_t signature; - uint32_t revision; - uint32_t header_size; //! little endian, usually 0x5c = 92 - uint32_t crc_header; - uint32_t reserved; //! must be 0 - uint64_t current_lba; - uint64_t backup_lba; - uint64_t first_usable_lba; - uint64_t last_usable_lba; - uint8_t disk_guid[16]; - uint64_t partition_entries_lba; - uint32_t nr_partition_entries; - uint32_t size_partition_entry; //! usually 0x80 = 128 - uint32_t crc_partition_entry; -} gpt_pth_t; - -// Partition Entries (LBA 2-33) -typedef struct partition_entries -{ - uint8_t partition_type_guid[16]; - uint8_t partition_guid[16]; - uint64_t first_lba; - uint64_t last_lba; //! inclusive - uint64_t attributes; - uint8_t name[72]; //! utf16 encoded -} partition_entries_t; - -// Find boot partition and load it to the destination -int gpt_load_partitions(BYTE card_type); diff --git a/tests/custom/cacheTest/Makefile b/tests/custom/cacheTest/Makefile deleted file mode 100644 index 393cfd0ec..000000000 --- a/tests/custom/cacheTest/Makefile +++ /dev/null @@ -1,19 +0,0 @@ -TARGETDIR := cacheTest -TARGET := $(TARGETDIR)/$(TARGETDIR).elf -ROOT := .. -LIBRARY_DIRS := ${ROOT}/crt0 -LIBRARY_FILES := crt0 - -MARCH :=-march=rv64imfdc -MABI :=-mabi=lp64d -LINKER := ${ROOT}/linker8000-0000.x -LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map -L $(RISCV)/riscv64-unknown-elf/lib - -CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany -mstrict-align -O2 -CC=riscv64-unknown-elf-gcc -DA=riscv64-unknown-elf-objdump -d - - -include $(ROOT)/makefile.inc - - diff --git a/tests/custom/cacheTest/header.h b/tests/custom/cacheTest/header.h deleted file mode 100644 index aab8973fd..000000000 --- a/tests/custom/cacheTest/header.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef __header -#define __header - -int fail(); -int simple_csrbr_test(); -int lbu_test(); -int icache_spill_test(); -void global_hist_0_space_test(); -void global_hist_1_space_test(); -void global_hist_2_space_test(); -void global_hist_3_space_test(); -#endif diff --git a/tests/custom/cacheTest/main.c b/tests/custom/cacheTest/main.c deleted file mode 100644 index fccdaf0ed..000000000 --- a/tests/custom/cacheTest/main.c +++ /dev/null @@ -1,12 +0,0 @@ -#include "header.h" - -#define LIMIT 8192 -int main(int argc, char *argv[]){ - long int array [LIMIT]; - int index; - for(index = 0; index < LIMIT; index++) { - array[index] = index; - } - *argv = array; - return array[LIMIT-1] + argc; -} diff --git a/tests/custom/fpga-blink-led/Makefile b/tests/custom/fpga-blink-led/Makefile deleted file mode 100644 index 8bfbe000b..000000000 --- a/tests/custom/fpga-blink-led/Makefile +++ /dev/null @@ -1,112 +0,0 @@ -CEXT := c -CPPEXT := cpp -AEXT := s -SEXT := S -SRCEXT := \([$(CEXT)$(AEXT)$(SEXT)]\|$(CPPEXT)\) -OBJEXT := o -DEPEXT := d -SRCDIR := . -BUILDDIR := OBJ - -SOURCES ?= $(shell find $(SRCDIR) -type f -regex ".*\.$(SRCEXT)" | sort) -OBJECTS := $(SOURCES:.$(CEXT)=.$(OBJEXT)) -OBJECTS := $(OBJECTS:.$(AEXT)=.$(OBJEXT)) -OBJECTS := $(OBJECTS:.$(SEXT)=.$(OBJEXT)) -OBJECTS := $(OBJECTS:.$(CPPEXT)=.$(OBJEXT)) -OBJECTS := $(patsubst $(SRCDIR)/%,$(BUILDDIR)/%,$(OBJECTS)) - -TARGETDIR := bin -TARGET := $(TARGETDIR)/blink-led -ROOT := .. -LIBRARY_DIRS := -LIBRARY_FILES := - -MARCH :=-march=rv64imfdc -MABI :=-mabi=lp64d -LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -L $(RISCV)/riscv64-unknown-elf/lib -LINKER :=$(ROOT)/linker1000.x - - -AFLAGS =$(MARCH) $(MABI) -W -CFLAGS =$(MARCH) $(MABI) -mcmodel=medany -O2 -AS=riscv64-unknown-elf-as -CC=riscv64-unknown-elf-gcc -AR=riscv64-unknown-elf-ar - - -#Default Make -all: directories $(TARGET).memfile - -#Remake -remake: clean all - -#Make the Directories -directories: - @mkdir -p $(TARGETDIR) - @mkdir -p $(BUILDDIR) - -clean: - rm -rf $(BUILDDIR) $(TARGETDIR) *.memfile *.objdump - - -#Needed for building additional library projects -ifdef LIBRARY_DIRS -LIBS+=${LIBRARY_DIRS:%=-L%} ${LIBRARY_FILES:%=-l%} -INC+=${LIBRARY_DIRS:%=-I%} - -${LIBRARY_DIRS}: - $(MAKE) -C $@ -j 1 - -.PHONY: $(LIBRARY_DIRS) $(TARGET) -endif - - -#Pull in dependency info for *existing* .o files --include $(OBJECTS:.$(OBJEXT)=.$(DEPEXT)) - -#Link -$(TARGET): $(OBJECTS) $(LIBRARY_DIRS) - $(CC) $(LINK_FLAGS) -g -o $(TARGET) $(OBJECTS) ${LIBS} -T ${LINKER} - - -#Compile -$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(CEXT) - @mkdir -p $(dir $@) - $(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list - @$(CC) $(CFLAGS) $(INC) -MM $(SRCDIR)/$*.$(CEXT) > $(BUILDDIR)/$*.$(DEPEXT) - @cp -f $(BUILDDIR)/$*.$(DEPEXT) $(BUILDDIR)/$*.$(DEPEXT).tmp - @sed -e 's|.*:|$(BUILDDIR)/$*.$(OBJEXT):|' < $(BUILDDIR)/$*.$(DEPEXT).tmp > $(BUILDDIR)/$*.$(DEPEXT) - @sed -e 's/.*://' -e 's/\\$$//' < $(BUILDDIR)/$*.$(DEPEXT).tmp | fmt -1 | sed -e 's/^ *//' -e 's/$$/:/' >> $(BUILDDIR)/$*.$(DEPEXT) - @rm -f $(BUILDDIR)/$*.$(DEPEXT).tmp - -# gcc won't output dependencies for assembly files for some reason -# most asm files don't have dependencies so the echo will work for now. -$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(AEXT) - @mkdir -p $(dir $@) - $(CC) $(CFLAGS) -c -o $@ $< > $(BUILDDIR)/$*.list - @echo $@: $< > $(BUILDDIR)/$*.$(DEPEXT) - -$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(SEXT) - @mkdir -p $(dir $@) - $(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list - @echo $@: $< > $(BUILDDIR)/$*.$(DEPEXT) - -# C++ -$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(CPPEXT) - @mkdir -p $(dir $@) - $(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list - @$(CC) $(CFLAGS) $(INC) -MM $(SRCDIR)/$*.$(CPPEXT) > $(BUILDDIR)/$*.$(DEPEXT) - @cp -f $(BUILDDIR)/$*.$(DEPEXT) $(BUILDDIR)/$*.$(DEPEXT).tmp - @sed -e 's|.*:|$(BUILDDIR)/$*.$(OBJEXT):|' < $(BUILDDIR)/$*.$(DEPEXT).tmp > $(BUILDDIR)/$*.$(DEPEXT) - @sed -e 's/.*://' -e 's/\\$$//' < $(BUILDDIR)/$*.$(DEPEXT).tmp | fmt -1 | sed -e 's/^ *//' -e 's/$$/:/' >> $(BUILDDIR)/$*.$(DEPEXT) - @rm -f $(BUILDDIR)/$*.$(DEPEXT).tmp - -# convert to hex -$(TARGET).memfile: $(TARGET) - @echo 'Making object dump file.' - @riscv64-unknown-elf-objdump -D $< > $<.objdump - @echo 'Making memory file' - exe2memfile0.pl $< - extractFunctionRadix.sh $<.objdump - mkdir -p ../../imperas-riscv-tests/work/rv64BP/ - cp -f $(TARGETDIR)/* ../../imperas-riscv-tests/work/rv64BP/ diff --git a/tests/custom/fpga-blink-led/blink-led.s b/tests/custom/fpga-blink-led/blink-led.s deleted file mode 100644 index 5d4d48ceb..000000000 --- a/tests/custom/fpga-blink-led/blink-led.s +++ /dev/null @@ -1,86 +0,0 @@ -PERIOD = 22000000 -#PERIOD = 100 - -.section .init -.global _start -.type _start, @function - - -_start: - # Initialize global pointer - .option push - .option norelax - 1:auipc gp, %pcrel_hi(__global_pointer$) - addi gp, gp, %pcrel_lo(1b) - .option pop - - li x1, 0 - li x2, 0 - li x4, 0 - li x5, 0 - li x6, 0 - li x7, 0 - li x8, 0 - li x9, 0 - li x10, 0 - li x11, 0 - li x12, 0 - li x13, 0 - li x14, 0 - li x15, 0 - li x16, 0 - li x17, 0 - li x18, 0 - li x19, 0 - li x20, 0 - li x21, 0 - li x22, 0 - li x23, 0 - li x24, 0 - li x25, 0 - li x26, 0 - li x27, 0 - li x28, 0 - li x29, 0 - li x30, 0 - li x31, 0 - - # write to gpio - li x2, 0xFF - la x3, 0x10060000 - - # +8 is output enable - # +C is output value - - addi x4, x3, 8 - addi x5, x3, 0xC - - # write initial value of 0xFF to GPO - sw x2, 0x0(x5) - # enable output - sw x2, 0x0(x4) - -loop: - - # delay - li x20, PERIOD/2 -delay1: - addi x20, x20, -1 - bge x20, x0, delay1 - - # clear GPO - sw x0, 0x0(x5) - - # delay - li x20, PERIOD/2 -delay2: - addi x20, x20, -1 - bge x20, x0, delay2 - - # write GPO - sw x2, 0x0(x5) - - j loop - - - diff --git a/tests/custom/fpga-test-dram/Makefile b/tests/custom/fpga-test-dram/Makefile deleted file mode 100644 index 8bfbe000b..000000000 --- a/tests/custom/fpga-test-dram/Makefile +++ /dev/null @@ -1,112 +0,0 @@ -CEXT := c -CPPEXT := cpp -AEXT := s -SEXT := S -SRCEXT := \([$(CEXT)$(AEXT)$(SEXT)]\|$(CPPEXT)\) -OBJEXT := o -DEPEXT := d -SRCDIR := . -BUILDDIR := OBJ - -SOURCES ?= $(shell find $(SRCDIR) -type f -regex ".*\.$(SRCEXT)" | sort) -OBJECTS := $(SOURCES:.$(CEXT)=.$(OBJEXT)) -OBJECTS := $(OBJECTS:.$(AEXT)=.$(OBJEXT)) -OBJECTS := $(OBJECTS:.$(SEXT)=.$(OBJEXT)) -OBJECTS := $(OBJECTS:.$(CPPEXT)=.$(OBJEXT)) -OBJECTS := $(patsubst $(SRCDIR)/%,$(BUILDDIR)/%,$(OBJECTS)) - -TARGETDIR := bin -TARGET := $(TARGETDIR)/blink-led -ROOT := .. -LIBRARY_DIRS := -LIBRARY_FILES := - -MARCH :=-march=rv64imfdc -MABI :=-mabi=lp64d -LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -L $(RISCV)/riscv64-unknown-elf/lib -LINKER :=$(ROOT)/linker1000.x - - -AFLAGS =$(MARCH) $(MABI) -W -CFLAGS =$(MARCH) $(MABI) -mcmodel=medany -O2 -AS=riscv64-unknown-elf-as -CC=riscv64-unknown-elf-gcc -AR=riscv64-unknown-elf-ar - - -#Default Make -all: directories $(TARGET).memfile - -#Remake -remake: clean all - -#Make the Directories -directories: - @mkdir -p $(TARGETDIR) - @mkdir -p $(BUILDDIR) - -clean: - rm -rf $(BUILDDIR) $(TARGETDIR) *.memfile *.objdump - - -#Needed for building additional library projects -ifdef LIBRARY_DIRS -LIBS+=${LIBRARY_DIRS:%=-L%} ${LIBRARY_FILES:%=-l%} -INC+=${LIBRARY_DIRS:%=-I%} - -${LIBRARY_DIRS}: - $(MAKE) -C $@ -j 1 - -.PHONY: $(LIBRARY_DIRS) $(TARGET) -endif - - -#Pull in dependency info for *existing* .o files --include $(OBJECTS:.$(OBJEXT)=.$(DEPEXT)) - -#Link -$(TARGET): $(OBJECTS) $(LIBRARY_DIRS) - $(CC) $(LINK_FLAGS) -g -o $(TARGET) $(OBJECTS) ${LIBS} -T ${LINKER} - - -#Compile -$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(CEXT) - @mkdir -p $(dir $@) - $(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list - @$(CC) $(CFLAGS) $(INC) -MM $(SRCDIR)/$*.$(CEXT) > $(BUILDDIR)/$*.$(DEPEXT) - @cp -f $(BUILDDIR)/$*.$(DEPEXT) $(BUILDDIR)/$*.$(DEPEXT).tmp - @sed -e 's|.*:|$(BUILDDIR)/$*.$(OBJEXT):|' < $(BUILDDIR)/$*.$(DEPEXT).tmp > $(BUILDDIR)/$*.$(DEPEXT) - @sed -e 's/.*://' -e 's/\\$$//' < $(BUILDDIR)/$*.$(DEPEXT).tmp | fmt -1 | sed -e 's/^ *//' -e 's/$$/:/' >> $(BUILDDIR)/$*.$(DEPEXT) - @rm -f $(BUILDDIR)/$*.$(DEPEXT).tmp - -# gcc won't output dependencies for assembly files for some reason -# most asm files don't have dependencies so the echo will work for now. -$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(AEXT) - @mkdir -p $(dir $@) - $(CC) $(CFLAGS) -c -o $@ $< > $(BUILDDIR)/$*.list - @echo $@: $< > $(BUILDDIR)/$*.$(DEPEXT) - -$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(SEXT) - @mkdir -p $(dir $@) - $(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list - @echo $@: $< > $(BUILDDIR)/$*.$(DEPEXT) - -# C++ -$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(CPPEXT) - @mkdir -p $(dir $@) - $(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list - @$(CC) $(CFLAGS) $(INC) -MM $(SRCDIR)/$*.$(CPPEXT) > $(BUILDDIR)/$*.$(DEPEXT) - @cp -f $(BUILDDIR)/$*.$(DEPEXT) $(BUILDDIR)/$*.$(DEPEXT).tmp - @sed -e 's|.*:|$(BUILDDIR)/$*.$(OBJEXT):|' < $(BUILDDIR)/$*.$(DEPEXT).tmp > $(BUILDDIR)/$*.$(DEPEXT) - @sed -e 's/.*://' -e 's/\\$$//' < $(BUILDDIR)/$*.$(DEPEXT).tmp | fmt -1 | sed -e 's/^ *//' -e 's/$$/:/' >> $(BUILDDIR)/$*.$(DEPEXT) - @rm -f $(BUILDDIR)/$*.$(DEPEXT).tmp - -# convert to hex -$(TARGET).memfile: $(TARGET) - @echo 'Making object dump file.' - @riscv64-unknown-elf-objdump -D $< > $<.objdump - @echo 'Making memory file' - exe2memfile0.pl $< - extractFunctionRadix.sh $<.objdump - mkdir -p ../../imperas-riscv-tests/work/rv64BP/ - cp -f $(TARGETDIR)/* ../../imperas-riscv-tests/work/rv64BP/ diff --git a/tests/custom/fpga-test-dram/blink-led.s b/tests/custom/fpga-test-dram/blink-led.s deleted file mode 100644 index 9e524b2e1..000000000 --- a/tests/custom/fpga-test-dram/blink-led.s +++ /dev/null @@ -1,130 +0,0 @@ -PERIOD = 22000000 -#PERIOD = 100 - -.section .init -.global _start -.type _start, @function - - -_start: - # Initialize global pointer - .option push - .option norelax - 1:auipc gp, %pcrel_hi(__global_pointer$) - addi gp, gp, %pcrel_lo(1b) - .option pop - - li x1, 0 - li x2, 0 - li x4, 0 - li x5, 0 - li x6, 0 - li x7, 0 - li x8, 0 - li x9, 0 - li x10, 0 - li x11, 0 - li x12, 0 - li x13, 0 - li x14, 0 - li x15, 0 - li x16, 0 - li x17, 0 - li x18, 0 - li x19, 0 - li x20, 0 - li x21, 0 - li x22, 0 - li x23, 0 - li x24, 0 - li x25, 0 - li x26, 0 - li x27, 0 - li x28, 0 - li x29, 0 - li x30, 0 - li x31, 0 - - # write to gpio - li x2, 0xFF - la x3, 0x10060000 - - # +8 is output enable - # +C is output value - - addi x4, x3, 8 - addi x5, x3, 0xC - - # write initial value of 0xFF to GPO - sw x2, 0x0(x5) - # enable output - sw x2, 0x0(x4) - - # before jumping to led loop - # lets try writting to dram. - - li x21, 0 - li x23, 4096*16 # 64KB of data - - li x22, 0x80000000 - li x24, 0 - -write_loop: - add x25, x22, x24 - sw x24, 0(x25) - addi x24, x24, 4 - blt x24, x23, write_loop - - li x24, 0 -read_loop: - add x25, x22, x24 - lw x21, 0(x25) - - # check value - bne x21, x24, fail_loop - - addi x24, x24, 4 - - # - blt x24, x23, read_loop - - - -loop: - - # delay - li x20, PERIOD -delay1: - addi x20, x20, -1 - bge x20, x0, delay1 - - # new GPO - addi x2, x2, 1 - sw x2, 0x0(x5) - - j loop - - -fail_loop: - - # delay - li x20, PERIOD/20 -fail_delay1: - addi x20, x20, -1 - bge x20, x0, fail_delay1 - - # clear GPO - sw x0, 0x0(x5) - - # delay - li x20, PERIOD/20 -fail_delay2: - addi x20, x20, -1 - bge x20, x0, fail_delay2 - - # write GPO - sw x2, 0x0(x5) - - j fail_loop - - diff --git a/tests/custom/fpga-test-sdc/Makefile b/tests/custom/fpga-test-sdc/Makefile deleted file mode 100644 index 42d227692..000000000 --- a/tests/custom/fpga-test-sdc/Makefile +++ /dev/null @@ -1,112 +0,0 @@ -CEXT := c -CPPEXT := cpp -AEXT := s -SEXT := S -SRCEXT := \([$(CEXT)$(AEXT)$(SEXT)]\|$(CPPEXT)\) -OBJEXT := o -DEPEXT := d -SRCDIR := . -BUILDDIR := OBJ - -SOURCES ?= $(shell find $(SRCDIR) -type f -regex ".*\.$(SRCEXT)" | sort) -OBJECTS := $(SOURCES:.$(CEXT)=.$(OBJEXT)) -OBJECTS := $(OBJECTS:.$(AEXT)=.$(OBJEXT)) -OBJECTS := $(OBJECTS:.$(SEXT)=.$(OBJEXT)) -OBJECTS := $(OBJECTS:.$(CPPEXT)=.$(OBJEXT)) -OBJECTS := $(patsubst $(SRCDIR)/%,$(BUILDDIR)/%,$(OBJECTS)) - -TARGETDIR := bin -TARGET := $(TARGETDIR)/fpga-test-sdc -ROOT := .. -LIBRARY_DIRS := -LIBRARY_FILES := - -MARCH :=-march=rv64imfdc -MABI :=-mabi=lp64d -LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -L $(RISCV)/riscv64-unknown-elf/lib -LINKER :=$(ROOT)/linker1000.x - - -AFLAGS =$(MARCH) $(MABI) -W -CFLAGS =$(MARCH) $(MABI) -mcmodel=medany -O2 -AS=riscv64-unknown-elf-as -CC=riscv64-unknown-elf-gcc -AR=riscv64-unknown-elf-ar - - -#Default Make -all: directories $(TARGET).memfile - -#Remake -remake: clean all - -#Make the Directories -directories: - @mkdir -p $(TARGETDIR) - @mkdir -p $(BUILDDIR) - -clean: - rm -rf $(BUILDDIR) $(TARGETDIR) *.memfile *.objdump - - -#Needed for building additional library projects -ifdef LIBRARY_DIRS -LIBS+=${LIBRARY_DIRS:%=-L%} ${LIBRARY_FILES:%=-l%} -INC+=${LIBRARY_DIRS:%=-I%} - -${LIBRARY_DIRS}: - $(MAKE) -C $@ -j 1 - -.PHONY: $(LIBRARY_DIRS) $(TARGET) -endif - - -#Pull in dependency info for *existing* .o files --include $(OBJECTS:.$(OBJEXT)=.$(DEPEXT)) - -#Link -$(TARGET): $(OBJECTS) $(LIBRARY_DIRS) - $(CC) $(LINK_FLAGS) -g -o $(TARGET) $(OBJECTS) ${LIBS} -T ${LINKER} - - -#Compile -$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(CEXT) - @mkdir -p $(dir $@) - $(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list - @$(CC) $(CFLAGS) $(INC) -MM $(SRCDIR)/$*.$(CEXT) > $(BUILDDIR)/$*.$(DEPEXT) - @cp -f $(BUILDDIR)/$*.$(DEPEXT) $(BUILDDIR)/$*.$(DEPEXT).tmp - @sed -e 's|.*:|$(BUILDDIR)/$*.$(OBJEXT):|' < $(BUILDDIR)/$*.$(DEPEXT).tmp > $(BUILDDIR)/$*.$(DEPEXT) - @sed -e 's/.*://' -e 's/\\$$//' < $(BUILDDIR)/$*.$(DEPEXT).tmp | fmt -1 | sed -e 's/^ *//' -e 's/$$/:/' >> $(BUILDDIR)/$*.$(DEPEXT) - @rm -f $(BUILDDIR)/$*.$(DEPEXT).tmp - -# gcc won't output dependencies for assembly files for some reason -# most asm files don't have dependencies so the echo will work for now. -$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(AEXT) - @mkdir -p $(dir $@) - $(CC) $(CFLAGS) -c -o $@ $< > $(BUILDDIR)/$*.list - @echo $@: $< > $(BUILDDIR)/$*.$(DEPEXT) - -$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(SEXT) - @mkdir -p $(dir $@) - $(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list - @echo $@: $< > $(BUILDDIR)/$*.$(DEPEXT) - -# C++ -$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(CPPEXT) - @mkdir -p $(dir $@) - $(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list - @$(CC) $(CFLAGS) $(INC) -MM $(SRCDIR)/$*.$(CPPEXT) > $(BUILDDIR)/$*.$(DEPEXT) - @cp -f $(BUILDDIR)/$*.$(DEPEXT) $(BUILDDIR)/$*.$(DEPEXT).tmp - @sed -e 's|.*:|$(BUILDDIR)/$*.$(OBJEXT):|' < $(BUILDDIR)/$*.$(DEPEXT).tmp > $(BUILDDIR)/$*.$(DEPEXT) - @sed -e 's/.*://' -e 's/\\$$//' < $(BUILDDIR)/$*.$(DEPEXT).tmp | fmt -1 | sed -e 's/^ *//' -e 's/$$/:/' >> $(BUILDDIR)/$*.$(DEPEXT) - @rm -f $(BUILDDIR)/$*.$(DEPEXT).tmp - -# convert to hex -$(TARGET).memfile: $(TARGET) - @echo 'Making object dump file.' - @riscv64-unknown-elf-objdump -D $< > $<.objdump - @echo 'Making memory file' - riscv64-unknown-elf-elf2hex --bit-width 64 --input $^ --output $@ - extractFunctionRadix.sh $<.objdump - mkdir -p ../work/ - cp -f $(TARGETDIR)/* ../work/ diff --git a/tests/custom/fpga-test-sdc/bios.s b/tests/custom/fpga-test-sdc/bios.s deleted file mode 100644 index 8057a277d..000000000 --- a/tests/custom/fpga-test-sdc/bios.s +++ /dev/null @@ -1,101 +0,0 @@ -PERIOD = 11000000 -#PERIOD = 20 - -.section .init -.global _start -.type _start, @function - - -_start: - # Initialize global pointer - .option push - .option norelax - 1:auipc gp, %pcrel_hi(__global_pointer$) - addi gp, gp, %pcrel_lo(1b) - .option pop - - li x1, 0 - li x2, 0 - li x4, 0 - li x5, 0 - li x6, 0 - li x7, 0 - li x8, 0 - li x9, 0 - li x10, 0 - li x11, 0 - li x12, 0 - li x13, 0 - li x14, 0 - li x15, 0 - li x16, 0 - li x17, 0 - li x18, 0 - li x19, 0 - li x20, 0 - li x21, 0 - li x22, 0 - li x23, 0 - li x24, 0 - li x25, 0 - li x26, 0 - li x27, 0 - li x28, 0 - li x29, 0 - li x30, 0 - li x31, 0 - - - # set the stack pointer to the top of memory - 8 bytes (pointer size) - li sp, 0x87FFFFF8 - - li a0, 0x00000000 - li a1, 0x80000000 - #li a2, 128*1024*1024/512 # copy 128MB - li a2, 127*1024*1024/512 # copy 127MB upper 1MB contains the return address (ra) - #li a2, 800 # copy 400KB - jal ra, copyFlash - - fence.i - # now toggle led so we know the copy completed. - - # write to gpio - li t2, 0xFF - la t3, 0x1006000C - li t4, 5 - -loop: - - # delay - li t0, PERIOD/2 -delay1: - addi t0, t0, -1 - bge t0, x0, delay1 - sw t2, 0x0(t3) - - li t0, PERIOD/2 -delay2: - addi t0, t0, -1 - bge t0, x0, delay2 - sw x0, 0x0(t3) - - addi t4, t4, -1 - bgt t4, x0, loop - - - # now that the card is copied and the led toggled we - # jump to the copied contents of the sd card. - -jumpToLinux: - csrrs a0, 0xF14, x0 # copy hard ID to a0 - li a1, 0x87000000 # end of memory? not 100% sure on this but it's 112MB - la a2, end_of_bios - li t0, 0x80000000 # start of code - - jalr x0, t0, 0 - -end_of_bios: - - - - diff --git a/tests/custom/fpga-test-sdc/copyFlash.c b/tests/custom/fpga-test-sdc/copyFlash.c deleted file mode 100644 index b78653779..000000000 --- a/tests/custom/fpga-test-sdc/copyFlash.c +++ /dev/null @@ -1,40 +0,0 @@ -/////////////////////////////////////////// -// copyFlash.sv -// -// Written: Rose Thompson September 25, 2021 -// Modified: -// -// Purpose: copies flash card into memory -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// - -#include "sdcDriver.h" - -void copyFlash(long int blockAddr, long int * Dst, int numBlocks) { - - setSDCCLK(4); // must be even, 1 gives no division. - waitInitSDC(); - - int index; - - for(index = 0; index < numBlocks; index++) { - copySDC512(blockAddr+(index*512), Dst+(index*512/8)); - } - - -} diff --git a/tests/custom/fpga-test-sdc/old.asm b/tests/custom/fpga-test-sdc/old.asm deleted file mode 100644 index 6137fae7e..000000000 --- a/tests/custom/fpga-test-sdc/old.asm +++ /dev/null @@ -1,154 +0,0 @@ - # start by writting the clock divider to 4 setting SDC to 25MHz - la x3, 0x12100 - li x4, -4 - sw x4, 0x0(x3) - - # start by writting the clock divider to 1 setting SDC to 100MHZ - la x3, 0x12100 - li x4, 1 - sw x4, 0x0(x3) - - - # wait until the SDC is done with initialization - li x4, 0x1 -wait_sdc_done_init: - lw x5, 4(x3) - and x5, x5, x4 - bne x5, x4, wait_sdc_done_init - - # now that it is done lets setup for a read - li x6, 0x20000000 - sd x6, 0x10(x3) # write address register - - # send read by writting to command register - li x7, 0x4 - sw x7, 0x8(x3) - - li x4, 0x2 -wait_sdc_done_read: - lw x5, 4(x3) - and x5, x5, x4 - beq x5, x4, wait_sdc_done_read - - # copy data from mailbox - li x11, 0x80000000 - li x9, 0 -copy_sdc: - li x8, 512/8 - ld x10, 0x18(x3) # read the mailbox - sd x10, 0x0(x11) # write to dram - addi x9, x9, 1 - addi x11, x11, 8 - blt x9, x8, copy_sdc - - # second read of sdc - # now that it is done lets setup for a read - li x6, 0x20000200 - sd x6, 0x10(x3) # write address register - - # send read by writting to command register - li x7, 0x4 - sw x7, 0x8(x3) - - li x4, 0x2 -wait_sdc_done_read2: - lw x5, 4(x3) - and x5, x5, x4 - beq x5, x4, wait_sdc_done_read2 - - # copy data from mailbox - li x11, 0x80000200 - li x9, 0 -copy_sdc2: - li x8, 512/8 - ld x10, 0x18(x3) # read the mailbox - sd x10, 0x0(x11) # write to dram - addi x9, x9, 1 - addi x11, x11, 8 - blt x9, x8, copy_sdc2 - - - - # write to gpio - li x2, 0xFF - la x3, 0x10060000 - - # +8 is output enable - # +C is output value - - addi x4, x3, 8 - addi x5, x3, 0xC - - # write initial value of 0xFF to GPO - sw x2, 0x0(x5) - # enable output - sw x2, 0x0(x4) - - # before jumping to led loop - # lets try writting to dram. - - li x21, 0 - li x23, 4096*16 # 64KB of data - - li x22, 0x80000000 - li x24, 0 - -write_loop: - add x25, x22, x24 - sw x24, 0(x25) - addi x24, x24, 4 - blt x24, x23, write_loop - - li x24, 0 -read_loop: - add x25, x22, x24 - lw x21, 0(x25) - - # check value - bne x21, x24, fail_loop - - addi x24, x24, 4 - - # - blt x24, x23, read_loop - - - -loop: - - # delay - li x20, PERIOD -delay1: - addi x20, x20, -1 - bge x20, x0, delay1 - - # new GPO - addi x2, x2, 1 - sw x2, 0x0(x5) - - j loop - - -fail_loop: - - # delay - li x20, PERIOD/20 -fail_delay1: - addi x20, x20, -1 - bge x20, x0, fail_delay1 - - # clear GPO - sw x0, 0x0(x5) - - # delay - li x20, PERIOD/20 -fail_delay2: - addi x20, x20, -1 - bge x20, x0, fail_delay2 - - # write GPO - sw x2, 0x0(x5) - - j fail_loop - - diff --git a/tests/custom/fpga-test-sdc/sdcDriver.c b/tests/custom/fpga-test-sdc/sdcDriver.c deleted file mode 100644 index 45caa42fa..000000000 --- a/tests/custom/fpga-test-sdc/sdcDriver.c +++ /dev/null @@ -1,69 +0,0 @@ -/////////////////////////////////////////// -// SDC.sv -// -// Written: Rose Thompson September 25, 2021 -// Modified: -// -// Purpose: driver for sdc reader. -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// - - -#include "sdcDriver.h" - -#define SDC_MAIL_BOX 0x12100 - -void copySDC512(long int blockAddr, long int * Dst) { - - waitInitSDC(); - - volatile long int * mailBoxAddr; - volatile int * mailBoxCmd; - volatile int * mailBoxStatus; - volatile long int * mailBoxReadData; - mailBoxStatus = (int *) (SDC_MAIL_BOX + 0x4); - mailBoxCmd = (int *) (SDC_MAIL_BOX + 0x8); - mailBoxAddr = (long int *) (SDC_MAIL_BOX + 0x10); - mailBoxReadData = (long int *) (SDC_MAIL_BOX + 0x18); - - // write the SDC address register with the blockAddr - *mailBoxAddr = blockAddr; - *mailBoxCmd = 0x4; - - // wait until the mailbox has valid data - // this occurs when status[1] = 0 - while((*mailBoxStatus & 0x2) == 0x2); - - int index; - for(index = 0; index < 512/8; index++) { - Dst[index] = *mailBoxReadData; - } -} - -volatile void waitInitSDC(){ - volatile int * mailBoxStatus; - mailBoxStatus = (int *) (SDC_MAIL_BOX + 0x4); - while((*mailBoxStatus & 0x1) != 0x1); -} - -void setSDCCLK(int divider){ - divider = (1 - (divider >> 1)); - volatile int * mailBoxCLK; - mailBoxCLK = (int *) (SDC_MAIL_BOX + 0x0); - *mailBoxCLK = divider; -} diff --git a/tests/custom/fpga-test-sdc/sdcDriver.h b/tests/custom/fpga-test-sdc/sdcDriver.h deleted file mode 100644 index 7876aeda1..000000000 --- a/tests/custom/fpga-test-sdc/sdcDriver.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef __SDCDRIVER_H -#define __SDCDRIVER_H - - -void copySDC512(long int, long int *); -volatile void waitInitSDC(); -void setSDCCLK(int); - -#endif diff --git a/tests/custom/fpga-test-sdc/test-sdc.asm b/tests/custom/fpga-test-sdc/test-sdc.asm deleted file mode 100644 index 4bc98a27f..000000000 --- a/tests/custom/fpga-test-sdc/test-sdc.asm +++ /dev/null @@ -1,97 +0,0 @@ -#PERIOD = 22000000 -PERIOD = 20 - -.section .init -.global _start -.type _start, @function - - -_start: - # Initialize global pointer - .option push - .option norelax - 1:auipc gp, %pcrel_hi(__global_pointer$) - addi gp, gp, %pcrel_lo(1b) - .option pop - - li x1, 0 - li x2, 0 - li x4, 0 - li x5, 0 - li x6, 0 - li x7, 0 - li x8, 0 - li x9, 0 - li x10, 0 - li x11, 0 - li x12, 0 - li x13, 0 - li x14, 0 - li x15, 0 - li x16, 0 - li x17, 0 - li x18, 0 - li x19, 0 - li x20, 0 - li x21, 0 - li x22, 0 - li x23, 0 - li x24, 0 - li x25, 0 - li x26, 0 - li x27, 0 - li x28, 0 - li x29, 0 - li x30, 0 - li x31, 0 - - - # set the stack pointer to the top of memory - 8 bytes (pointer size) - li sp, 0x87FFFFF8 - - li a0, 0x20000000 - li a1, 0x80000000 - li a2, 2 - jal ra, copyFlash - - - # now toggle led so we know the copy completed. - - # write to gpio - li t2, 0xFF - la t3, 0x1001200C - li t4, 5 - -loop: - - # delay - li t0, PERIOD/2 -delay1: - addi t0, t0, -1 - bge t0, x0, delay1 - sw t2, 0x0(t3) - - li t0, PERIOD/2 -delay2: - addi t0, t0, -1 - bge t0, x0, delay2 - sw x0, 0x0(t3) - - addi t4, t4, -1 - bgt t4, x0, loop - - - - jal ra, _halt - -.section .text -.global _halt -.type _halt, @function -_halt: - li gp, 1 - li a0, 0 - ecall - j _halt - - - diff --git a/tests/custom/mibench_qsort/LICENSE b/tests/custom/mibench_qsort/LICENSE deleted file mode 100644 index 6016daa7c..000000000 --- a/tests/custom/mibench_qsort/LICENSE +++ /dev/null @@ -1,3 +0,0 @@ -Matt wrote this using STL. - -It is GPL'ed. diff --git a/tests/custom/mibench_qsort/Makefile b/tests/custom/mibench_qsort/Makefile deleted file mode 100644 index 0f9bba726..000000000 --- a/tests/custom/mibench_qsort/Makefile +++ /dev/null @@ -1,20 +0,0 @@ -TARGETDIR := qsort -TARGET := $(TARGETDIR)/$(TARGETDIR).elf -ROOT := .. -LIBRARY_DIRS := ${ROOT}/crt0 -LIBRARY_FILES := crt0 - -MARCH :=-march=rv64ic -MABI :=-mabi=lp64 -LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map -L $(RISCV)/riscv64-unknown-elf/lib -LINKER := ${ROOT}/linker8000-0000.x - -CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany -mstrict-align -O2 - -CC=riscv64-unknown-elf-gcc -DA=riscv64-unknown-elf-objdump -d - - -include $(ROOT)/makefile.inc - - diff --git a/tests/custom/mibench_qsort/qsort_small.c b/tests/custom/mibench_qsort/qsort_small.c deleted file mode 100644 index 1b28eea4c..000000000 --- a/tests/custom/mibench_qsort/qsort_small.c +++ /dev/null @@ -1,10038 +0,0 @@ -#include -#include -#include - -#define UNLIMIT -#define MAXARRAY 11000 /* this number, if too large, will cause a seg. fault!! */ - -struct myStringStruct { - char qstring[128]; -}; - -struct myStringStruct array[MAXARRAY]; - -int compare(const void *elem1, const void *elem2) -{ - int result; - - result = strcmp((*((struct myStringStruct *)elem1)).qstring, (*((struct myStringStruct *)elem2)).qstring); - - return (result < 0) ? 1 : ((result == 0) ? 0 : -1); -} - - -int -main(int argc, char *argv[]) { - FILE *fp; - int i,count=0; - -strcpy(array[count++].qstring, "Kurt"); -strcpy(array[count++].qstring, "Vonneguts"); -strcpy(array[count++].qstring, "Commencement"); -strcpy(array[count++].qstring, "Address"); -strcpy(array[count++].qstring, "at"); -strcpy(array[count++].qstring, "MIT"); -strcpy(array[count++].qstring, "Ladies"); -strcpy(array[count++].qstring, "and"); -strcpy(array[count++].qstring, "gentlemen"); -strcpy(array[count++].qstring, "of"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "class"); -strcpy(array[count++].qstring, "of"); -strcpy(array[count++].qstring, "97"); -strcpy(array[count++].qstring, "Wear"); -strcpy(array[count++].qstring, "sunscreen"); -strcpy(array[count++].qstring, "If"); -strcpy(array[count++].qstring, "I"); -strcpy(array[count++].qstring, "could"); -strcpy(array[count++].qstring, "offer"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "only"); -strcpy(array[count++].qstring, "one"); -strcpy(array[count++].qstring, "tip"); -strcpy(array[count++].qstring, "for"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "future"); -strcpy(array[count++].qstring, "sunscreen"); -strcpy(array[count++].qstring, "would"); -strcpy(array[count++].qstring, "be"); -strcpy(array[count++].qstring, "it"); -strcpy(array[count++].qstring, "The"); -strcpy(array[count++].qstring, "longterm"); -strcpy(array[count++].qstring, "benefits"); -strcpy(array[count++].qstring, "of"); -strcpy(array[count++].qstring, "sunscreen"); -strcpy(array[count++].qstring, "have"); -strcpy(array[count++].qstring, "been"); -strcpy(array[count++].qstring, "proved"); -strcpy(array[count++].qstring, "by"); -strcpy(array[count++].qstring, "scientists"); -strcpy(array[count++].qstring, "whereas"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "rest"); -strcpy(array[count++].qstring, "of"); -strcpy(array[count++].qstring, "my"); -strcpy(array[count++].qstring, "advice"); -strcpy(array[count++].qstring, "has"); -strcpy(array[count++].qstring, "no"); -strcpy(array[count++].qstring, "basis"); -strcpy(array[count++].qstring, "more"); -strcpy(array[count++].qstring, "reliable"); -strcpy(array[count++].qstring, "than"); -strcpy(array[count++].qstring, "my"); -strcpy(array[count++].qstring, "own"); -strcpy(array[count++].qstring, "meandering"); -strcpy(array[count++].qstring, "experience"); -strcpy(array[count++].qstring, "I"); -strcpy(array[count++].qstring, "will"); -strcpy(array[count++].qstring, "dispense"); -strcpy(array[count++].qstring, "this"); -strcpy(array[count++].qstring, "advice"); -strcpy(array[count++].qstring, "now"); -strcpy(array[count++].qstring, "Enjoy"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "power"); -strcpy(array[count++].qstring, "and"); -strcpy(array[count++].qstring, "beauty"); -strcpy(array[count++].qstring, "of"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "youth"); -strcpy(array[count++].qstring, "Oh"); -strcpy(array[count++].qstring, "never"); -strcpy(array[count++].qstring, "mind"); -strcpy(array[count++].qstring, "You"); -strcpy(array[count++].qstring, "will"); -strcpy(array[count++].qstring, "not"); -strcpy(array[count++].qstring, "understand"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "power"); -strcpy(array[count++].qstring, "and"); -strcpy(array[count++].qstring, "beauty"); -strcpy(array[count++].qstring, "of"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "youth"); -strcpy(array[count++].qstring, "until"); -strcpy(array[count++].qstring, "theyve"); -strcpy(array[count++].qstring, "faded"); -strcpy(array[count++].qstring, "But"); -strcpy(array[count++].qstring, "trust"); -strcpy(array[count++].qstring, "me"); -strcpy(array[count++].qstring, "in"); -strcpy(array[count++].qstring, "20"); -strcpy(array[count++].qstring, "years"); -strcpy(array[count++].qstring, "youll"); -strcpy(array[count++].qstring, "look"); -strcpy(array[count++].qstring, "back"); -strcpy(array[count++].qstring, "at"); -strcpy(array[count++].qstring, "photos"); -strcpy(array[count++].qstring, "of"); -strcpy(array[count++].qstring, "yourself"); -strcpy(array[count++].qstring, "and"); -strcpy(array[count++].qstring, "recall"); -strcpy(array[count++].qstring, "in"); -strcpy(array[count++].qstring, "a"); -strcpy(array[count++].qstring, "way"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "cant"); -strcpy(array[count++].qstring, "grasp"); -strcpy(array[count++].qstring, "now"); -strcpy(array[count++].qstring, "how"); -strcpy(array[count++].qstring, "much"); -strcpy(array[count++].qstring, "possibility"); -strcpy(array[count++].qstring, "lay"); -strcpy(array[count++].qstring, "before"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "and"); -strcpy(array[count++].qstring, "how"); -strcpy(array[count++].qstring, "fabulous"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "really"); -strcpy(array[count++].qstring, "looked"); -strcpy(array[count++].qstring, "You"); -strcpy(array[count++].qstring, "are"); -strcpy(array[count++].qstring, "not"); -strcpy(array[count++].qstring, "as"); -strcpy(array[count++].qstring, "fat"); -strcpy(array[count++].qstring, "as"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "imagine"); -strcpy(array[count++].qstring, "Dont"); -strcpy(array[count++].qstring, "worry"); -strcpy(array[count++].qstring, "about"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "future"); -strcpy(array[count++].qstring, "Or"); -strcpy(array[count++].qstring, "worry"); -strcpy(array[count++].qstring, "but"); -strcpy(array[count++].qstring, "know"); -strcpy(array[count++].qstring, "that"); -strcpy(array[count++].qstring, "worrying"); -strcpy(array[count++].qstring, "is"); -strcpy(array[count++].qstring, "as"); -strcpy(array[count++].qstring, "effective"); -strcpy(array[count++].qstring, "as"); -strcpy(array[count++].qstring, "trying"); -strcpy(array[count++].qstring, "to"); -strcpy(array[count++].qstring, "solve"); -strcpy(array[count++].qstring, "an"); -strcpy(array[count++].qstring, "algebra"); -strcpy(array[count++].qstring, "equation"); -strcpy(array[count++].qstring, "by"); -strcpy(array[count++].qstring, "chewing"); -strcpy(array[count++].qstring, "bubble"); -strcpy(array[count++].qstring, "gum"); -strcpy(array[count++].qstring, "The"); -strcpy(array[count++].qstring, "real"); -strcpy(array[count++].qstring, "troubles"); -strcpy(array[count++].qstring, "in"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "life"); -strcpy(array[count++].qstring, "are"); -strcpy(array[count++].qstring, "apt"); -strcpy(array[count++].qstring, "to"); -strcpy(array[count++].qstring, "be"); -strcpy(array[count++].qstring, "things"); -strcpy(array[count++].qstring, "that"); -strcpy(array[count++].qstring, "never"); -strcpy(array[count++].qstring, "crossed"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "worried"); -strcpy(array[count++].qstring, "mind"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "kind"); -strcpy(array[count++].qstring, "that"); -strcpy(array[count++].qstring, "blindside"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "at"); -strcpy(array[count++].qstring, "4"); -strcpy(array[count++].qstring, "pm"); -strcpy(array[count++].qstring, "on"); -strcpy(array[count++].qstring, "some"); -strcpy(array[count++].qstring, "idle"); -strcpy(array[count++].qstring, "Tuesday"); -strcpy(array[count++].qstring, "Do"); -strcpy(array[count++].qstring, "one"); -strcpy(array[count++].qstring, "thing"); -strcpy(array[count++].qstring, "every"); -strcpy(array[count++].qstring, "day"); -strcpy(array[count++].qstring, "that"); -strcpy(array[count++].qstring, "scares"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "Sing"); -strcpy(array[count++].qstring, "Dont"); -strcpy(array[count++].qstring, "be"); -strcpy(array[count++].qstring, "reckless"); -strcpy(array[count++].qstring, "with"); -strcpy(array[count++].qstring, "other"); -strcpy(array[count++].qstring, "peoples"); -strcpy(array[count++].qstring, "hearts"); -strcpy(array[count++].qstring, "Dont"); -strcpy(array[count++].qstring, "put"); -strcpy(array[count++].qstring, "up"); -strcpy(array[count++].qstring, "with"); -strcpy(array[count++].qstring, "people"); -strcpy(array[count++].qstring, "who"); -strcpy(array[count++].qstring, "are"); -strcpy(array[count++].qstring, "reckless"); -strcpy(array[count++].qstring, "with"); -strcpy(array[count++].qstring, "yours"); -strcpy(array[count++].qstring, "Floss"); -strcpy(array[count++].qstring, "Dont"); -strcpy(array[count++].qstring, "waste"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "time"); -strcpy(array[count++].qstring, "on"); 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-strcpy(array[count++].qstring, "old"); -strcpy(array[count++].qstring, "love"); -strcpy(array[count++].qstring, "letters"); -strcpy(array[count++].qstring, "Throw"); -strcpy(array[count++].qstring, "away"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "old"); -strcpy(array[count++].qstring, "bank"); -strcpy(array[count++].qstring, "statements"); -strcpy(array[count++].qstring, "Stretch"); -strcpy(array[count++].qstring, "Dont"); -strcpy(array[count++].qstring, "feel"); -strcpy(array[count++].qstring, "guilty"); -strcpy(array[count++].qstring, "if"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "dont"); -strcpy(array[count++].qstring, "know"); -strcpy(array[count++].qstring, "what"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "want"); -strcpy(array[count++].qstring, "to"); -strcpy(array[count++].qstring, "do"); -strcpy(array[count++].qstring, "with"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "life"); 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-strcpy(array[count++].qstring, "know"); -strcpy(array[count++].qstring, "still"); -strcpy(array[count++].qstring, "dont"); -strcpy(array[count++].qstring, "Get"); -strcpy(array[count++].qstring, "plenty"); -strcpy(array[count++].qstring, "of"); -strcpy(array[count++].qstring, "calcium"); -strcpy(array[count++].qstring, "Be"); -strcpy(array[count++].qstring, "kind"); -strcpy(array[count++].qstring, "to"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "knees"); -strcpy(array[count++].qstring, "Youll"); -strcpy(array[count++].qstring, "miss"); -strcpy(array[count++].qstring, "them"); -strcpy(array[count++].qstring, "when"); -strcpy(array[count++].qstring, "theyre"); -strcpy(array[count++].qstring, "gone"); -strcpy(array[count++].qstring, "Maybe"); -strcpy(array[count++].qstring, "youll"); -strcpy(array[count++].qstring, "marry"); -strcpy(array[count++].qstring, "maybe"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "wont"); -strcpy(array[count++].qstring, "Maybe"); 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-strcpy(array[count++].qstring, "You"); -strcpy(array[count++].qstring, "never"); -strcpy(array[count++].qstring, "know"); -strcpy(array[count++].qstring, "when"); -strcpy(array[count++].qstring, "theyll"); -strcpy(array[count++].qstring, "be"); -strcpy(array[count++].qstring, "gone"); -strcpy(array[count++].qstring, "for"); -strcpy(array[count++].qstring, "good"); -strcpy(array[count++].qstring, "Be"); -strcpy(array[count++].qstring, "nice"); -strcpy(array[count++].qstring, "to"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "siblings"); -strcpy(array[count++].qstring, "Theyre"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "best"); -strcpy(array[count++].qstring, "link"); -strcpy(array[count++].qstring, "to"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "past"); -strcpy(array[count++].qstring, "and"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "people"); -strcpy(array[count++].qstring, "most"); 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-strcpy(array[count++].qstring, "to"); -strcpy(array[count++].qstring, "bridge"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "gaps"); -strcpy(array[count++].qstring, "in"); -strcpy(array[count++].qstring, "geography"); -strcpy(array[count++].qstring, "and"); -strcpy(array[count++].qstring, "lifestyle"); -strcpy(array[count++].qstring, "because"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "older"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "get"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "more"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "need"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "people"); -strcpy(array[count++].qstring, "who"); -strcpy(array[count++].qstring, "knew"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "when"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "were"); 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-strcpy(array[count++].qstring, "Youll"); -strcpy(array[count++].qstring, "miss"); -strcpy(array[count++].qstring, "them"); -strcpy(array[count++].qstring, "when"); -strcpy(array[count++].qstring, "theyre"); -strcpy(array[count++].qstring, "gone"); -strcpy(array[count++].qstring, "Maybe"); -strcpy(array[count++].qstring, "youll"); -strcpy(array[count++].qstring, "marry"); -strcpy(array[count++].qstring, "maybe"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "wont"); -strcpy(array[count++].qstring, "Maybe"); -strcpy(array[count++].qstring, "youll"); -strcpy(array[count++].qstring, "have"); -strcpy(array[count++].qstring, "children"); -strcpy(array[count++].qstring, "maybe"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "wont"); -strcpy(array[count++].qstring, "Maybe"); -strcpy(array[count++].qstring, "youll"); -strcpy(array[count++].qstring, "divorce"); -strcpy(array[count++].qstring, "at"); -strcpy(array[count++].qstring, "40"); -strcpy(array[count++].qstring, "maybe"); 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-strcpy(array[count++].qstring, "are"); -strcpy(array[count++].qstring, "half"); -strcpy(array[count++].qstring, "chance"); -strcpy(array[count++].qstring, "So"); -strcpy(array[count++].qstring, "are"); -strcpy(array[count++].qstring, "everybody"); -strcpy(array[count++].qstring, "elses"); -strcpy(array[count++].qstring, "Enjoy"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "body"); -strcpy(array[count++].qstring, "Use"); -strcpy(array[count++].qstring, "it"); -strcpy(array[count++].qstring, "every"); -strcpy(array[count++].qstring, "way"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "can"); -strcpy(array[count++].qstring, "Dont"); -strcpy(array[count++].qstring, "be"); -strcpy(array[count++].qstring, "afraid"); -strcpy(array[count++].qstring, "of"); -strcpy(array[count++].qstring, "it"); -strcpy(array[count++].qstring, "or"); -strcpy(array[count++].qstring, "of"); -strcpy(array[count++].qstring, "what"); -strcpy(array[count++].qstring, "other"); -strcpy(array[count++].qstring, "people"); -strcpy(array[count++].qstring, "think"); -strcpy(array[count++].qstring, "of"); -strcpy(array[count++].qstring, "it"); -strcpy(array[count++].qstring, "Its"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "greatest"); -strcpy(array[count++].qstring, "instrument"); -strcpy(array[count++].qstring, "youll"); -strcpy(array[count++].qstring, "ever"); -strcpy(array[count++].qstring, "own"); -strcpy(array[count++].qstring, "Dance"); -strcpy(array[count++].qstring, "even"); -strcpy(array[count++].qstring, "if"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "have"); -strcpy(array[count++].qstring, "nowhere"); -strcpy(array[count++].qstring, "to"); -strcpy(array[count++].qstring, "do"); -strcpy(array[count++].qstring, "it"); -strcpy(array[count++].qstring, "but"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "living"); -strcpy(array[count++].qstring, "room"); -strcpy(array[count++].qstring, "Read"); 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-strcpy(array[count++].qstring, "You"); -strcpy(array[count++].qstring, "never"); -strcpy(array[count++].qstring, "know"); -strcpy(array[count++].qstring, "when"); -strcpy(array[count++].qstring, "theyll"); -strcpy(array[count++].qstring, "be"); -strcpy(array[count++].qstring, "gone"); -strcpy(array[count++].qstring, "for"); -strcpy(array[count++].qstring, "good"); -strcpy(array[count++].qstring, "Be"); -strcpy(array[count++].qstring, "nice"); -strcpy(array[count++].qstring, "to"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "siblings"); -strcpy(array[count++].qstring, "Theyre"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "best"); -strcpy(array[count++].qstring, "link"); -strcpy(array[count++].qstring, "to"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "past"); -strcpy(array[count++].qstring, "and"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "people"); -strcpy(array[count++].qstring, "most"); -strcpy(array[count++].qstring, "likely"); -strcpy(array[count++].qstring, "to"); -strcpy(array[count++].qstring, "stick"); -strcpy(array[count++].qstring, "with"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "in"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "future"); -strcpy(array[count++].qstring, "Understand"); -strcpy(array[count++].qstring, "that"); -strcpy(array[count++].qstring, "friends"); -strcpy(array[count++].qstring, "come"); -strcpy(array[count++].qstring, "and"); -strcpy(array[count++].qstring, "go"); -strcpy(array[count++].qstring, "but"); -strcpy(array[count++].qstring, "with"); -strcpy(array[count++].qstring, "a"); -strcpy(array[count++].qstring, "precious"); -strcpy(array[count++].qstring, "few"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "should"); -strcpy(array[count++].qstring, "hold"); -strcpy(array[count++].qstring, "on"); -strcpy(array[count++].qstring, "Work"); -strcpy(array[count++].qstring, "hard"); -strcpy(array[count++].qstring, "to"); -strcpy(array[count++].qstring, "bridge"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "gaps"); -strcpy(array[count++].qstring, "in"); -strcpy(array[count++].qstring, "geography"); -strcpy(array[count++].qstring, "and"); -strcpy(array[count++].qstring, "lifestyle"); -strcpy(array[count++].qstring, "because"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "older"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "get"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "more"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "need"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "people"); -strcpy(array[count++].qstring, "who"); -strcpy(array[count++].qstring, "knew"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "when"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "were"); -strcpy(array[count++].qstring, "young"); -strcpy(array[count++].qstring, "Live"); -strcpy(array[count++].qstring, "in"); -strcpy(array[count++].qstring, "New"); -strcpy(array[count++].qstring, "York"); -strcpy(array[count++].qstring, "City"); -strcpy(array[count++].qstring, "once"); -strcpy(array[count++].qstring, "but"); -strcpy(array[count++].qstring, "leave"); -strcpy(array[count++].qstring, "before"); -strcpy(array[count++].qstring, "it"); -strcpy(array[count++].qstring, "makes"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "hard"); -strcpy(array[count++].qstring, "Live"); -strcpy(array[count++].qstring, "in"); -strcpy(array[count++].qstring, "Northern"); -strcpy(array[count++].qstring, "California"); -strcpy(array[count++].qstring, "once"); -strcpy(array[count++].qstring, "but"); -strcpy(array[count++].qstring, "leave"); -strcpy(array[count++].qstring, "before"); -strcpy(array[count++].qstring, "it"); -strcpy(array[count++].qstring, "makes"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "soft"); -strcpy(array[count++].qstring, "Travel"); -strcpy(array[count++].qstring, "Accept"); -strcpy(array[count++].qstring, "certain"); -strcpy(array[count++].qstring, "inalienable"); -strcpy(array[count++].qstring, "truths"); -strcpy(array[count++].qstring, "Prices"); -strcpy(array[count++].qstring, "will"); -strcpy(array[count++].qstring, "rise"); -strcpy(array[count++].qstring, "Politicians"); -strcpy(array[count++].qstring, "will"); -strcpy(array[count++].qstring, "philander"); -strcpy(array[count++].qstring, "You"); -strcpy(array[count++].qstring, "too"); -strcpy(array[count++].qstring, "will"); -strcpy(array[count++].qstring, "get"); -strcpy(array[count++].qstring, "old"); -strcpy(array[count++].qstring, "And"); -strcpy(array[count++].qstring, "when"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "do"); -strcpy(array[count++].qstring, "youll"); -strcpy(array[count++].qstring, "fantasize"); -strcpy(array[count++].qstring, "that"); -strcpy(array[count++].qstring, "when"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "were"); -strcpy(array[count++].qstring, "young"); -strcpy(array[count++].qstring, "prices"); -strcpy(array[count++].qstring, "were"); -strcpy(array[count++].qstring, "reasonable"); -strcpy(array[count++].qstring, "politicians"); -strcpy(array[count++].qstring, "were"); -strcpy(array[count++].qstring, "noble"); -strcpy(array[count++].qstring, "and"); -strcpy(array[count++].qstring, "children"); -strcpy(array[count++].qstring, "respected"); -strcpy(array[count++].qstring, "their"); -strcpy(array[count++].qstring, "elders"); -strcpy(array[count++].qstring, "Respect"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "elders"); -strcpy(array[count++].qstring, "Dont"); -strcpy(array[count++].qstring, "expect"); -strcpy(array[count++].qstring, "anyone"); -strcpy(array[count++].qstring, "else"); -strcpy(array[count++].qstring, "to"); -strcpy(array[count++].qstring, "support"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "Maybe"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "have"); -strcpy(array[count++].qstring, "a"); -strcpy(array[count++].qstring, "trust"); -strcpy(array[count++].qstring, "fund"); -strcpy(array[count++].qstring, "Maybe"); -strcpy(array[count++].qstring, "youll"); -strcpy(array[count++].qstring, "have"); -strcpy(array[count++].qstring, "a"); -strcpy(array[count++].qstring, "wealthy"); -strcpy(array[count++].qstring, "spouse"); -strcpy(array[count++].qstring, "But"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "never"); -strcpy(array[count++].qstring, "know"); -strcpy(array[count++].qstring, "when"); -strcpy(array[count++].qstring, "either"); -strcpy(array[count++].qstring, "one"); -strcpy(array[count++].qstring, "might"); -strcpy(array[count++].qstring, "run"); -strcpy(array[count++].qstring, "out"); -strcpy(array[count++].qstring, "Dont"); -strcpy(array[count++].qstring, "mess"); -strcpy(array[count++].qstring, "too"); -strcpy(array[count++].qstring, "much"); -strcpy(array[count++].qstring, "with"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "hair"); -strcpy(array[count++].qstring, "or"); -strcpy(array[count++].qstring, "by"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "time"); -strcpy(array[count++].qstring, "youre"); -strcpy(array[count++].qstring, "40"); -strcpy(array[count++].qstring, "it"); -strcpy(array[count++].qstring, "will"); -strcpy(array[count++].qstring, "look"); -strcpy(array[count++].qstring, "85"); -strcpy(array[count++].qstring, "Be"); -strcpy(array[count++].qstring, "careful"); -strcpy(array[count++].qstring, "whose"); -strcpy(array[count++].qstring, "advice"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "buy"); -strcpy(array[count++].qstring, "but"); -strcpy(array[count++].qstring, "be"); -strcpy(array[count++].qstring, "patient"); -strcpy(array[count++].qstring, "with"); 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-strcpy(array[count++].qstring, "and"); -strcpy(array[count++].qstring, "how"); -strcpy(array[count++].qstring, "fabulous"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "really"); -strcpy(array[count++].qstring, "looked"); -strcpy(array[count++].qstring, "You"); -strcpy(array[count++].qstring, "are"); -strcpy(array[count++].qstring, "not"); -strcpy(array[count++].qstring, "as"); -strcpy(array[count++].qstring, "fat"); -strcpy(array[count++].qstring, "as"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "imagine"); -strcpy(array[count++].qstring, "Dont"); -strcpy(array[count++].qstring, "worry"); -strcpy(array[count++].qstring, "about"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "future"); -strcpy(array[count++].qstring, "Or"); -strcpy(array[count++].qstring, "worry"); -strcpy(array[count++].qstring, "but"); -strcpy(array[count++].qstring, "know"); -strcpy(array[count++].qstring, "that"); -strcpy(array[count++].qstring, "worrying"); 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-strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "Sing"); -strcpy(array[count++].qstring, "Dont"); -strcpy(array[count++].qstring, "be"); -strcpy(array[count++].qstring, "reckless"); -strcpy(array[count++].qstring, "with"); -strcpy(array[count++].qstring, "other"); -strcpy(array[count++].qstring, "peoples"); -strcpy(array[count++].qstring, "hearts"); -strcpy(array[count++].qstring, "Dont"); -strcpy(array[count++].qstring, "put"); -strcpy(array[count++].qstring, "up"); -strcpy(array[count++].qstring, "with"); -strcpy(array[count++].qstring, "people"); -strcpy(array[count++].qstring, "who"); -strcpy(array[count++].qstring, "are"); -strcpy(array[count++].qstring, "reckless"); -strcpy(array[count++].qstring, "with"); -strcpy(array[count++].qstring, "yours"); -strcpy(array[count++].qstring, "Floss"); -strcpy(array[count++].qstring, "Dont"); -strcpy(array[count++].qstring, "waste"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "time"); -strcpy(array[count++].qstring, "on"); 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-strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "insults"); -strcpy(array[count++].qstring, "If"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "succeed"); -strcpy(array[count++].qstring, "in"); -strcpy(array[count++].qstring, "doing"); -strcpy(array[count++].qstring, "this"); -strcpy(array[count++].qstring, "tell"); -strcpy(array[count++].qstring, "me"); -strcpy(array[count++].qstring, "how"); -strcpy(array[count++].qstring, "Keep"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "old"); -strcpy(array[count++].qstring, "love"); -strcpy(array[count++].qstring, "letters"); -strcpy(array[count++].qstring, "Throw"); -strcpy(array[count++].qstring, "away"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "old"); -strcpy(array[count++].qstring, "bank"); -strcpy(array[count++].qstring, "statements"); -strcpy(array[count++].qstring, "Stretch"); -strcpy(array[count++].qstring, "Dont"); -strcpy(array[count++].qstring, "feel"); -strcpy(array[count++].qstring, "guilty"); -strcpy(array[count++].qstring, "if"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "dont"); -strcpy(array[count++].qstring, "know"); -strcpy(array[count++].qstring, "what"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "want"); -strcpy(array[count++].qstring, "to"); -strcpy(array[count++].qstring, "do"); -strcpy(array[count++].qstring, "with"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "life"); -strcpy(array[count++].qstring, "The"); -strcpy(array[count++].qstring, "most"); -strcpy(array[count++].qstring, "interesting"); -strcpy(array[count++].qstring, "people"); -strcpy(array[count++].qstring, "I"); -strcpy(array[count++].qstring, "know"); -strcpy(array[count++].qstring, "didnt"); -strcpy(array[count++].qstring, "know"); -strcpy(array[count++].qstring, "at"); -strcpy(array[count++].qstring, "22"); -strcpy(array[count++].qstring, "what"); -strcpy(array[count++].qstring, "they"); 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-strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "Sing"); -strcpy(array[count++].qstring, "Dont"); -strcpy(array[count++].qstring, "be"); -strcpy(array[count++].qstring, "reckless"); -strcpy(array[count++].qstring, "with"); -strcpy(array[count++].qstring, "other"); -strcpy(array[count++].qstring, "peoples"); -strcpy(array[count++].qstring, "hearts"); -strcpy(array[count++].qstring, "Dont"); -strcpy(array[count++].qstring, "put"); -strcpy(array[count++].qstring, "up"); -strcpy(array[count++].qstring, "with"); -strcpy(array[count++].qstring, "people"); -strcpy(array[count++].qstring, "who"); -strcpy(array[count++].qstring, "are"); -strcpy(array[count++].qstring, "reckless"); -strcpy(array[count++].qstring, "with"); -strcpy(array[count++].qstring, "yours"); -strcpy(array[count++].qstring, "Floss"); -strcpy(array[count++].qstring, "Dont"); -strcpy(array[count++].qstring, "waste"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "time"); -strcpy(array[count++].qstring, "on"); -strcpy(array[count++].qstring, "jealousy"); -strcpy(array[count++].qstring, "Sometimes"); -strcpy(array[count++].qstring, "youre"); -strcpy(array[count++].qstring, "ahead"); -strcpy(array[count++].qstring, "sometimes"); -strcpy(array[count++].qstring, "youre"); -strcpy(array[count++].qstring, "behind"); -strcpy(array[count++].qstring, "The"); -strcpy(array[count++].qstring, "race"); -strcpy(array[count++].qstring, "is"); -strcpy(array[count++].qstring, "long"); -strcpy(array[count++].qstring, "and"); -strcpy(array[count++].qstring, "in"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "end"); -strcpy(array[count++].qstring, "its"); -strcpy(array[count++].qstring, "only"); -strcpy(array[count++].qstring, "with"); -strcpy(array[count++].qstring, "yourself"); -strcpy(array[count++].qstring, "Remember"); -strcpy(array[count++].qstring, "compliments"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "receive"); -strcpy(array[count++].qstring, "Forget"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "insults"); -strcpy(array[count++].qstring, "If"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "succeed"); -strcpy(array[count++].qstring, "in"); -strcpy(array[count++].qstring, "doing"); -strcpy(array[count++].qstring, "this"); -strcpy(array[count++].qstring, "tell"); -strcpy(array[count++].qstring, "me"); -strcpy(array[count++].qstring, "how"); -strcpy(array[count++].qstring, "Keep"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "old"); -strcpy(array[count++].qstring, "love"); -strcpy(array[count++].qstring, "letters"); -strcpy(array[count++].qstring, "Throw"); -strcpy(array[count++].qstring, "away"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "old"); -strcpy(array[count++].qstring, "bank"); -strcpy(array[count++].qstring, "statements"); -strcpy(array[count++].qstring, "Stretch"); -strcpy(array[count++].qstring, "Dont"); -strcpy(array[count++].qstring, "feel"); -strcpy(array[count++].qstring, "guilty"); -strcpy(array[count++].qstring, "if"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "dont"); -strcpy(array[count++].qstring, "know"); -strcpy(array[count++].qstring, "what"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "want"); -strcpy(array[count++].qstring, "to"); -strcpy(array[count++].qstring, "do"); -strcpy(array[count++].qstring, "with"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "life"); -strcpy(array[count++].qstring, "The"); -strcpy(array[count++].qstring, "most"); -strcpy(array[count++].qstring, "interesting"); -strcpy(array[count++].qstring, "people"); -strcpy(array[count++].qstring, "I"); -strcpy(array[count++].qstring, "know"); -strcpy(array[count++].qstring, "didnt"); -strcpy(array[count++].qstring, "know"); -strcpy(array[count++].qstring, "at"); -strcpy(array[count++].qstring, "22"); -strcpy(array[count++].qstring, "what"); -strcpy(array[count++].qstring, "they"); -strcpy(array[count++].qstring, "wanted"); -strcpy(array[count++].qstring, "to"); -strcpy(array[count++].qstring, "do"); -strcpy(array[count++].qstring, "with"); -strcpy(array[count++].qstring, "their"); -strcpy(array[count++].qstring, "lives"); -strcpy(array[count++].qstring, "Some"); -strcpy(array[count++].qstring, "of"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "most"); -strcpy(array[count++].qstring, "interesting"); -strcpy(array[count++].qstring, "40yearolds"); -strcpy(array[count++].qstring, "I"); -strcpy(array[count++].qstring, "know"); -strcpy(array[count++].qstring, "still"); -strcpy(array[count++].qstring, "dont"); -strcpy(array[count++].qstring, "Get"); -strcpy(array[count++].qstring, "plenty"); -strcpy(array[count++].qstring, "of"); -strcpy(array[count++].qstring, "calcium"); -strcpy(array[count++].qstring, "Be"); -strcpy(array[count++].qstring, "kind"); -strcpy(array[count++].qstring, "to"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "knees"); -strcpy(array[count++].qstring, "Youll"); -strcpy(array[count++].qstring, "miss"); -strcpy(array[count++].qstring, "them"); -strcpy(array[count++].qstring, "when"); -strcpy(array[count++].qstring, "theyre"); -strcpy(array[count++].qstring, "gone"); -strcpy(array[count++].qstring, "Maybe"); -strcpy(array[count++].qstring, "youll"); -strcpy(array[count++].qstring, "marry"); -strcpy(array[count++].qstring, "maybe"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "wont"); -strcpy(array[count++].qstring, "Maybe"); -strcpy(array[count++].qstring, "youll"); -strcpy(array[count++].qstring, "have"); -strcpy(array[count++].qstring, "children"); -strcpy(array[count++].qstring, "maybe"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "wont"); -strcpy(array[count++].qstring, "Maybe"); -strcpy(array[count++].qstring, "youll"); -strcpy(array[count++].qstring, "divorce"); -strcpy(array[count++].qstring, "at"); -strcpy(array[count++].qstring, "40"); -strcpy(array[count++].qstring, "maybe"); -strcpy(array[count++].qstring, "youll"); -strcpy(array[count++].qstring, "dance"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "funky"); -strcpy(array[count++].qstring, "chicken"); -strcpy(array[count++].qstring, "on"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "75th"); -strcpy(array[count++].qstring, "wedding"); -strcpy(array[count++].qstring, "anniversary"); -strcpy(array[count++].qstring, "Whatever"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "do"); -strcpy(array[count++].qstring, "dont"); -strcpy(array[count++].qstring, "congratulate"); -strcpy(array[count++].qstring, "yourself"); -strcpy(array[count++].qstring, "too"); -strcpy(array[count++].qstring, "much"); -strcpy(array[count++].qstring, "or"); -strcpy(array[count++].qstring, "berate"); -strcpy(array[count++].qstring, "yourself"); -strcpy(array[count++].qstring, "either"); -strcpy(array[count++].qstring, "Your"); -strcpy(array[count++].qstring, "choices"); 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-strcpy(array[count++].qstring, "people"); -strcpy(array[count++].qstring, "think"); -strcpy(array[count++].qstring, "of"); -strcpy(array[count++].qstring, "it"); -strcpy(array[count++].qstring, "Its"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "greatest"); -strcpy(array[count++].qstring, "instrument"); -strcpy(array[count++].qstring, "youll"); -strcpy(array[count++].qstring, "ever"); -strcpy(array[count++].qstring, "own"); -strcpy(array[count++].qstring, "Dance"); -strcpy(array[count++].qstring, "even"); -strcpy(array[count++].qstring, "if"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "have"); -strcpy(array[count++].qstring, "nowhere"); -strcpy(array[count++].qstring, "to"); -strcpy(array[count++].qstring, "do"); -strcpy(array[count++].qstring, "it"); -strcpy(array[count++].qstring, "but"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "living"); -strcpy(array[count++].qstring, "room"); -strcpy(array[count++].qstring, "Read"); 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-strcpy(array[count++].qstring, "and"); -strcpy(array[count++].qstring, "go"); -strcpy(array[count++].qstring, "but"); -strcpy(array[count++].qstring, "with"); -strcpy(array[count++].qstring, "a"); -strcpy(array[count++].qstring, "precious"); -strcpy(array[count++].qstring, "few"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "should"); -strcpy(array[count++].qstring, "hold"); -strcpy(array[count++].qstring, "on"); -strcpy(array[count++].qstring, "Work"); -strcpy(array[count++].qstring, "hard"); -strcpy(array[count++].qstring, "to"); -strcpy(array[count++].qstring, "bridge"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "gaps"); -strcpy(array[count++].qstring, "in"); -strcpy(array[count++].qstring, "geography"); -strcpy(array[count++].qstring, "and"); -strcpy(array[count++].qstring, "lifestyle"); -strcpy(array[count++].qstring, "because"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "older"); -strcpy(array[count++].qstring, "you"); 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-strcpy(array[count++].qstring, "whereas"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "rest"); -strcpy(array[count++].qstring, "of"); -strcpy(array[count++].qstring, "my"); -strcpy(array[count++].qstring, "advice"); -strcpy(array[count++].qstring, "has"); -strcpy(array[count++].qstring, "no"); -strcpy(array[count++].qstring, "basis"); -strcpy(array[count++].qstring, "more"); -strcpy(array[count++].qstring, "reliable"); -strcpy(array[count++].qstring, "than"); -strcpy(array[count++].qstring, "my"); -strcpy(array[count++].qstring, "own"); -strcpy(array[count++].qstring, "meandering"); -strcpy(array[count++].qstring, "experience"); -strcpy(array[count++].qstring, "I"); -strcpy(array[count++].qstring, "will"); -strcpy(array[count++].qstring, "dispense"); -strcpy(array[count++].qstring, "this"); -strcpy(array[count++].qstring, "advice"); -strcpy(array[count++].qstring, "now"); -strcpy(array[count++].qstring, "Enjoy"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "power"); -strcpy(array[count++].qstring, "and"); -strcpy(array[count++].qstring, "beauty"); -strcpy(array[count++].qstring, "of"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "youth"); -strcpy(array[count++].qstring, "Oh"); -strcpy(array[count++].qstring, "never"); -strcpy(array[count++].qstring, "mind"); -strcpy(array[count++].qstring, "You"); -strcpy(array[count++].qstring, "will"); -strcpy(array[count++].qstring, "not"); -strcpy(array[count++].qstring, "understand"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "power"); -strcpy(array[count++].qstring, "and"); -strcpy(array[count++].qstring, "beauty"); -strcpy(array[count++].qstring, "of"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "youth"); -strcpy(array[count++].qstring, "until"); -strcpy(array[count++].qstring, "theyve"); -strcpy(array[count++].qstring, "faded"); -strcpy(array[count++].qstring, "But"); -strcpy(array[count++].qstring, "trust"); -strcpy(array[count++].qstring, "me"); -strcpy(array[count++].qstring, "in"); -strcpy(array[count++].qstring, "20"); -strcpy(array[count++].qstring, "years"); -strcpy(array[count++].qstring, "youll"); -strcpy(array[count++].qstring, "look"); -strcpy(array[count++].qstring, "back"); -strcpy(array[count++].qstring, "at"); -strcpy(array[count++].qstring, "photos"); -strcpy(array[count++].qstring, "of"); -strcpy(array[count++].qstring, "yourself"); -strcpy(array[count++].qstring, "and"); -strcpy(array[count++].qstring, "recall"); -strcpy(array[count++].qstring, "in"); -strcpy(array[count++].qstring, "a"); -strcpy(array[count++].qstring, "way"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "cant"); -strcpy(array[count++].qstring, "grasp"); -strcpy(array[count++].qstring, "now"); -strcpy(array[count++].qstring, "how"); -strcpy(array[count++].qstring, "much"); -strcpy(array[count++].qstring, "possibility"); -strcpy(array[count++].qstring, "lay"); -strcpy(array[count++].qstring, "before"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "and"); -strcpy(array[count++].qstring, "how"); -strcpy(array[count++].qstring, "fabulous"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "really"); -strcpy(array[count++].qstring, "looked"); -strcpy(array[count++].qstring, "You"); -strcpy(array[count++].qstring, "are"); -strcpy(array[count++].qstring, "not"); -strcpy(array[count++].qstring, "as"); -strcpy(array[count++].qstring, "fat"); -strcpy(array[count++].qstring, "as"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "imagine"); -strcpy(array[count++].qstring, "Dont"); -strcpy(array[count++].qstring, "worry"); -strcpy(array[count++].qstring, "about"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "future"); -strcpy(array[count++].qstring, "Or"); -strcpy(array[count++].qstring, "worry"); -strcpy(array[count++].qstring, "but"); -strcpy(array[count++].qstring, "know"); -strcpy(array[count++].qstring, "that"); -strcpy(array[count++].qstring, "worrying"); -strcpy(array[count++].qstring, "is"); -strcpy(array[count++].qstring, "as"); -strcpy(array[count++].qstring, "effective"); -strcpy(array[count++].qstring, "as"); -strcpy(array[count++].qstring, "trying"); -strcpy(array[count++].qstring, "to"); -strcpy(array[count++].qstring, "solve"); -strcpy(array[count++].qstring, "an"); -strcpy(array[count++].qstring, "algebra"); -strcpy(array[count++].qstring, "equation"); -strcpy(array[count++].qstring, "by"); -strcpy(array[count++].qstring, "chewing"); -strcpy(array[count++].qstring, "bubble"); -strcpy(array[count++].qstring, "gum"); -strcpy(array[count++].qstring, "The"); -strcpy(array[count++].qstring, "real"); -strcpy(array[count++].qstring, "troubles"); -strcpy(array[count++].qstring, "in"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "life"); -strcpy(array[count++].qstring, "are"); -strcpy(array[count++].qstring, "apt"); -strcpy(array[count++].qstring, "to"); -strcpy(array[count++].qstring, "be"); -strcpy(array[count++].qstring, "things"); -strcpy(array[count++].qstring, "that"); -strcpy(array[count++].qstring, "never"); -strcpy(array[count++].qstring, "crossed"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "worried"); -strcpy(array[count++].qstring, "mind"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "kind"); -strcpy(array[count++].qstring, "that"); -strcpy(array[count++].qstring, "blindside"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "at"); -strcpy(array[count++].qstring, "4"); -strcpy(array[count++].qstring, "pm"); -strcpy(array[count++].qstring, "on"); -strcpy(array[count++].qstring, "some"); -strcpy(array[count++].qstring, "idle"); -strcpy(array[count++].qstring, "Tuesday"); -strcpy(array[count++].qstring, "Do"); -strcpy(array[count++].qstring, "one"); -strcpy(array[count++].qstring, "thing"); -strcpy(array[count++].qstring, "every"); -strcpy(array[count++].qstring, "day"); -strcpy(array[count++].qstring, "that"); -strcpy(array[count++].qstring, "scares"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "Sing"); -strcpy(array[count++].qstring, "Dont"); -strcpy(array[count++].qstring, "be"); -strcpy(array[count++].qstring, "reckless"); -strcpy(array[count++].qstring, "with"); -strcpy(array[count++].qstring, "other"); -strcpy(array[count++].qstring, "peoples"); -strcpy(array[count++].qstring, "hearts"); -strcpy(array[count++].qstring, "Dont"); -strcpy(array[count++].qstring, "put"); -strcpy(array[count++].qstring, "up"); -strcpy(array[count++].qstring, "with"); -strcpy(array[count++].qstring, "people"); -strcpy(array[count++].qstring, "who"); -strcpy(array[count++].qstring, "are"); -strcpy(array[count++].qstring, "reckless"); -strcpy(array[count++].qstring, "with"); -strcpy(array[count++].qstring, "yours"); -strcpy(array[count++].qstring, "Floss"); -strcpy(array[count++].qstring, "Dont"); -strcpy(array[count++].qstring, "waste"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "time"); -strcpy(array[count++].qstring, "on"); -strcpy(array[count++].qstring, "jealousy"); -strcpy(array[count++].qstring, "Sometimes"); -strcpy(array[count++].qstring, "youre"); -strcpy(array[count++].qstring, "ahead"); -strcpy(array[count++].qstring, "sometimes"); -strcpy(array[count++].qstring, "youre"); -strcpy(array[count++].qstring, "behind"); -strcpy(array[count++].qstring, "The"); -strcpy(array[count++].qstring, "race"); -strcpy(array[count++].qstring, "is"); -strcpy(array[count++].qstring, "long"); -strcpy(array[count++].qstring, "and"); -strcpy(array[count++].qstring, "in"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "end"); -strcpy(array[count++].qstring, "its"); -strcpy(array[count++].qstring, "only"); -strcpy(array[count++].qstring, "with"); -strcpy(array[count++].qstring, "yourself"); -strcpy(array[count++].qstring, "Remember"); -strcpy(array[count++].qstring, "compliments"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "receive"); -strcpy(array[count++].qstring, "Forget"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "insults"); -strcpy(array[count++].qstring, "If"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "succeed"); -strcpy(array[count++].qstring, "in"); -strcpy(array[count++].qstring, "doing"); -strcpy(array[count++].qstring, "this"); -strcpy(array[count++].qstring, "tell"); -strcpy(array[count++].qstring, "me"); -strcpy(array[count++].qstring, "how"); -strcpy(array[count++].qstring, "Keep"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "old"); -strcpy(array[count++].qstring, "love"); -strcpy(array[count++].qstring, "letters"); -strcpy(array[count++].qstring, "Throw"); -strcpy(array[count++].qstring, "away"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "old"); -strcpy(array[count++].qstring, "bank"); -strcpy(array[count++].qstring, "statements"); -strcpy(array[count++].qstring, "Stretch"); -strcpy(array[count++].qstring, "Dont"); -strcpy(array[count++].qstring, "feel"); -strcpy(array[count++].qstring, "guilty"); -strcpy(array[count++].qstring, "if"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "dont"); -strcpy(array[count++].qstring, "know"); -strcpy(array[count++].qstring, "what"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "want"); -strcpy(array[count++].qstring, "to"); -strcpy(array[count++].qstring, "do"); -strcpy(array[count++].qstring, "with"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "life"); -strcpy(array[count++].qstring, "The"); -strcpy(array[count++].qstring, "most"); -strcpy(array[count++].qstring, "interesting"); -strcpy(array[count++].qstring, "people"); -strcpy(array[count++].qstring, "I"); -strcpy(array[count++].qstring, "know"); -strcpy(array[count++].qstring, "didnt"); -strcpy(array[count++].qstring, "know"); -strcpy(array[count++].qstring, "at"); -strcpy(array[count++].qstring, "22"); -strcpy(array[count++].qstring, "what"); -strcpy(array[count++].qstring, "they"); -strcpy(array[count++].qstring, "wanted"); -strcpy(array[count++].qstring, "to"); -strcpy(array[count++].qstring, "do"); -strcpy(array[count++].qstring, "with"); -strcpy(array[count++].qstring, "their"); -strcpy(array[count++].qstring, "lives"); -strcpy(array[count++].qstring, "Some"); -strcpy(array[count++].qstring, "of"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "most"); -strcpy(array[count++].qstring, "interesting"); -strcpy(array[count++].qstring, "40yearolds"); -strcpy(array[count++].qstring, "I"); -strcpy(array[count++].qstring, "know"); -strcpy(array[count++].qstring, "still"); -strcpy(array[count++].qstring, "dont"); -strcpy(array[count++].qstring, "Get"); -strcpy(array[count++].qstring, "plenty"); -strcpy(array[count++].qstring, "of"); -strcpy(array[count++].qstring, "calcium"); -strcpy(array[count++].qstring, "Be"); -strcpy(array[count++].qstring, "kind"); -strcpy(array[count++].qstring, "to"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "knees"); -strcpy(array[count++].qstring, "Youll"); -strcpy(array[count++].qstring, "miss"); -strcpy(array[count++].qstring, "them"); -strcpy(array[count++].qstring, "when"); -strcpy(array[count++].qstring, "theyre"); -strcpy(array[count++].qstring, "gone"); -strcpy(array[count++].qstring, "Maybe"); -strcpy(array[count++].qstring, "youll"); -strcpy(array[count++].qstring, "marry"); -strcpy(array[count++].qstring, "maybe"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "wont"); -strcpy(array[count++].qstring, "Maybe"); -strcpy(array[count++].qstring, "youll"); -strcpy(array[count++].qstring, "have"); -strcpy(array[count++].qstring, "children"); -strcpy(array[count++].qstring, "maybe"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "wont"); -strcpy(array[count++].qstring, "Maybe"); -strcpy(array[count++].qstring, "youll"); -strcpy(array[count++].qstring, "divorce"); -strcpy(array[count++].qstring, "at"); -strcpy(array[count++].qstring, "40"); -strcpy(array[count++].qstring, "maybe"); -strcpy(array[count++].qstring, "youll"); -strcpy(array[count++].qstring, "dance"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "funky"); -strcpy(array[count++].qstring, "chicken"); -strcpy(array[count++].qstring, "on"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "75th"); -strcpy(array[count++].qstring, "wedding"); -strcpy(array[count++].qstring, "anniversary"); -strcpy(array[count++].qstring, "Whatever"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "do"); -strcpy(array[count++].qstring, "dont"); -strcpy(array[count++].qstring, "congratulate"); -strcpy(array[count++].qstring, "yourself"); -strcpy(array[count++].qstring, "too"); -strcpy(array[count++].qstring, "much"); -strcpy(array[count++].qstring, "or"); -strcpy(array[count++].qstring, "berate"); -strcpy(array[count++].qstring, "yourself"); -strcpy(array[count++].qstring, "either"); -strcpy(array[count++].qstring, "Your"); -strcpy(array[count++].qstring, "choices"); -strcpy(array[count++].qstring, "are"); -strcpy(array[count++].qstring, "half"); -strcpy(array[count++].qstring, "chance"); -strcpy(array[count++].qstring, "So"); -strcpy(array[count++].qstring, "are"); -strcpy(array[count++].qstring, "everybody"); -strcpy(array[count++].qstring, "elses"); -strcpy(array[count++].qstring, "Enjoy"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "body"); -strcpy(array[count++].qstring, "Use"); -strcpy(array[count++].qstring, "it"); -strcpy(array[count++].qstring, "every"); -strcpy(array[count++].qstring, "way"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "can"); -strcpy(array[count++].qstring, "Dont"); -strcpy(array[count++].qstring, "be"); -strcpy(array[count++].qstring, "afraid"); -strcpy(array[count++].qstring, "of"); -strcpy(array[count++].qstring, "it"); -strcpy(array[count++].qstring, "or"); -strcpy(array[count++].qstring, "of"); -strcpy(array[count++].qstring, "what"); -strcpy(array[count++].qstring, "other"); -strcpy(array[count++].qstring, "people"); -strcpy(array[count++].qstring, "think"); -strcpy(array[count++].qstring, "of"); -strcpy(array[count++].qstring, "it"); -strcpy(array[count++].qstring, "Its"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "greatest"); -strcpy(array[count++].qstring, "instrument"); -strcpy(array[count++].qstring, "youll"); -strcpy(array[count++].qstring, "ever"); -strcpy(array[count++].qstring, "own"); -strcpy(array[count++].qstring, "Dance"); -strcpy(array[count++].qstring, "even"); -strcpy(array[count++].qstring, "if"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "have"); -strcpy(array[count++].qstring, "nowhere"); -strcpy(array[count++].qstring, "to"); -strcpy(array[count++].qstring, "do"); -strcpy(array[count++].qstring, "it"); -strcpy(array[count++].qstring, "but"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "living"); -strcpy(array[count++].qstring, "room"); -strcpy(array[count++].qstring, "Read"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "directions"); -strcpy(array[count++].qstring, "even"); -strcpy(array[count++].qstring, "if"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "dont"); -strcpy(array[count++].qstring, "follow"); -strcpy(array[count++].qstring, "them"); -strcpy(array[count++].qstring, "Do"); -strcpy(array[count++].qstring, "not"); -strcpy(array[count++].qstring, "read"); -strcpy(array[count++].qstring, "beauty"); -strcpy(array[count++].qstring, "magazines"); -strcpy(array[count++].qstring, "They"); -strcpy(array[count++].qstring, "will"); -strcpy(array[count++].qstring, "only"); -strcpy(array[count++].qstring, "make"); -strcpy(array[count++].qstring, "you"); -strcpy(array[count++].qstring, "feel"); -strcpy(array[count++].qstring, "ugly"); -strcpy(array[count++].qstring, "Get"); -strcpy(array[count++].qstring, "to"); -strcpy(array[count++].qstring, "know"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "parents"); -strcpy(array[count++].qstring, "You"); -strcpy(array[count++].qstring, "never"); -strcpy(array[count++].qstring, "know"); -strcpy(array[count++].qstring, "when"); -strcpy(array[count++].qstring, "theyll"); -strcpy(array[count++].qstring, "be"); -strcpy(array[count++].qstring, "gone"); -strcpy(array[count++].qstring, "for"); -strcpy(array[count++].qstring, "good"); -strcpy(array[count++].qstring, "Be"); -strcpy(array[count++].qstring, "nice"); -strcpy(array[count++].qstring, "to"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "siblings"); -strcpy(array[count++].qstring, "Theyre"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "best"); -strcpy(array[count++].qstring, "link"); -strcpy(array[count++].qstring, "to"); -strcpy(array[count++].qstring, "your"); -strcpy(array[count++].qstring, "past"); -strcpy(array[count++].qstring, "and"); -strcpy(array[count++].qstring, "the"); -strcpy(array[count++].qstring, "people"); -strcpy(array[count++].qstring, "most"); -strcpy(array[count++].qstring, "likely"); -strcpy(array[count++].qstring, "to"); - - - -//printf("\nSorting %d elements.\n\n",count); - qsort(array,count,sizeof(struct myStringStruct),compare); - - //for(i=0;i --tb testbench_fp +``` +The choices for `` are as follows: + +>cvtint - test integer conversion unit (fcvtint) +cvtfp - test floating-point conversion unit (fcvtfp) +cmp - test comparison unit's LT, LE, EQ opperations (fcmp) +add - test addition +fma - test fma +mul - test mult with fma +sub - test subtraction +div - test division +sqrt - test square root + +Any config that includes floating point support can be used. Each test will test all its vectors for all precisions supported by the given config. + +### Testvector Count 46464 185856 836352 f16_add_rd.tv 46464 185856 836352 f16_add_rne.tv