From 09b2cd304f152eeec5aa3d49ee44050829e09d6b Mon Sep 17 00:00:00 2001 From: Marcus Mellor Date: Fri, 31 Mar 2023 09:51:33 -0500 Subject: [PATCH] Address comments in openhwgroup/cvw#180 --- src/fpu/fctrl.sv | 2 ++ tests/coverage/fpu.S | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index feb2034ef..9db3d670e 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -147,6 +147,7 @@ module fctrl ( 7'b0100001: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b01) ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.d.(s/h/q) // coverage off + // Not covered in testing because rv64gc does not support half or quad precision 7'b0100010: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b10) ControlsD = `FCTRLW'b1_0_01_00_010_0_0_0; // fcvt.h.(s/d/q) 7'b0100011: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b11) @@ -177,6 +178,7 @@ module fctrl ( 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.d d->lu endcase // coverage off + // Not covered in testing because rv64gc does not support half or quad precision 7'b1101010: case(Rs2D) 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.h.w w->h 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.h.wu wu->h diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S index b93b75056..3fdca6e84 100644 --- a/tests/coverage/fpu.S +++ b/tests/coverage/fpu.S @@ -38,10 +38,8 @@ main: fsh ft0, 8(a0) # Tests for fpu/fctrl.sv - ## The following cover lines 149 to 154 fcvt.h.s ft1, ft0 fcvt.q.s ft2, ft0 - ## The following cover lines 179 to 204 fcvt.h.w ft3, a0 fcvt.h.wu ft3, a0 fcvt.h.l ft3, a0