diff --git a/.gitignore b/.gitignore index 9c0f454d7..f199c8a64 100644 --- a/.gitignore +++ b/.gitignore @@ -6,6 +6,9 @@ __pycache__/ .vscode/ +#External repos +addins + #vsim work files to ignore transcript vsim.wlf @@ -38,6 +41,7 @@ wally-pipelined/linux-testgen/buildroot-config-src/main.config.old wally-pipelined/linux-testgen/buildroot-config-src/linux.config.old wally-pipelined/linux-testgen/buildroot-config-src/busybox.config.old wally-pipelined/regression/slack-notifier/slack-webhook-url.txt +wally-pipelined/regression/logs /testsBP/fpga-test-dram/bin/blink-led /testsBP/fpga-test-dram/bin/blink-led.memfile diff --git a/README.md b/README.md index 4f1afd9e2..559c3e0ee 100644 --- a/README.md +++ b/README.md @@ -5,15 +5,32 @@ Wally is a 5-stage pipelined processor configurable to support all the standard To use Wally on Linux: +``` git clone https://github.com/davidharrishmc/riscv-wally cd riscv-wally cd imperas-riscv-tests make cd ../addins git clone https://github.com/riscv-non-isa/riscv-arch-test - +git clone https://github.com/riscv-software-src/riscv-isa-sim +cd riscv-isa-sim +mkdir build +cd build +set RISCV=/cad/riscv/gcc/bin (or whatever your path is) +../configure --prefix=$RISCV +make (this will take a while to build SPIKE) +sudo make install +cd ../../riscv-arch-test +cp ../riscv-isa-sim/arch_test_target/spike/Makefile.include . +edit Makefile.include + change line with TARGETDIR to /home/harris/riscv-wally/addins/riscv-isa-sim/arch_test_target (or whatever your path is) + add line export RISCV_PREFIX = riscv64-unknown-elf- # this might not be needed if you have 32-bit versions of the riscv gcc compiler built separately +make +make XLEN=32 +exe2memfile.pl work/*/*/*.elf # converts ELF files to a format that can be read by Modelsim +``` Notes: Eventually download imperas-riscv-tests separately Move our custom tests to another directory -Handle exe2memfile separately. +Eventually replace exe2memfile.pl with objcopy diff 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b/wally-pipelined/config/buildroot/wally-config.vh index 764b88404..101c9b306 100644 --- a/wally-pipelined/config/buildroot/wally-config.vh +++ b/wally-pipelined/config/buildroot/wally-config.vh @@ -42,6 +42,7 @@ `define ZIFENCEI_SUPPORTED 1 `define ZICOUNTERS_SUPPORTED 1 `define COUNTERS 32 +`define DESIGN_COMPILER 0 // Microarchitectural Features `define UARCH_PIPELINED 1 diff --git a/wally-pipelined/config/busybear/wally-config.vh b/wally-pipelined/config/busybear/wally-config.vh index 7b3f4afbf..422da7d9e 100644 --- a/wally-pipelined/config/busybear/wally-config.vh +++ b/wally-pipelined/config/busybear/wally-config.vh @@ -41,6 +41,7 @@ `define ZIFENCEI_SUPPORTED 1 `define ZICOUNTERS_SUPPORTED 1 `define COUNTERS 32 +`define DESIGN_COMPILER 0 // Microarchitectural Features `define UARCH_PIPELINED 1 diff --git a/wally-pipelined/config/coremark/wally-config.vh b/wally-pipelined/config/coremark/wally-config.vh index d19e40e84..1c23f2fd4 100644 --- a/wally-pipelined/config/coremark/wally-config.vh +++ b/wally-pipelined/config/coremark/wally-config.vh @@ -40,6 +40,8 @@ `define ZIFENCEI_SUPPORTED 1 `define COUNTERS 32 `define ZICOUNTERS_SUPPORTED 1 +`define DESIGN_COMPILER 0 + // Microarchitectural Features `define UARCH_PIPELINED 1 diff --git a/wally-pipelined/config/coremark_bare/wally-config.vh b/wally-pipelined/config/coremark_bare/wally-config.vh index 86360c259..ff8852e60 100644 --- a/wally-pipelined/config/coremark_bare/wally-config.vh +++ b/wally-pipelined/config/coremark_bare/wally-config.vh @@ -41,6 +41,8 @@ `define ZIFENCEI_SUPPORTED 1 `define COUNTERS 32 `define ZICOUNTERS_SUPPORTED 1 +`define DESIGN_COMPILER 0 + // Microarchitectural Features `define UARCH_PIPELINED 1 diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py index 3defc260b..b560e75af 100755 --- a/wally-pipelined/regression/regression-wally.py +++ b/wally-pipelined/regression/regression-wally.py @@ -31,7 +31,7 @@ configs = [ TestCase( name="buildroot", cmd="vsim -do wally-buildroot-batch.do -c > {}", - grepstr="8500000 instructions" + grepstr="6300000 instructions" ), TestCase( name="lints", diff --git a/wally-pipelined/regression/sim-fp64 b/wally-pipelined/regression/sim-fp64 new file mode 100755 index 000000000..b6b8ba5ca --- /dev/null +++ b/wally-pipelined/regression/sim-fp64 @@ -0,0 +1 @@ +vsim -do wally-fp64.do diff --git a/wally-pipelined/regression/sim-fp64-batch b/wally-pipelined/regression/sim-fp64-batch new file mode 100755 index 000000000..693bfeb24 --- /dev/null +++ b/wally-pipelined/regression/sim-fp64-batch @@ -0,0 +1,3 @@ +vsim -c < +# Example: do wally-pipelined-batch.do rv32ic imperas-32i + +# Use this wally-pipelined-batch.do file to run this example. +# Either bring up ModelSim and type the following at the "ModelSim>" prompt: +# do wally-pipelined-batch.do +# or, to run from a shell, type the following at the shell prompt: +# vsim -do wally-pipelined-batch.do -c +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +# create library +if [file exists work_${1}_${2}] { + vdel -lib work_${1}_${2} -all +} +vlib work_${1}_${2} + +# compile source files +# suppress spurious warnngs about +# "Extra checking for conflicts with always_comb done at vopt time" +# because vsim will run vopt + +# default to config/rv64ic, but allow this to be overridden at the command line. For example: +# do wally-pipelined-batch.do ../config/rv32ic rv32ic +vlog -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-f64.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583 + +# start and run simulation +# remove +acc flag for faster sim during regressions if there is no need to access internal signals +vopt work_${1}_${2}.testbench -work work_${1}_${2} -G TEST=$2 -o testbenchopt +vsim -lib work_${1}_${2} testbenchopt +# Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time +#vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf +#vsim -coverage -lib work_$2 workopt_$2 + +run -all +#coverage report -file wally-pipelined-coverage.txt +# These aren't doing anything helpful +#coverage report -memory +#profile report -calltree -file wally-pipelined-calltree.rpt -cutoff 2 +quit diff --git a/wally-pipelined/regression/wally-fp64.do b/wally-pipelined/regression/wally-fp64.do new file mode 100644 index 000000000..c131ff16d --- /dev/null +++ b/wally-pipelined/regression/wally-fp64.do @@ -0,0 +1,54 @@ +# wally-pipelined.do +# +# Modification by Oklahoma State University & Harvey Mudd College +# Use with Testbench +# James Stine, 2008; David Harris 2021 +# Go Cowboys!!!!!! +# +# Takes 1:10 to run RV64IC tests using gui + +# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m" + +# Use this wally-pipelined.do file to run this example. +# Either bring up ModelSim and type the following at the "ModelSim>" prompt: +# do wally-pipelined.do +# or, to run from a shell, type the following at the shell prompt: +# vsim -do wally-pipelined.do -c +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +# create library +if [file exists work] { + vdel -all +} +vlib work + +# compile source files +# suppress spurious warnngs about +# "Extra checking for conflicts with always_comb done at vopt time" +# because vsim will run vopt + +# default to config/rv64ic, but allow this to be overridden at the command line. For example: +# do wally-pipelined.do ../config/rv32ic +#switch $argc { +# 0 {vlog +incdir+../config/rv64ic +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583} +# 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583} +#} +# start and run simulation +# remove +acc flag for faster sim during regressions if there is no need to access internal signals +vlog +incdir+../config/rv64g +incdir+../config/shared ../testbench/testbench-f64.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583 +vopt +acc work.testbench -G TEST=imperas64d -o workopt +vsim workopt + +view wave +-- display input and output signals as hexidecimal values +do ./wave-dos/generic.do + +-- Run the Simulation +#run 3600 +run -all +#quit +#noview ../testbench/testbench-imperas.sv +noview ../testbench/testbench.sv +view wave diff --git a/wally-pipelined/src/cache/cachereplacementpolicy.sv b/wally-pipelined/src/cache/cachereplacementpolicy.sv index 0e508ca11..01d225b1c 100644 --- a/wally-pipelined/src/cache/cachereplacementpolicy.sv +++ b/wally-pipelined/src/cache/cachereplacementpolicy.sv @@ -25,7 +25,7 @@ `include "wally-config.vh" module cachereplacementpolicy - #(NUMWAYS, INDEXLEN, OFFSETLEN, NUMLINES) + #(parameter NUMWAYS = 4, INDEXLEN = 9, OFFSETLEN = 5, NUMLINES = 128) (input logic clk, reset, input logic [NUMWAYS-1:0] WayHit, output logic [NUMWAYS-1:0] VictimWay, diff --git a/wally-pipelined/src/cache/cacheway.sv b/wally-pipelined/src/cache/cacheway.sv index 5a7c3d9e7..ad6b980d3 100644 --- a/wally-pipelined/src/cache/cacheway.sv +++ b/wally-pipelined/src/cache/cacheway.sv @@ -26,7 +26,7 @@ `include "wally-config.vh" module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26, - parameter OFFSETLEN, parameter INDEXLEN, parameter DIRTY_BITS = 1) + parameter OFFSETLEN = 5, parameter INDEXLEN = 9, parameter DIRTY_BITS = 1) (input logic clk, input logic reset, @@ -109,6 +109,9 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26, ValidBits <= {NUMLINES{1'b0}}; else if (SetValid & (WriteEnable | VDWriteEnable)) ValidBits[WAdr] <= 1'b1; else if (ClearValid & (WriteEnable | VDWriteEnable)) ValidBits[WAdr] <= 1'b0; + end + + always_ff @(posedge clk) begin Valid <= ValidBits[RAdr]; end @@ -119,6 +122,14 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26, DirtyBits <= {NUMLINES{1'b0}}; else if (SetDirty & (WriteEnable | VDWriteEnable)) DirtyBits[WAdr] <= 1'b1; else if (ClearDirty & (WriteEnable | VDWriteEnable)) DirtyBits[WAdr] <= 1'b0; + end + end + endgenerate + + // Since this is always updated on a clock edge we cannot include reset. + generate + if(DIRTY_BITS) begin + always_ff @(posedge clk) begin Dirty <= DirtyBits[RAdr]; end end else begin diff --git a/wally-pipelined/src/cache/dcachefsm.sv b/wally-pipelined/src/cache/dcachefsm.sv index 6cac35aee..1a8e632d8 100644 --- a/wally-pipelined/src/cache/dcachefsm.sv +++ b/wally-pipelined/src/cache/dcachefsm.sv @@ -146,18 +146,7 @@ module dcachefsm always_ff @(posedge clk, posedge reset) if (reset) CurrState <= #1 STATE_READY; - else CurrState <= #1 NextState; - -/* -----\/----- EXCLUDED -----\/----- - flopenl #(.TYPE(statetype)) - StateReg(.clk, - .load(reset), - .en(1'b1), - .d(NextState), - .q(CurrState), - .val(STATE_READY)); - -----/\----- EXCLUDED -----/\----- */ - + else CurrState <= #1 NextState; // next state logic and some state ouputs. always_comb begin diff --git a/wally-pipelined/src/fpu/cvtfp.sv b/wally-pipelined/src/fpu/cvtfp.sv index a8fd2bc4c..fb9f5cf1f 100644 --- a/wally-pipelined/src/fpu/cvtfp.sv +++ b/wally-pipelined/src/fpu/cvtfp.sv @@ -1,24 +1,42 @@ // `include "wally-config.vh" module cvtfp ( - input logic [10:0] XExpE, - input logic [52:0] XManE, - input logic XSgnE, - input logic XZeroE, - input logic XDenormE, - input logic XInfE, - input logic XNaNE, - input logic XSNaNE, - input logic [2:0] FrmE, - input logic FmtE, - output logic [63:0] CvtFpResE, - output logic [4:0] CvtFpFlgE); + input logic [10:0] XExpE, // input's exponent + input logic [52:0] XManE, // input's mantissa + input logic XSgnE, // input's sign + input logic XZeroE, // is the input zero + input logic XDenormE, // is the input denormalized + input logic XInfE, // is the input infinity + input logic XNaNE, // is the input a NaN + input logic XSNaNE, // is the input a signaling NaN + input logic [2:0] FrmE, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude + input logic FmtE, // the input's precision (1 = double 0 = single) + output logic [63:0] CvtFpResE, // the fp to fp conversion's result + output logic [4:0] CvtFpFlgE); // the fp to fp conversion's flags - logic [7:0] DExp; - logic [51:0] Frac; - logic Denorm; + logic [12:0] DSExp; // double to single precision exponent + logic Denorm; // is the double to single precision result denormalized + logic Shift; // do you shift the double precision exponent (if single precision result is denormalized) + logic [51:0] SDFrac; // single to double precision fraction + logic [25:0] DSFrac; // double to single precision fraction + logic [77:0] DSFracShifted; // single precision fraction shifted for double precision + logic Sticky, UfSticky, Guard, Round, LSBFrac, UfGuard, UfRound, UfLSBFrac; // rounding bits + logic CalcPlus1, UfCalcPlus1, Plus1, UfPlus1; // do you add one to the result + logic [12:0] DSExpFull; // full double to single exponent + logic [22:0] DSResFrac; // final double to single fraction + logic [7:0] DSResExp; // final double to single exponent + logic [10:0] SDExp; // final single to double precision exponent + logic Overflow, Underflow, Inexact; // flags + logic [31:0] DSRes; // double to single precision result + + /////////////////////////////////////////////////////////////////////////////// + // LZC + /////////////////////////////////////////////////////////////////////////////// + + + // LZC - find the first 1 in the input's mantissa logic [8:0] i,NormCnt; always_comb begin i = 0; @@ -27,42 +45,62 @@ module cvtfp ( end + /////////////////////////////////////////////////////////////////////////////// + // Expoents + /////////////////////////////////////////////////////////////////////////////// + + // convert the single precion exponent to single precision. + // - subtract the double precision exponent (1023) and add the + // single precsision exponent (127) + // - if the input is zero then kill the exponent + + assign DSExp = ({2'b0,XExpE}-13'd1023+13'd127)&{13{~XZeroE}}; + + // is the converted double to single precision exponent in the denormalized range + assign Denorm = $signed(DSExp) <= 0 & $signed(DSExp) > $signed(-(13'd23)); + + + // caluculate the final single to double precsion exponent + // - subtract the single precision bias (127) and add the double + // precision bias (127) + // - if the result is zero or denormalized, kill the exponent + assign SDExp = XExpE-({2'b0,NormCnt&{9{~XZeroE}}})+({11{XDenormE}}&1024-127); //*** seems ineffecient + /////////////////////////////////////////////////////////////////////////////// + // Fraction + /////////////////////////////////////////////////////////////////////////////// + + + // normalize the single precision fraction for double precsion + // - needed for denormal single precsion values + assign SDFrac = XManE[51:0] << NormCnt; + + // check if the double precision mantissa needs to be shifted + // - the mantissa needs to be shifted if the single precision result is denormal + assign Shift = Denorm | (($signed(DSExp) > $signed(-(13'd25))) & DSExp[12]); + // shift the mantissa + assign DSFracShifted = {XManE, 25'b0} >> ((-DSExp+1)&{13{Shift}}); //***might be some optimization here + assign DSFrac = DSFracShifted[76:51]; - logic [12:0] DExpCalc; - // logic Overflow, Underflow; - assign DExpCalc = (XExpE-1023+127)&{13{~XZeroE}}; - assign Denorm = $signed(DExpCalc) <= 0 & $signed(DExpCalc) > $signed(-23); + /////////////////////////////////////////////////////////////////////////////// + // Rounder + /////////////////////////////////////////////////////////////////////////////// - logic [12:0] ShiftCnt; - logic [51:0] SFrac; - logic [25:0] DFrac; - logic [77:0] DFracTmp; - //assign ShiftCnt = FmtE ? -DExpCalc&{13{Denorm}} : NormCnt; - assign SFrac = XManE[51:0] << NormCnt; -logic Shift; -assign Shift = {13{Denorm|(($signed(DExpCalc) > $signed(-25)) & DExpCalc[12])}}; - assign DFracTmp = {XManE, 25'b0} >> ((-DExpCalc+1)&{13{Shift}}); -assign DFrac = DFracTmp[76:51]; - - logic Sticky, UfSticky, Guard, Round, LSBFrac, UfGuard, UfRound, UfLSBFrac; - logic CalcPlus1, UfCalcPlus1; - logic Plus1, UfPlus1; // used to determine underflow flag - assign UfSticky = |DFracTmp[50:0]; - assign UfGuard = DFrac[1]; - assign UfRound = DFrac[0]; - assign UfLSBFrac = DFrac[2]; + assign UfSticky = |DSFracShifted[50:0]; + assign UfGuard = DSFrac[1]; + assign UfRound = DSFrac[0]; + assign UfLSBFrac = DSFrac[2]; assign Sticky = UfSticky | UfRound; - assign Guard = DFrac[2]; - assign Round = DFrac[1]; - assign LSBFrac = DFrac[3]; + assign Guard = DSFrac[2]; + assign Round = DSFrac[1]; + assign LSBFrac = DSFrac[3]; always_comb begin @@ -87,32 +125,48 @@ assign DFrac = DFracTmp[76:51]; end - // If an answer is exact don't round + // if an answer is exact don't round assign Plus1 = CalcPlus1 & (Sticky | UfGuard | Guard | Round); assign UfPlus1 = UfCalcPlus1 & (Sticky | UfGuard); - logic [12:0] DExpFull; -logic [22:0] DResFrac; -logic [7:0] DResExp; - assign {DExpFull, DResFrac} = {DExpCalc&{13{~Denorm}}, DFrac[25:3]} + Plus1; - assign DResExp = DExpFull[7:0]; - logic [10:0] SExp; - assign SExp = XExpE-(NormCnt&{8{~XZeroE}})+({11{XDenormE}}&1024-127); - logic Overflow, Underflow, Inexact; - assign Overflow = $signed(DExpFull) >= $signed({1'b0, {8{1'b1}}}) & ~(XNaNE|XInfE); - assign Underflow = (($signed(DExpFull) <= 0) & ((Sticky|Guard|Round) | (XManE[52]&~|DFrac) | (|DFrac&~Denorm)) | ((DExpFull == 1) & Denorm & ~(UfPlus1&UfLSBFrac))) & ~(XNaNE|XInfE); + + // round the double to single precision result + assign {DSExpFull, DSResFrac} = {DSExp&{13{~Denorm}}, DSFrac[25:3]} + {35'b0,Plus1}; + assign DSResExp = DSExpFull[7:0]; + + + /////////////////////////////////////////////////////////////////////////////// + // Flags + /////////////////////////////////////////////////////////////////////////////// + + // calculate the flags + // - overflow, underflow and inexact can only be set by the double to single precision opperation + // - don't set underflow or overflow if the input is NaN or Infinity + // - don't set the inexact flag if the input is NaN + assign Overflow = $signed(DSExpFull) >= $signed({5'b0, {8{1'b1}}}) & ~(XNaNE|XInfE); + assign Underflow = (($signed(DSExpFull) <= 0) & ((Sticky|Guard|Round) | (XManE[52]&~|DSFrac) | (|DSFrac&~Denorm)) | ((DSExpFull == 1) & Denorm & ~(UfPlus1&UfLSBFrac))) & ~(XNaNE|XInfE); assign Inexact = (Sticky|Guard|Round|Underflow|Overflow) &~(XNaNE); - -logic [31:0] DRes; - assign DRes = XNaNE ? {XSgnE, XExpE, 1'b1, XManE[50:29]} : - Underflow & ~Denorm ? {XSgnE, 30'b0, CalcPlus1&(|FrmE[1:0]|Shift)} : - Overflow | XInfE ? ((FrmE[1:0]==2'b01) | (FrmE[1:0]==2'b10&~XSgnE) | (FrmE[1:0]==2'b11&XSgnE)) & ~XInfE ? {XSgnE, 8'hfe, {23{1'b1}}} : - {XSgnE, 8'hff, 23'b0} : - {XSgnE, DResExp, DResFrac}; - assign CvtFpResE = FmtE ? {{32{1'b1}},DRes} : {XSgnE, SExp, SFrac[51]|XNaNE, SFrac[50:0]}; + + // pack the flags together and choose the result based on the opperation assign CvtFpFlgE = FmtE ? {XSNaNE, 1'b0, Overflow, Underflow, Inexact} : {XSNaNE, 4'b0}; + + + /////////////////////////////////////////////////////////////////////////////// + // Result Selection + /////////////////////////////////////////////////////////////////////////////// + + // select the double to single precision result + assign DSRes = XNaNE ? {XSgnE, {8{1'b1}}, 1'b1, XManE[50:29]} : + Underflow & ~Denorm ? {XSgnE, 30'b0, CalcPlus1&(|FrmE[1:0]|Shift)} : + Overflow | XInfE ? ((FrmE[1:0]==2'b01) | (FrmE[1:0]==2'b10&~XSgnE) | (FrmE[1:0]==2'b11&XSgnE)) & ~XInfE ? {XSgnE, 8'hfe, {23{1'b1}}} : + {XSgnE, 8'hff, 23'b0} : + {XSgnE, DSResExp, DSResFrac}; + + // select the final result based on the opperation + assign CvtFpResE = FmtE ? {{32{1'b1}},DSRes} : {XSgnE, SDExp, SDFrac[51]|XNaNE, SDFrac[50:0]}; + endmodule // fpadd diff --git a/wally-pipelined/src/fpu/divconv.sv b/wally-pipelined/src/fpu/divconv.sv index 271cd69a1..7fa89c82e 100755 --- a/wally-pipelined/src/fpu/divconv.sv +++ b/wally-pipelined/src/fpu/divconv.sv @@ -1,102 +1,121 @@ -module divconv ( +/////////////////////////////////////////// +// +// Written: James Stine +// Modified: 9/28/2021 +// +// Purpose: Main convergence routine for floating point divider/square root unit (Goldschmidt) +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// - input logic [52:0] d, n, +module divconv ( + input logic [52:0] d, n, input logic [2:0] sel_muxa, sel_muxb, - input logic sel_muxr, - input logic load_rega, load_regb, load_regc, load_regd, - input logic load_regr, load_regs, - input logic P, - input logic op_type, - input logic exp_odd, - input logic reset, - input logic clk, - - output logic [63:0] q1, qp1, qm1, - output logic [63:0] q0, qp0, qm0, - output logic [63:0] rega_out, regb_out, regc_out, regd_out, - output logic [127:0] regr_out + input logic sel_muxr, + input logic load_rega, load_regb, load_regc, load_regd, + input logic load_regr, load_regs, + input logic P, + input logic op_type, + input logic exp_odd, + input logic reset, + input logic clk, + + output logic [59:0] q1, qp1, qm1, + output logic [59:0] q0, qp0, qm0, + output logic [59:0] rega_out, regb_out, regc_out, regd_out, + output logic [119:0] regr_out ); - logic [63:0] muxa_out, muxb_out; + logic [59:0] muxa_out, muxb_out; logic [10:0] ia_div, ia_sqrt; - logic [63:0] ia_out; - logic [127:0] mul_out; - logic [63:0] q_out1, qm_out1, qp_out1; - logic [63:0] q_out0, qm_out0, qp_out0; - logic [63:0] mcand, mplier, mcand_q; - logic [63:0] twocmp_out; - logic [64:0] three; - logic [127:0] Carry, Carry2; - logic [127:0] Sum, Sum2; - logic [127:0] constant, constant2; - logic [63:0] q_const, qp_const, qm_const; - logic [63:0] d2, n2; - logic [11:0] d3; - logic muxr_out; - logic cout1, cout2, cout3, cout4, cout5, cout6, cout7; + logic [59:0] ia_out; + logic [119:0] mul_out; + logic [59:0] q_out1, qm_out1, qp_out1; + logic [59:0] q_out0, qm_out0, qp_out0; + logic [59:0] mcand, mplier, mcand_q; + logic [59:0] twocmp_out; + logic [60:0] three; + logic [119:0] constant, constant2; + logic [59:0] q_const, qp_const, qm_const; + logic [59:0] d2, n2; + logic muxr_out; + logic cout1, cout2, cout3, cout4, cout5, cout6, cout7; // Check if exponent is odd for sqrt // If exp_odd=1 and sqrt, then M/2 and use ia_addr=0 as IA - assign d2 = (exp_odd&op_type) ? {1'b0,d,10'h0} : {d,11'h0}; - assign n2 = op_type ? d2 : {n,11'h0}; + assign d2 = (exp_odd&op_type) ? {1'b0, d, 6'h0} : {d, 7'h0}; + assign n2 = op_type ? d2 : {n, 7'h0}; // IA div/sqrt sbtm_div ia1 (d[52:41], ia_div); - sbtm_sqrt ia2 (d2[63:52], ia_sqrt); - assign ia_out = op_type ? {ia_sqrt, {53{1'b0}}} : {ia_div, {53{1'b0}}}; + sbtm_sqrt ia2 (d2[59:48], ia_sqrt); + assign ia_out = op_type ? {ia_sqrt, {49{1'b0}}} : {ia_div, {49{1'b0}}}; // Choose IA or iteration - mux6 #(64) mx1 (d2, ia_out, rega_out, regc_out, regd_out, regb_out, sel_muxb, muxb_out); - mux5 #(64) mx2 (regc_out, n2, ia_out, regb_out, regd_out, sel_muxa, muxa_out); + mux6 #(60) mx1 (d2, ia_out, rega_out, regc_out, regd_out, regb_out, sel_muxb, muxb_out); + mux5 #(60) mx2 (regc_out, n2, ia_out, regb_out, regd_out, sel_muxa, muxa_out); // Deal with remainder if [0.5, 1) instead of [1, 2) - mux2 #(128) mx3a ({~n, {75{1'b1}}}, {{1'b1}, ~n, {74{1'b1}}}, q1[63], constant2); + mux2 #(120) mx3a ({~n, {67{1'b1}}}, {{1'b1}, ~n, {66{1'b1}}}, q1[59], constant2); // Select Mcand, Remainder/Q'' - mux2 #(128) mx3 (128'h0, constant2, sel_muxr, constant); + mux2 #(120) mx3 (120'h0, constant2, sel_muxr, constant); // Select mcand - remainder should always choose q1 [1,2) because // adjustment of N in the from XX.FFFFFFF - mux2 #(64) mx4 (q0, q1, q1[63], mcand_q); - mux2 #(64) mx5 (muxb_out, mcand_q, sel_muxr&op_type, mplier); - mux2 #(64) mx6 (muxa_out, mcand_q, sel_muxr, mcand); + mux2 #(60) mx4 (q0, q1, q1[59], mcand_q); + mux2 #(60) mx5 (muxb_out, mcand_q, sel_muxr&op_type, mplier); + mux2 #(60) mx6 (muxa_out, mcand_q, sel_muxr, mcand); // Q*D - N (reversed but changed in rounder.v to account for sign reversal) // Add ulp for subtraction in remainder mux2 #(1) mx7 (1'b0, 1'b1, sel_muxr, muxr_out); // Constant for Q'' - mux2 #(64) mx8 ({64'h0000_0000_0000_0200}, {64'h0000_0040_0000_0000}, P, q_const); - mux2 #(64) mx9 ({64'h0000_0000_0000_0A00}, {64'h0000_0140_0000_0000}, P, qp_const); - mux2 #(64) mxA ({64'hFFFF_FFFF_FFFF_F9FF}, {64'hFFFF_FF3F_FFFF_FFFF}, P, qm_const); + mux2 #(60) mx8 ({60'h0000_0000_0000_020}, {60'h0000_0040_0000_000}, P, q_const); + mux2 #(60) mx9 ({60'h0000_0000_0000_0A0}, {60'h0000_0140_0000_000}, P, qp_const); + mux2 #(60) mxA ({60'hFFFF_FFFF_FFFF_F9F}, {60'hFFFF_FF3F_FFFF_FFF}, P, qm_const); // CPA (from CSA)/Remainder addition/subtraction - assign {cout1, mul_out} = (mcand*mplier) + constant + muxr_out; + assign {cout1, mul_out} = (mcand*mplier) + constant + {118'b0, muxr_out}; // Assuming [1,2) - q1 assign {cout2, q_out1} = regb_out + q_const; assign {cout3, qp_out1} = regb_out + qp_const; assign {cout4, qm_out1} = regb_out + qm_const + 1'b1; // Assuming [0.5,1) - q0 - assign {cout5, q_out0} = {regb_out[62:0], 1'b0} + q_const; - assign {cout6, qp_out0} = {regb_out[62:0], 1'b0} + qp_const; - assign {cout7, qm_out0} = {regb_out[62:0], 1'b0} + qm_const + 1'b1; + assign {cout5, q_out0} = {regb_out[58:0], 1'b0} + q_const; + assign {cout6, qp_out0} = {regb_out[58:0], 1'b0} + qp_const; + assign {cout7, qm_out0} = {regb_out[58:0], 1'b0} + qm_const + 1'b1; // One's complement instead of two's complement (for hw efficiency) - assign three = {~mul_out[126], mul_out[126], ~mul_out[125:63]}; - mux2 #(64) mxTC (~mul_out[126:63], three[64:1], op_type, twocmp_out); + assign three = {~mul_out[118], mul_out[118], ~mul_out[117:59]}; + mux2 #(60) mxTC (~mul_out[118:59], three[60:1], op_type, twocmp_out); // regs - flopenr #(64) regc (clk, reset, load_regc, twocmp_out, regc_out); - flopenr #(64) regb (clk, reset, load_regb, mul_out[126:63], regb_out); - flopenr #(64) rega (clk, reset, load_rega, mul_out[126:63], rega_out); - flopenr #(64) regd (clk, reset, load_regd, mul_out[126:63], regd_out); - flopenr #(128) regr (clk, reset, load_regr, mul_out, regr_out); + flopenr #(60) regc (clk, reset, load_regc, twocmp_out, regc_out); + flopenr #(60) regb (clk, reset, load_regb, mul_out[118:59], regb_out); + flopenr #(60) rega (clk, reset, load_rega, mul_out[118:59], rega_out); + flopenr #(60) regd (clk, reset, load_regd, mul_out[118:59], regd_out); + flopenr #(120) regr (clk, reset, load_regr, mul_out, regr_out); // Assuming [1,2) - flopenr #(64) rege (clk, reset, load_regs, {q_out1[63:39], (q_out1[38:10] & {29{~P}}), 10'h0}, q1); - flopenr #(64) regf (clk, reset, load_regs, {qm_out1[63:39], (qm_out1[38:10] & {29{~P}}), 10'h0}, qm1); - flopenr #(64) regg (clk, reset, load_regs, {qp_out1[63:39], (qp_out1[38:10] & {29{~P}}), 10'h0}, qp1); + flopenr #(60) rege (clk, reset, load_regs, {q_out1[59:35], (q_out1[34:6] & {29{~P}}), 6'h0}, q1); + flopenr #(60) regf (clk, reset, load_regs, {qm_out1[59:35], (qm_out1[34:6] & {29{~P}}), 6'h0}, qm1); + flopenr #(60) regg (clk, reset, load_regs, {qp_out1[59:35], (qp_out1[34:6] & {29{~P}}), 6'h0}, qp1); // Assuming [0,1) - flopenr #(64) regh (clk, reset, load_regs, {q_out0[63:39], (q_out0[38:10] & {29{~P}}), 10'h0}, q0); - flopenr #(64) regj (clk, reset, load_regs, {qm_out0[63:39], (qm_out0[38:10] & {29{~P}}), 10'h0}, qm0); - flopenr #(64) regk (clk, reset, load_regs, {qp_out0[63:39], (qp_out0[38:10] & {29{~P}}), 10'h0}, qp0); + flopenr #(60) regh (clk, reset, load_regs, {q_out0[59:35], (q_out0[34:6] & {29{~P}}), 6'h0}, q0); + flopenr #(60) regj (clk, reset, load_regs, {qm_out0[59:35], (qm_out0[34:6] & {29{~P}}), 6'h0}, qm0); + flopenr #(60) regk (clk, reset, load_regs, {qp_out0[59:35], (qp_out0[34:6] & {29{~P}}), 6'h0}, qp0); endmodule // divconv - diff --git a/wally-pipelined/src/fpu/divconv_pipe.sv b/wally-pipelined/src/fpu/divconv_pipe.sv new file mode 100755 index 000000000..4e3b843d6 --- /dev/null +++ b/wally-pipelined/src/fpu/divconv_pipe.sv @@ -0,0 +1,175 @@ +/////////////////////////////////////////// +// +// Written: James Stine +// Modified: 8/1/2018 +// +// Purpose: Convergence unit for pipelined floating point divider/square root top unit (Goldschmidt) +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +`include "wally-config.vh" + +module divconv_pipe (q1, qm1, qp1, q0, qm0, qp0, rega_out, regb_out, regc_out, regd_out, + regr_out, d, n, sel_muxa, sel_muxb, sel_muxr, reset, clk, + load_rega, load_regb, load_regc, load_regd, load_regr, load_regs, load_regp, + P, op_type, exp_odd); + + input logic [52:0] d, n; + input logic [2:0] sel_muxa, sel_muxb; + input logic sel_muxr; + input logic load_rega, load_regb, load_regc, load_regd; + input logic load_regr, load_regs; + input logic load_regp; + input logic P; + input logic op_type; + input logic exp_odd; + input logic reset; + input logic clk; + + output logic [59:0] q1, qp1, qm1; + output logic [59:0] q0, qp0, qm0; + output logic [59:0] rega_out, regb_out, regc_out, regd_out; + output logic [119:0] regr_out; + + supply1 vdd; + supply0 vss; + + logic [59:0] muxa_out, muxb_out; + logic [10:0] ia_div, ia_sqrt; + logic [59:0] ia_out; + logic [119:0] mul_out; + logic [59:0] q_out1, qm_out1, qp_out1; + logic [59:0] q_out0, qm_out0, qp_out0; + logic [59:0] mcand, mplier, mcand_q; + logic [59:0] twocmp_out; + logic [60:0] three; + logic [119:0] Carry, Carry2; + logic [119:0] Sum, Sum2; + logic [119:0] constant, constant2; + logic [59:0] q_const, qp_const, qm_const; + logic [59:0] d2, n2; + logic [11:0] d3; + + // Check if exponent is odd for sqrt + // If exp_odd=1 and sqrt, then M/2 and use ia_addr=0 as IA + assign d2 = (exp_odd&op_type) ? {vss,d,6'h0} : {d,7'h0}; + assign n2 = op_type ? d2 : {n,7'h0}; + + // IA div/sqrt + sbtm_div ia1 (d[52:41], ia_div); + sbtm_sqrt ia2 (d2[59:48], ia_sqrt); + assign ia_out = op_type ? {ia_sqrt, {49{1'b0}}} : {ia_div, {49{1'b0}}}; + + // Choose IA or iteration + mux6 #(60) mx1 (d2, ia_out, rega_out, regc_out, regd_out, regb_out, sel_muxb, muxb_out); + mux5 #(60) mx2 (regc_out, n2, ia_out, regb_out, regd_out, sel_muxa, muxa_out); + + // Deal with remainder if [0.5, 1) instead of [1, 2) + mux2 #(120) mx3a ({~n, {67{1'b1}}}, {{1'b1}, ~n, {66{1'b1}}}, q1[59], constant2); + // Select Mcand, Remainder/Q'' + mux2 #(120) mx3 (120'h0, constant2, sel_muxr, constant); + // Select mcand - remainder should always choose q1 [1,2) because + // adjustment of N in the from XX.FFFFFFF + mux2 #(60) mx4 (q0, q1, q1[59], mcand_q); + mux2 #(60) mx5 (muxb_out, mcand_q, sel_muxr&op_type, mplier); + mux2 #(60) mx6 (muxa_out, mcand_q, sel_muxr, mcand); + // R4 Booth TDM multiplier (carry/save) + redundantmul #(60) bigmul(.a(mcand), .b(mplier), .out0(Sum), .out1(Carry)); + // Q*D - N (reversed but changed in rounder.v to account for sign reversal) + csa #(120) csa1 (Sum, Carry, constant, Sum2, Carry2); + // Add ulp for subtraction in remainder + mux2 #(1) mx7 (1'b0, 1'b1, sel_muxr, muxr_out); + + // Constant for Q'' + mux2 #(60) mx8 ({60'h0000_0000_0000_020}, {60'h0000_0040_0000_000}, P, q_const); + mux2 #(60) mx9 ({60'h0000_0000_0000_0A0}, {60'h0000_0140_0000_000}, P, qp_const); + mux2 #(60) mxA ({60'hFFFF_FFFF_FFFF_F9F}, {60'hFFFF_FF3F_FFFF_FFF}, P, qm_const); + + logic [119:0] Sum_pipe; + logic [119:0] Carry_pipe; + logic muxr_pipe; + logic rega_pipe; + logic regb_pipe; + logic regc_pipe; + logic regd_pipe; + logic regs_pipe; + logic regs_pipe2; + logic regr_pipe; + logic P_pipe; + logic op_type_pipe; + logic [59:0] q_const_pipe; + logic [59:0] qm_const_pipe; + logic [59:0] qp_const_pipe; + logic [59:0] q_const_pipe2; + logic [59:0] qm_const_pipe2; + logic [59:0] qp_const_pipe2; + + // Stage 1 + flopenr #(120) regp1 (clk, reset, load_regp, Sum2, Sum_pipe); + flopenr #(120) regp2 (clk, reset, load_regp, Carry2, Carry_pipe); + flopenr #(1) regp3 (clk, reset, load_regp, muxr_out, muxr_pipe); + + flopenr #(1) regp4 (clk, reset, load_regp, load_rega, rega_pipe); + flopenr #(1) regp5 (clk, reset, load_regp, load_regb, regb_pipe); + flopenr #(1) regp6 (clk, reset, load_regp, load_regc, regc_pipe); + flopenr #(1) regp7 (clk, reset, load_regp, load_regd, regd_pipe); + flopenr #(1) regp8 (clk, reset, load_regp, load_regs, regs_pipe); + flopenr #(1) regp9 (clk, reset, load_regp, load_regr, regr_pipe); + flopenr #(1) regpA (clk, reset, load_regp, P, P_pipe); + flopenr #(1) regpB (clk, reset, load_regp, op_type, op_type_pipe); + flopenr #(60) regpC (clk, reset, load_regp, q_const, q_const_pipe); + flopenr #(60) regpD (clk, reset, load_regp, qp_const, qp_const_pipe); + flopenr #(60) regpE (clk, reset, load_regp, qm_const, qm_const_pipe); + + // CPA (from CSA)/Remainder addition/subtraction + assign {cout1, mul_out} = Sum_pipe + Carry_pipe + muxr_pipe; + // One's complement instead of two's complement (for hw efficiency) + assign three = {~mul_out[118] , mul_out[118], ~mul_out[117:59]}; + mux2 #(60) mxTC (~mul_out[118:59], three[60:1], op_type_pipe, twocmp_out); + + // Stage 2 + flopenr #(60) regc (clk, reset, regc_pipe, twocmp_out, regc_out); + flopenr #(60) regb (clk, reset, regb_pipe, mul_out[118:59], regb_out); + flopenr #(60) rega (clk, reset, rega_pipe, mul_out[118:59], rega_out); + flopenr #(60) regd (clk, reset, regd_pipe, mul_out[118:59], regd_out); + flopenr #(120) regr (clk, reset, regr_pipe, mul_out, regr_out); + flopenr #(1) regl (clk, reset, regs_pipe, regs_pipe, regs_pipe2); + flopenr #(60) regm (clk, reset, regs_pipe, q_const_pipe, q_const_pipe2); + flopenr #(60) regn (clk, reset, regs_pipe, qp_const_pipe, qp_const_pipe2); + flopenr #(60) rego (clk, reset, regs_pipe, qm_const_pipe, qm_const_pipe2); + + // Assuming [1,2) - q1 + assign {cout2, q_out1} = regb_out + q_const; + assign {cout3, qp_out1} = regb_out + qp_const; + assign {cout4, qm_out1} = regb_out + qm_const + 1'b1; + // Assuming [0.5,1) - q0 + assign {cout5, q_out0} = {regb_out[58:0], 1'b0} + q_const; + assign {cout6, qp_out0} = {regb_out[58:0], 1'b0} + qp_const; + assign {cout7, qm_out0} = {regb_out[58:0], 1'b0} + qm_const + 1'b1; + + // Stage 3 + // Assuming [1,2) + flopenr #(60) rege (clk, reset, regs_pipe2, {q_out1[59:35], (q_out1[34:6] & {29{~P_pipe}}), 6'h0}, q1); + flopenr #(60) regf (clk, reset, regs_pipe2, {qm_out1[59:35], (qm_out1[34:6] & {29{~P_pipe}}), 6'h0}, qm1); + flopenr #(60) regg (clk, reset, regs_pipe2, {qp_out1[59:35], (qp_out1[34:6] & {29{~P_pipe}}), 6'h0}, qp1); + // Assuming [0,1) + flopenr #(60) regh (clk, reset, regs_pipe2, {q_out0[59:35], (q_out0[34:6] & {29{~P_pipe}}), 6'h0}, q0); + flopenr #(60) regj (clk, reset, regs_pipe2, {qm_out0[59:35], (qm_out0[34:6] & {29{~P_pipe}}), 6'h0}, qm0); + flopenr #(60) regk (clk, reset, regs_pipe2, {qp_out0[59:35], (qp_out0[34:6] & {29{~P_pipe}}), 6'h0}, qp0); + +endmodule // divconv diff --git a/wally-pipelined/src/fpu/fctrl.sv b/wally-pipelined/src/fpu/fctrl.sv index a109ed67c..6fd29a2b8 100755 --- a/wally-pipelined/src/fpu/fctrl.sv +++ b/wally-pipelined/src/fpu/fctrl.sv @@ -17,7 +17,7 @@ module fctrl ( output logic FWriteIntD // is the result written to the integer register ); - `define FCTRLW 15 + `define FCTRLW 14 logic [`FCTRLW-1:0] ControlsD; // FPU Instruction Decoder always_comb @@ -69,7 +69,7 @@ module fctrl ( 2'b01: ControlsD = `FCTRLW'b1_0_11_010_011_00_0_0; // fcvt.s.wu 2'b10: ControlsD = `FCTRLW'b1_0_11_100_011_00_0_0; // fcvt.s.l 2'b11: ControlsD = `FCTRLW'b1_0_11_110_011_00_0_0; // fcvt.s.lu - default: ControlsD = `FCTRLW'b0_0_00_0000_000_00_0_1; // non-implemented instruction + default: ControlsD = `FCTRLW'b0_0_00_000_000_00_0_1; // non-implemented instruction endcase 7'b1100000: case(Rs2D[1:0]) 2'b00: ControlsD = `FCTRLW'b0_1_11_001_011_11_0_0; // fcvt.w.s @@ -98,7 +98,7 @@ module fctrl ( //7'b0100001: ControlsD = `FCTRLW'b1_0_11_000_100_00_0_0; // fcvt.d.s default: ControlsD = `FCTRLW'b0_0_00_000_100_00_0_1; // non-implemented instruction endcase - default: ControlsD = `FCTRLW'b0_0_000_000_000_00_0_1; // non-implemented instruction + default: ControlsD = `FCTRLW'b0_0_00_000_000_00_0_1; // non-implemented instruction endcase // unswizzle control bits diff --git a/wally-pipelined/src/fpu/fcvt.sv b/wally-pipelined/src/fpu/fcvt.sv index 17da80306..479da90c4 100644 --- a/wally-pipelined/src/fpu/fcvt.sv +++ b/wally-pipelined/src/fpu/fcvt.sv @@ -68,7 +68,7 @@ module fcvt ( assign Bits = Res64 ? 8'd64 : 8'd32; // calulate the unbiased exponent - assign ExpVal = XExpE - BiasE + XDenormE; + assign ExpVal = {1'b0,XExpE} - {1'b0,BiasE} + {12'b0, XDenormE}; //////////////////////////////////////////////////////// @@ -84,11 +84,11 @@ module fcvt ( always_comb begin i = 0; while (~PosInt[64-1-i] && i < `XLEN) i = i+1; // search for leading one - LZResP = i+1; // compute shift count + LZResP = i[5:0]+1; // compute shift count end // if no one was found set to zero otherwise calculate the exponent - assign TmpExp = i==`XLEN ? 0 : FmtE ? 1023 + SubBits - LZResP : 127 + SubBits - LZResP; + assign TmpExp = i==`XLEN ? 0 : FmtE ? 11'd1023 + {3'b0, SubBits} - {5'b0, LZResP} : 11'd127 + {3'b0, SubBits} - {5'b0, LZResP}; @@ -97,13 +97,13 @@ module fcvt ( // select the shift value and amount based on operation (to fp or int) - assign ShiftCnt = FOpCtrlE[0] ? ExpVal : LZResP; - assign ShiftVal = FOpCtrlE[0] ? {{64-2{1'b0}}, XManE} : {PosInt, 52'b0}; + assign ShiftCnt = FOpCtrlE[0] ? ExpVal : {7'b0, LZResP}; + assign ShiftVal = FOpCtrlE[0] ? {{64-1{1'b0}}, XManE} : {PosInt, 52'b0}; // if shift = -1 then shift one bit right for gaurd bit (right shifting twice never rounds) // if the shift is negitive add a bit for sticky bit calculation // otherwise shift left - assign ShiftedManTmp = &ShiftCnt ? {{64-1{1'b0}}, XManE[52:1]} : ShiftCnt[12] ? {{64+51{1'b0}}, ~XZeroE} : ShiftVal << ShiftCnt; + assign ShiftedManTmp = &ShiftCnt ? {{64{1'b0}}, XManE[52:1]} : ShiftCnt[12] ? {{64+51{1'b0}}, ~XZeroE} : ShiftVal << ShiftCnt; // truncate the shifted mantissa assign ShiftedMan = ShiftedManTmp[64+51:50]; @@ -135,8 +135,8 @@ module fcvt ( assign Plus1 = CalcPlus1 & (Guard|Round|Sticky)&~(XZeroE&FOpCtrlE[0]); // round the shifted mantissa - assign RoundedTmp = ShiftedMan[64+1:2] + Plus1; - assign {ResExp, ResFrac} = FmtE ? {TmpExp, ShiftedMan[64+1:14]} + Plus1 : {{TmpExp, ShiftedMan[64+1:43]} + Plus1, 29'b0} ; + assign RoundedTmp = ShiftedMan[64+1:2] + {64'b0, Plus1}; + assign {ResExp, ResFrac} = FmtE ? {TmpExp, ShiftedMan[64+1:14]} + {62'b0, Plus1} : {{TmpExp, ShiftedMan[64+1:43]} + {33'b0,Plus1}, 29'b0} ; // fit the rounded result into the appropriate size and take the 2's complement if needed assign Rounded = Res64 ? XSgnE&FOpCtrlE[0] ? -RoundedTmp[63:0] : RoundedTmp[63:0] : @@ -148,10 +148,10 @@ module fcvt ( // check if the result overflows - assign Of = (~XSgnE&($signed(ShiftCnt) >= $signed(Bits))) | (~XSgnE&RoundSgn&~FOpCtrlE[1]) | (RoundMSB&(ShiftCnt==(Bits-1))) | (~XSgnE&XInfE) | XNaNE; + assign Of = (~XSgnE&($signed(ShiftCnt) >= $signed({{5{Bits[7]}}, Bits}))) | (~XSgnE&RoundSgn&~FOpCtrlE[1]) | (RoundMSB&(ShiftCnt==({{5{Bits[7]}}, Bits}-1))) | (~XSgnE&XInfE) | XNaNE; // check if the result underflows (this calculation changes if the result is signed or unsigned) - assign Uf = FOpCtrlE[1] ? XSgnE&~XZeroE | (XSgnE&XInfE) | (XSgnE&~XZeroE&(~ShiftCnt[12]|CalcPlus1)) | (ShiftCnt[12]&Plus1) : (XSgnE&XInfE) | (XSgnE&($signed(ShiftCnt) >= $signed(Bits))) | (XSgnE&~RoundSgn&~ShiftCnt[12]); // assign CvtIntRes = (XSgnE | ShiftCnt[12]) ? {64{1'b0}} : (ShiftCnt >= 64) ? {64{1'b1}} : Rounded; + assign Uf = FOpCtrlE[1] ? XSgnE&~XZeroE | (XSgnE&XInfE) | (XSgnE&~XZeroE&(~ShiftCnt[12]|CalcPlus1)) | (ShiftCnt[12]&Plus1) : (XSgnE&XInfE) | (XSgnE&($signed(ShiftCnt) >= $signed({{5{Bits[7]}}, Bits}))) | (XSgnE&~RoundSgn&~ShiftCnt[12]); // assign CvtIntRes = (XSgnE | ShiftCnt[12]) ? {64{1'b0}} : (ShiftCnt >= 64) ? {64{1'b1}} : Rounded; // calculate the result's sign assign SgnRes = ~FOpCtrlE[2] & FOpCtrlE[0]; diff --git a/wally-pipelined/src/fpu/fhazard.sv b/wally-pipelined/src/fpu/fhazard.sv index e53317376..d515b24d8 100644 --- a/wally-pipelined/src/fpu/fhazard.sv +++ b/wally-pipelined/src/fpu/fhazard.sv @@ -45,7 +45,7 @@ module fhazard( // if the needed value is in the memory stage - input 1 if ((Adr1E == RdM) & FRegWriteM) // if the result will be FResM (can be taken from the memory stage) - if(FResultSelM == 3'b11) FForwardXE = 2'b10; // choose FResM + if(FResultSelM == 2'b11) FForwardXE = 2'b10; // choose FResM else FStallD = 1; // otherwise stall // if the needed value is in the writeback stage else if ((Adr1E == RdW) & FRegWriteW) FForwardXE = 2'b01; // choose FPUResult64W @@ -54,7 +54,7 @@ module fhazard( // if the needed value is in the memory stage - input 2 if ((Adr2E == RdM) & FRegWriteM) // if the result will be FResM (can be taken from the memory stage) - if(FResultSelM == 3'b11) FForwardYE = 2'b10; // choose FResM + if(FResultSelM == 2'b11) FForwardYE = 2'b10; // choose FResM else FStallD = 1; // otherwise stall // if the needed value is in the writeback stage else if ((Adr2E == RdW) & FRegWriteW) FForwardYE = 2'b01; // choose FPUResult64W @@ -63,7 +63,7 @@ module fhazard( // if the needed value is in the memory stage - input 3 if ((Adr3E == RdM) & FRegWriteM) // if the result will be FResM (can be taken from the memory stage) - if(FResultSelM == 3'b11) FForwardZE = 2'b10; // choose FResM + if(FResultSelM == 2'b11) FForwardZE = 2'b10; // choose FResM else FStallD = 1; // otherwise stall // if the needed value is in the writeback stage else if ((Adr3E == RdW) & FRegWriteW) FForwardZE = 2'b01; // choose FPUResult64W diff --git a/wally-pipelined/src/fpu/fma.sv b/wally-pipelined/src/fpu/fma.sv index 22b5cbe00..5dcfe883d 100644 --- a/wally-pipelined/src/fpu/fma.sv +++ b/wally-pipelined/src/fpu/fma.sv @@ -172,14 +172,14 @@ module expadd( // denormalized numbers have diffrent values depending on which precison it is. // double - 1 - // single - 1024-128+1 = 897 + // single - 1023-127+1 = 897 assign Denorm = FmtE ? 1 : 897; // pick denormalized value or exponent assign XExpVal = XDenormE ? Denorm : XExpE; assign YExpVal = YDenormE ? Denorm : YExpE; // kill the exponent if the product is zero - either X or Y is 0 - assign ProdExpE = (XExpVal + YExpVal - `NE'h3ff)&{`NE+2{~(XZeroE|YZeroE)}}; + assign ProdExpE = ({2'b0, XExpVal} + {2'b0, YExpVal} - {2'b0, `NE'h3ff})&{`NE+2{~(XZeroE|YZeroE)}}; endmodule @@ -251,7 +251,7 @@ module align( // - positive means the product is larger, so shift Z right // - Denormal numbers have a diffrent exponent value depending on the precision assign ZExpVal = ZDenormE ? Denorm : ZExpE; - assign AlignCnt = ProdExpE - ZExpVal + (`NF+3); + assign AlignCnt = ProdExpE - {2'b0, ZExpVal} + (`NF+3); // Defualt Addition without shifting // | 54'b0 | 106'b(product) | 2'b0 | @@ -266,7 +266,7 @@ module align( // | 54'b0 | 106'b(product) | 2'b0 | // | addnend | - if ($signed(AlignCnt) < $signed(0)) begin + if ($signed(AlignCnt) < $signed(13'b0)) begin KillProdE = 1; ZManShifted = ZManPreShifted; AddendStickyE = ~(XZeroE|YZeroE); @@ -274,7 +274,7 @@ module align( // If the Addend is shifted right // | 54'b0 | 106'b(product) | 2'b0 | // | addnend | - end else if ($signed(AlignCnt)<=$signed(3*`NF+4)) begin + end else if ($signed(AlignCnt)<=$signed(13'd3*13'd`NF+13'd4)) begin KillProdE = 0; ZManShifted = ZManPreShifted >> AlignCnt; AddendStickyE = |(ZManShifted[`NF-1:0]); @@ -337,7 +337,7 @@ module add( // Do the addition // - calculate a positive and negitive sum in parallel - assign PreSum = AlignedAddendInv + {ProdManKilled, 2'b0}; + assign PreSum = AlignedAddendInv + {55'b0, ProdManKilled, 2'b0}; assign NegPreSum = AlignedAddendE + NegProdManKilled; // Is the sum negitive @@ -387,7 +387,7 @@ module posloa( logic [8:0] i; always_comb begin i = 0; - while (~pf[3*`NF+6-i] && $unsigned(i) <= $unsigned(3*`NF+6)) i = i+1; // search for leading one + while (~pf[3*`NF+6-i] && $unsigned(i) <= $unsigned(9'd3*9'd`NF+9'd6)) i = i+1; // search for leading one PCnt = i; end @@ -413,7 +413,7 @@ module negloa( logic [8:0] i; always_comb begin i = 0; - while (~f[3*`NF+6-i] && $unsigned(i) <= $unsigned(3*`NF+6)) i = i+1; // search for leading one + while (~f[3*`NF+6-i] && $unsigned(i) <= $unsigned(9'd3*9'd`NF+9'd6)) i = i+1; // search for leading one NCnt = i; end @@ -594,8 +594,8 @@ module resultselect( ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{32{1'b1}}, ResultSgn, 8'hfe, {23{1'b1}}} : {{32{1'b1}}, ResultSgn, 8'hff, 23'b0}; assign InvalidResult = FmtM ? {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{32{1'b1}}, ResultSgn, 8'hff, 1'b1, 22'b0}; - assign KillProdResult = FmtM ? {ResultSgn, {ZExpM, ZManM[`NF-1:0]} - (Minus1&AddendStickyM) + (Plus1&AddendStickyM)} : {{32{1'b1}}, ResultSgn, {ZExpM[`NE-1],ZExpM[6:0], ZManM[51:29]} - {30'b0, (Minus1&AddendStickyM)} + {30'b0, (Plus1&AddendStickyM)}}; - assign UnderflowResult = FmtM ? {ResultSgn, {`FLEN-1{1'b0}}} + (CalcPlus1&(AddendStickyM|FrmM[1])) : {{32{1'b1}}, {ResultSgn, 31'b0} + {31'b0, (CalcPlus1&(AddendStickyM|FrmM[1]))}}; + assign KillProdResult = FmtM ? {ResultSgn, {ZExpM, ZManM[`NF-1:0]} - {62'b0, (Minus1&AddendStickyM) + (Plus1&AddendStickyM)}} : {{32{1'b1}}, ResultSgn, {ZExpM[`NE-1],ZExpM[6:0], ZManM[51:29]} - {30'b0, (Minus1&AddendStickyM)} + {30'b0, (Plus1&AddendStickyM)}}; + assign UnderflowResult = FmtM ? {ResultSgn, {`FLEN-1{1'b0}}} + {63'b0,(CalcPlus1&(AddendStickyM|FrmM[1]))} : {{32{1'b1}}, {ResultSgn, 31'b0} + {31'b0, (CalcPlus1&(AddendStickyM|FrmM[1]))}}; assign FMAResM = XNaNM ? XNaNResult : YNaNM ? YNaNResult : ZNaNM ? ZNaNResult : @@ -666,7 +666,7 @@ module normalize( assign UfSticky = AddendStickyM | NormSumSticky; // Determine sum's exponent - assign SumExp = (SumExpTmp+LZAPlus1+(~|SumExpTmp&SumShifted[3*`NF+6])) & {`NE+2{~(SumZero|ResultDenorm)}}; + assign SumExp = (SumExpTmp+{12'b0, LZAPlus1}+{12'b0, ~|SumExpTmp&SumShifted[3*`NF+6]}) & {`NE+2{~(SumZero|ResultDenorm)}}; // recalculate if the result is denormalized assign ResultDenorm = PreResultDenorm&~SumShifted[3*`NF+6]&~SumShifted[3*`NF+7]; diff --git a/wally-pipelined/src/fpu/fpdiv.sv b/wally-pipelined/src/fpu/fpdiv.sv index 0a937b5b0..571d79c47 100755 --- a/wally-pipelined/src/fpu/fpdiv.sv +++ b/wally-pipelined/src/fpu/fpdiv.sv @@ -60,12 +60,10 @@ module fpdiv ( logic Invalid; logic [4:0] FlagsIn; logic signResult; - logic convert; - logic sub; - logic [63:0] q1, qm1, qp1, q0, qm0, qp0; - logic [63:0] rega_out, regb_out, regc_out, regd_out; - logic [127:0] regr_out; + logic [59:0] q1, qm1, qp1, q0, qm0, qp0; + logic [59:0] rega_out, regb_out, regc_out, regd_out; + logic [119:0] regr_out; logic [2:0] sel_muxa, sel_muxb; logic sel_muxr; logic load_rega, load_regb, load_regc, load_regd, load_regr; @@ -90,11 +88,11 @@ module fpdiv ( assign exp2 = {2'b0, Float2[62:52]}; assign bias = {3'h0, 10'h3FF}; // Divide exponent - assign {exp_cout1, open, exp_diff} = exp1 - exp2 + bias; + assign {exp_cout1, open, exp_diff} = {2'b0, exp1} - {2'b0, exp2} + {2'b0, bias}; // Sqrt exponent (check if exponent is odd) assign exp_odd = Float1[52] ? 1'b0 : 1'b1; - assign {exp_cout2, exp_sqrt} = {1'b0, exp1} + {4'h0, 10'h3ff} + exp_odd; + assign {exp_cout2, exp_sqrt} = {1'b0, exp1} + {4'h0, 10'h3ff} + {13'b0, exp_odd}; // Choose correct exponent assign expF = op_type ? exp_sqrt[13:1] : exp_diff; @@ -105,10 +103,10 @@ module fpdiv ( .load_regr, .load_regs, .P, .op_type, .exp_odd); // FSM : control divider - fsm control (.clk, .reset, .start, .op_type, - .done, .load_rega, .load_regb, .load_regc, .load_regd, - .load_regr, .load_regs, .sel_muxa, .sel_muxb, .sel_muxr, - .divBusy(FDivBusyE)); + fsm_fpdiv control (.clk, .reset, .start, .op_type, + .done, .load_rega, .load_regb, .load_regc, .load_regd, + .load_regr, .load_regs, .sel_muxa, .sel_muxb, .sel_muxr, + .divBusy(FDivBusyE)); // Round the mantissa to a 52-bit value, with the leading one // removed. The rounding units also handles special cases and diff --git a/wally-pipelined/src/fpu/fpdiv_pipe.sv b/wally-pipelined/src/fpu/fpdiv_pipe.sv new file mode 100755 index 000000000..52380d3c6 --- /dev/null +++ b/wally-pipelined/src/fpu/fpdiv_pipe.sv @@ -0,0 +1,172 @@ +/////////////////////////////////////////// +// +// Written: James Stine +// Modified: 8/1/2018 +// +// Purpose: Floating point divider/square root top unit pipelined version (Goldschmidt) +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +module fpdiv_pipe ( + input logic clk, + input logic reset, + input logic start, + input logic [63:0] op1, + input logic [63:0] op2, + input logic [1:0] rm, + input logic op_type, + input logic P, + input logic OvEn, + input logic UnEn, + input logic XNaNQ, + input logic YNaNQ, + input logic XZeroQ, + input logic YZeroQ, + input logic XInfQ, + input logic YInfQ, + + output logic done, + output logic FDivBusyE, + output logic [63:0] AS_Result, + output logic [4:0] Flags); + + supply1 vdd; + supply0 vss; + + logic [63:0] Float1; + logic [63:0] Float2; + logic [63:0] IntValue; + + logic [12:0] exp1, exp2, expF; + logic [12:0] exp_diff, bias; + logic [13:0] exp_sqrt; + + logic [63:0] Result; + logic [52:0] mantissaA; + logic [52:0] mantissaB; + + logic [2:0] sel_inv; + logic Invalid; + logic [4:0] FlagsIn; + logic exp_gt63; + logic Sticky_out; + logic signResult, sign_corr; + logic corr_sign; + logic zeroB; + logic convert; + logic swap; + logic sub; + + logic [59:0] q1, qm1, qp1, q0, qm0, qp0; + logic [59:0] rega_out, regb_out, regc_out, regd_out; + logic [119:0] regr_out; + logic [2:0] sel_muxa, sel_muxb; + logic sel_muxr; + logic load_rega, load_regb, load_regc, load_regd, load_regr; + logic load_regp; + + logic donev, sel_muxrv, sel_muxsv; + logic [1:0] sel_muxav, sel_muxbv; + logic load_regav, load_regbv, load_regcv; + logic load_regrv, load_regsv; + + + // op_type : fdiv=0, fsqrt=1 + assign Float1 = op1; + assign Float2 = op_type ? op1 : op2; + + // Exception detection + exception_div exc1 (.A(Float1), .B(Float2), .op_type, .Ztype(sel_inv), .Invalid); + + // Determine Sign/Mantissa + assign signResult = ((Float1[63]^Float2[63])&~op_type) | Float1[63]&op_type; + assign mantissaA = {vdd, Float1[51:0]}; + assign mantissaB = {vdd, Float2[51:0]}; + // Early-ending detection + assign early_detection = |mantissaB[31:0]; + + // Perform Exponent Subtraction - expA - expB + Bias + assign exp1 = {2'b0, Float1[62:52]}; + assign exp2 = {2'b0, Float2[62:52]}; + // bias : DP = 2^{11-1}-1 = 1023 + assign bias = {3'h0, 10'h3FF}; + // Divide exponent + assign {exp_cout1, open, exp_diff} = {2'b0, exp1} - {2'b0, exp2} + {2'b0, bias}; + + // Sqrt exponent (check if exponent is odd) + assign exp_odd = Float1[52] ? vss : vdd; + assign {exp_cout2, exp_sqrt} = {1'b0, exp1} + {4'h0, 10'h3ff} + {13'b0, exp_odd}; + + // Choose correct exponent + assign expF = op_type ? exp_sqrt[13:1] : exp_diff; + + logic exp_odd1; + logic P1; + logic op_type1; + logic [12:0] expF1; + logic [52:0] mantissaA1; + logic [52:0] mantissaB1; + logic [2:0] sel_inv1; + logic DenormIn1; + logic signResult1; + logic Invalid1; + + flopenr #(1) rega (clk, reset, 1'b1, exp_odd, exp_odd1); + flopenr #(1) regb (clk, reset, 1'b1, P, P1); + flopenr #(1) regc (clk, reset, 1'b1, op_type, op_type1); + flopenr #(13) regd (clk, reset, 1'b1, expF, expF1); + flopenr #(53) rege (clk, reset, 1'b1, mantissaA, mantissaA1); + flopenr #(53) regf (clk, reset, 1'b1, mantissaB, mantissaB1); + flopenr #(1) regg (clk, reset, 1'b1, start, start1); + flopenr #(3) regh (clk, reset, 1'b1, sel_inv, sel_inv1); + flopenr #(1) regi (clk, reset, 1'b1, DenormIn, DenormIn1); + flopenr #(1) regj (clk, reset, 1'b1, signResult, signResult1); + flopenr #(1) regk (clk, reset, 1'b1, Invalid, Invalid1); + + // Main Goldschmidt/Division Routine + divconv_pipe goldy (q1, qm1, qp1, q0, qm0, qp0, rega_out, regb_out, regc_out, regd_out, + regr_out, mantissaB1, mantissaA1, + sel_muxa, sel_muxb, sel_muxr, reset, clk, + load_rega, load_regb, load_regc, load_regd, + load_regr, load_regs, load_regp, + P1, op_type1, exp_odd1); + + // FSM : control divider + fsm_fpdiv_pipe control (.clk, .reset, .start, .op_type, .P, + .done, .load_rega, .load_regb, .load_regc, .load_regd, + .load_regr, .load_regs, .load_regp, + .sel_muxa, .sel_muxb, .sel_muxr, .divBusy(FDivBusyE)); + + + // Round the mantissa to a 52-bit value, with the leading one + // removed. The rounding units also handles special cases and + // set the exception flags. + rounder_div round1 (.rm, .P, .OvEn, .UnEn, .exp_diff(expF), + .sel_inv, .Invalid, .SignR(signResult), + .Float1(op1), .Float2(op2), + .XNaNQ, .YNaNQ, .XZeroQ, .YZeroQ, + .XInfQ, .YInfQ, .op_type, + .q1, .qm1, .qp1, .q0, .qm0, .qp0, .regr_out, + .Result, .Flags(FlagsIn)); + + // Store the final result and the exception flags in registers. + flopenr #(64) regl (clk, reset, done, Result, AS_Result); + flopenr #(5) regn (clk, reset, done, FlagsIn, Flags); + +endmodule // fpdiv_pipe + diff --git a/wally-pipelined/src/fpu/fpu.sv b/wally-pipelined/src/fpu/fpu.sv index 6793479b2..fd91b1b2f 100755 --- a/wally-pipelined/src/fpu/fpu.sv +++ b/wally-pipelined/src/fpu/fpu.sv @@ -129,16 +129,16 @@ module fpu ( logic [63:0] AlignedSrcAE; // align SrcA to the floating point format // DECODE STAGE + // calculate FP control signals fctrl fctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]), .FRM_REGW, .IllegalFPUInstrD, .FRegWriteD, .FDivStartD, .FResultSelD, .FOpCtrlD, .FResSelD, .FIntResSelD, .FmtD, .FrmD, .FWriteIntD); // FP register file - // - can read 3 registers and write 1 register every cycle fregfile fregfile (.clk, .reset, .we4(FRegWriteW), - .a1(InstrD[19:15]), .a2(InstrD[24:20]), .a3(InstrD[31:27]), .a4(RdW), - .wd4(FPUResultW), + .a1(InstrD[19:15]), .a2(InstrD[24:20]), .a3(InstrD[31:27]), + .a4(RdW), .wd4(FPUResultW), .rd1(FRD1D), .rd2(FRD2D), .rd3(FRD3D)); // D/E pipeline registers @@ -158,23 +158,23 @@ module fpu ( .FStallD, .FForwardXE, .FForwardYE, .FForwardZE); // forwarding muxs - mux3 #(64) fxemux(FRD1E, FPUResultW, FResM, FForwardXE, FSrcXE); - mux3 #(64) fyemux(FRD2E, FPUResultW, FResM, FForwardYE, FPreSrcYE); - mux3 #(64) fzemux(FRD3E, FPUResultW, FResM, FForwardZE, FPreSrcZE); - mux3 #(64) fyaddmux(FPreSrcYE, {{32{1'b1}}, 2'b0, {7{1'b1}}, 23'b0}, - {2'b0, {10{1'b1}}, 52'b0}, - {FmtE&FOpCtrlE[2]&FOpCtrlE[1]&(FResultSelE==3'b01), ~FmtE&FOpCtrlE[2]&FOpCtrlE[1]&(FResultSelE==3'b01)}, - FSrcYE); // Force Z to be 0 for multiply instructions + mux3 #(64) fxemux (FRD1E, FPUResultW, FResM, FForwardXE, FSrcXE); + mux3 #(64) fyemux (FRD2E, FPUResultW, FResM, FForwardYE, FPreSrcYE); + mux3 #(64) fzemux (FRD3E, FPUResultW, FResM, FForwardZE, FPreSrcZE); + mux3 #(64) fyaddmux (FPreSrcYE, {{32{1'b1}}, 2'b0, {7{1'b1}}, 23'b0}, + {2'b0, {10{1'b1}}, 52'b0}, + {FmtE&FOpCtrlE[2]&FOpCtrlE[1]&(FResultSelE==2'b01), ~FmtE&FOpCtrlE[2]&FOpCtrlE[1]&(FResultSelE==2'b01)}, + FSrcYE); // Force Z to be 0 for multiply instructions // Force Z to be 0 for multiply instructions - mux3 #(64) fzmulmux(FPreSrcZE, 64'b0, FPreSrcYE, {FOpCtrlE[2]&FOpCtrlE[1], FOpCtrlE[2]&~FOpCtrlE[1]}, FSrcZE); + mux3 #(64) fzmulmux (FPreSrcZE, 64'b0, FPreSrcYE, {FOpCtrlE[2]&FOpCtrlE[1], FOpCtrlE[2]&~FOpCtrlE[1]}, FSrcZE); // unpacking unit // - splits FP inputs into their various parts // - does some classifications (SNaN, NaN, Denorm, Norm, Zero, Infifnity) - unpacking unpacking(.X(FSrcXE), .Y(FSrcYE), .Z(FSrcZE), .FOpCtrlE, .FmtE, - .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE, - .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE, - .XZeroE, .YZeroE, .ZZeroE, .BiasE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .XNormE); + unpacking unpacking (.X(FSrcXE), .Y(FSrcYE), .Z(FSrcZE), .FOpCtrlE, .FmtE, + .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE, + .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE, + .XZeroE, .YZeroE, .ZZeroE, .BiasE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .XNormE); // FMA // - two stage FMA @@ -191,35 +191,21 @@ module fpu ( .FmtE, .FmtM, .FrmM, .FMAFlgM, .FMAResM); - // clock gater - // - creates a clock that only runs durring divide/sqrt instructions - // - using the seperate clock gives the divide/sqrt unit some to get set up - // *** the module says not to use in synthisis - clockgater fpdivclkg(.E(FDivStartE), - .SE(1'b0), - .CLK(clk), - .ECLK(FDivClk)); - - // capture the inputs for divide/sqrt - // - if not captured any forwarded inputs will change durring computation - // - this problem is caused by stalling the execute stage - // - the other units don't have this problem, only div/sqrt stalls the execute stage + // fpdivsqrt using Goldschmidt's iteration floprc #(64) reg_input1 (.d({XSgnE, XExpE, XManE[51:0]}), .q(DivInput1E), - .clear(FDivSqrtDoneE), - .reset(reset), .clk(FDivBusyE)); + .clear(FDivSqrtDoneE), + .reset(reset), .clk(FDivBusyE)); floprc #(64) reg_input2 (.d({YSgnE, YExpE, YManE[51:0]}), .q(DivInput2E), - .clear(FDivSqrtDoneE), - .reset(reset), .clk(FDivBusyE)); + .clear(FDivSqrtDoneE), + .reset(reset), .clk(FDivBusyE)); floprc #(6) reg_input3 (.d({XNaNE, YNaNE, XInfE, YInfE, XZeroE, YZeroE}), - .q({XNaNQ, YNaNQ, XInfQ, YInfQ, XZeroQ, YZeroQ}), - .clear(FDivSqrtDoneE), - .reset(reset), .clk(FDivBusyE)); - - // fpdivsqrt using Goldschmidt's iteration - fpdiv fdivsqrt (.op1(DivInput1E), .op2(DivInput2E), .rm(FrmE[1:0]), .op_type(FOpCtrlE[0]), - .reset, .clk(FDivClk), .start(FDivStartE), .P(~FmtE), .OvEn(1'b1), .UnEn(1'b1), - .XNaNQ, .YNaNQ, .XInfQ, .YInfQ, .XZeroQ, .YZeroQ, - .FDivBusyE, .done(FDivSqrtDoneE), .AS_Result(FDivResM), .Flags(FDivFlgM)); + .q({XNaNQ, YNaNQ, XInfQ, YInfQ, XZeroQ, YZeroQ}), + .clear(FDivSqrtDoneE), + .reset(reset), .clk(FDivBusyE)); + fpdiv fdivsqrt (.op1(DivInput1E), .op2(DivInput2E), .rm(FrmE[1:0]), .op_type(FOpCtrlE[0]), + .reset, .clk(clk), .start(FDivStartE), .P(~FmtE), .OvEn(1'b1), .UnEn(1'b1), + .XNaNQ, .YNaNQ, .XInfQ, .YInfQ, .XZeroQ, .YZeroQ, + .FDivBusyE, .done(FDivSqrtDoneE), .AS_Result(FDivResM), .Flags(FDivFlgM)); // convert from signle to double and vice versa cvtfp cvtfp (.XExpE, .XManE, .XSgnE, .XZeroE, .XDenormE, .XInfE, .XNaNE, .XSNaNE, .FrmE, .FmtE, .CvtFpResE, .CvtFpFlgE); @@ -234,17 +220,14 @@ module fpu ( .Invalid(CmpNVE), .CmpResE); // sign injection unit - // - computation is done in one stage fsgn fsgn (.SgnOpCodeE(FOpCtrlE[1:0]), .XSgnE, .YSgnE, .FSrcXE, .FmtE, .XExpMaxE, .SgnNVE, .SgnResE); // classify - // - computation is done in one stage - // - most of the work is done in the unpacking unit - // - result is written to the integer register fclassify fclassify (.XSgnE, .XDenormE, .XZeroE, .XNaNE, .XInfE, .XNormE, .XSNaNE, .ClassResE); - + + // Convert fcvt fcvt (.XSgnE, .XExpE, .XManE, .XZeroE, .XNaNE, .XInfE, .XDenormE, .BiasE, .SrcAE, .FOpCtrlE, .FmtE, .FrmE, .CvtResE, .CvtFlgE); @@ -267,22 +250,23 @@ module fpu ( // E/M pipe registers // flopenrc #(64) EMFpReg1(clk, reset, FlushM, ~StallM, FSrcXE, FSrcXM); - flopenrc #(65) EMFpReg2(clk, reset, FlushM, ~StallM, {XSgnE,XExpE,XManE}, {XSgnM,XExpM,XManM}); - flopenrc #(65) EMFpReg3(clk, reset, FlushM, ~StallM, {YSgnE,YExpE,YManE}, {YSgnM,YExpM,YManM}); - flopenrc #(64) EMFpReg4(clk, reset, FlushM, ~StallM, {ZExpE,ZManE}, {ZExpM,ZManM}); - flopenrc #(12) EMFpReg5(clk, reset, FlushM, ~StallM, - {XZeroE, YZeroE, ZZeroE, XInfE, YInfE, ZInfE, XNaNE, YNaNE, ZNaNE, XSNaNE, YSNaNE, ZSNaNE}, - {XZeroM, YZeroM, ZZeroM, XInfM, YInfM, ZInfM, XNaNM, YNaNM, ZNaNM, XSNaNM, YSNaNM, ZSNaNM}); - flopenrc #(64) EMRegCmpRes(clk, reset, FlushM, ~StallM, FResE, FResM); - flopenrc #(5) EMRegCmpFlg(clk, reset, FlushM, ~StallM, FFlgE, FFlgM); - flopenrc #(`XLEN) EMRegSgnRes(clk, reset, FlushM, ~StallM, FIntResE, FIntResM); - flopenrc #(11) EMCtrlReg(clk, reset, FlushM, ~StallM, - {FRegWriteE, FResultSelE, FrmE, FmtE, FOpCtrlE, FWriteIntE}, - {FRegWriteM, FResultSelM, FrmM, FmtM, FOpCtrlM, FWriteIntM}); + flopenrc #(65) EMFpReg2 (clk, reset, FlushM, ~StallM, {XSgnE,XExpE,XManE}, {XSgnM,XExpM,XManM}); + flopenrc #(65) EMFpReg3 (clk, reset, FlushM, ~StallM, {YSgnE,YExpE,YManE}, {YSgnM,YExpM,YManM}); + flopenrc #(64) EMFpReg4 (clk, reset, FlushM, ~StallM, {ZExpE,ZManE}, {ZExpM,ZManM}); + flopenrc #(12) EMFpReg5 (clk, reset, FlushM, ~StallM, + {XZeroE, YZeroE, ZZeroE, XInfE, YInfE, ZInfE, XNaNE, YNaNE, ZNaNE, XSNaNE, YSNaNE, ZSNaNE}, + {XZeroM, YZeroM, ZZeroM, XInfM, YInfM, ZInfM, XNaNM, YNaNM, ZNaNM, XSNaNM, YSNaNM, ZSNaNM}); + flopenrc #(64) EMRegCmpRes (clk, reset, FlushM, ~StallM, FResE, FResM); + flopenrc #(5) EMRegCmpFlg (clk, reset, FlushM, ~StallM, FFlgE, FFlgM); + flopenrc #(`XLEN) EMRegSgnRes (clk, reset, FlushM, ~StallM, FIntResE, FIntResM); + flopenrc #(11) EMCtrlReg (clk, reset, FlushM, ~StallM, + {FRegWriteE, FResultSelE, FrmE, FmtE, FOpCtrlE, FWriteIntE}, + {FRegWriteM, FResultSelM, FrmM, FmtM, FOpCtrlM, FWriteIntM}); // BEGIN MEMORY STAGE + // FPU flag selection - to privileged - mux4 #(5) FPUFlgMux(5'b0, FMAFlgM, FDivFlgM, FFlgM, FResultSelW, SetFflagsM); + mux4 #(5) FPUFlgMux (5'b0, FMAFlgM, FDivFlgM, FFlgM, FResultSelW, SetFflagsM); // M/W pipe registers flopenrc #(64) MWRegFma(clk, reset, FlushW, ~StallW, FMAResM, FMAResW); @@ -298,10 +282,10 @@ module fpu ( // put ReadData into NaN-blocking format // - if there are any unsused bits the most significant bits are filled with 1s // - for load instruction - mux2 #(64) ReadResMux({{32{1'b1}}, ReadDataW[31:0]}, {{64-`XLEN{1'b1}}, ReadDataW}, FmtW, ReadResW); + mux2 #(64) ReadResMux ({{32{1'b1}}, ReadDataW[31:0]}, {{64-`XLEN{1'b1}}, ReadDataW}, FmtW, ReadResW); // select the result to be written to the FP register - mux4 #(64) FPUResultMux(ReadResW, FMAResW, FDivResW, FResW, FResultSelW, FPUResultW); + mux4 #(64) FPUResultMux (ReadResW, FMAResW, FDivResW, FResW, FResultSelW, FPUResultW); end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low assign FStallD = 0; diff --git a/wally-pipelined/src/fpu/fsm.sv b/wally-pipelined/src/fpu/fsm_fpdiv.sv similarity index 93% rename from wally-pipelined/src/fpu/fsm.sv rename to wally-pipelined/src/fpu/fsm_fpdiv.sv index 4e015ba75..2f5bbd274 100755 --- a/wally-pipelined/src/fpu/fsm.sv +++ b/wally-pipelined/src/fpu/fsm_fpdiv.sv @@ -22,7 +22,7 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -module fsm ( +module fsm_fpdiv ( input logic clk, input logic reset, input logic start, @@ -47,7 +47,7 @@ module fsm ( statetype current_state, next_state; - always @(negedge clk) + always @(posedge clk) begin if (reset == 1'b1) current_state = S0; @@ -269,8 +269,23 @@ module fsm ( sel_muxa = 3'b000; sel_muxb = 3'b000; sel_muxr = 1'b0; + next_state = S11; + end // case: S10 + S11: // done + begin + done = 1'b0; + divBusy = 1'b0; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b0; next_state = S0; - end + end S13: // start of sqrt path begin done = 1'b0; @@ -479,8 +494,23 @@ module fsm ( sel_muxa = 3'b000; sel_muxb = 3'b000; sel_muxr = 1'b0; + next_state = S27; + end // case: S26 + S27: // done + begin + done = 1'b0; + divBusy = 1'b0; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b0; next_state = S0; - end + end default: begin done = 1'b0; diff --git a/wally-pipelined/src/fpu/fsm_fpdiv_pipe.sv b/wally-pipelined/src/fpu/fsm_fpdiv_pipe.sv new file mode 100755 index 000000000..66ce0ab7e --- /dev/null +++ b/wally-pipelined/src/fpu/fsm_fpdiv_pipe.sv @@ -0,0 +1,1216 @@ +/////////////////////////////////////////// +// +// Written: James Stine +// Modified: 9/28/2021 +// +// Purpose: FSM for floating point divider/square root unit (Goldschmidt) +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +module fsm_fpdiv_pipe ( + input logic clk, + input logic reset, + input logic start, + input logic op_type, + input logic P, + output logic done, + output logic load_rega, + output logic load_regb, + output logic load_regc, + output logic load_regd, + output logic load_regr, + output logic load_regs, + output logic load_regp, + output logic [2:0] sel_muxa, + output logic [2:0] sel_muxb, + output logic sel_muxr, + output logic divBusy + ); + + // div64 : S0-S14 (15 cycles) + // sqrt64 : S15-S35 (21 cycles) + // div32: S36-S47 (12 cycles) + // sqrt32 : S48-S64 (17 cycles) + typedef enum logic [6:0] {S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, + S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, + S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, + S30, S31, S32, S33, S34, S35, S36, S37, S38, S39, + S40, S41, S42, S43, S44, S45, S46, S47, S48, S49, + S50, S51, S52, S53, S54, S55, S56, S57, S58, S59, + S60, S61, S62, S63, S64} statetype; + + statetype current_state, next_state; + + always @(posedge clk) + begin + if (reset == 1'b1) + current_state <= S0; + else + current_state <= next_state; + end + + always @(*) + begin + case(current_state) + S0: // iteration 0 + begin + if (start==1'b0) + begin + done = 1'b0; + divBusy = 1'b0; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b0; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b0; + next_state <= S0; + end + else if (start==1'b1 && op_type==1'b0 && P==1'b0) + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b1; + load_regb = 1'b0; + load_regc = 1'b1; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b010; + sel_muxb = 3'b000; + sel_muxr = 1'b0; + next_state <= S1; + end + else if (start==1'b1 && op_type==1'b0 && P==1'b1) + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b1; + load_regb = 1'b0; + load_regc = 1'b1; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b010; + sel_muxb = 3'b000; + sel_muxr = 1'b0; + next_state <= S36; + end + else if (start==1'b1 && op_type==1'b1 && P==1'b0) + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b1; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b010; + sel_muxb = 3'b001; + sel_muxr = 1'b0; + next_state <= S15; + end + else if (start==1'b1 && op_type==1'b1 && P==1'b1) + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b1; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b010; + sel_muxb = 3'b001; + sel_muxr = 1'b0; + next_state <= S48; + end + else + begin + done = 1'b0; + divBusy = 1'b0; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b0; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b0; + next_state <= S0; + end + end // case: S0 + // div64 + S1: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b1; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b001; + sel_muxb = 3'b001; + sel_muxr = 1'b0; + next_state <= S2; + end // case: S1 + S2: // iteration 1 + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b1; + load_regb = 1'b0; + load_regc = 1'b1; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b010; + sel_muxr = 1'b0; + next_state <= S3; + end + S3: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b1; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b011; + sel_muxb = 3'b011; + sel_muxr = 1'b0; + next_state <= S4; + end + S4: // iteration 2 + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b1; + load_regb = 1'b0; + load_regc = 1'b1; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b010; + sel_muxr = 1'b0; + next_state <= S5; + end + S5: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b1; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b011; + sel_muxb = 3'b011; + sel_muxr = 1'b0; // add + next_state <= S6; + end + S6: // iteration 3 + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b1; + load_regb = 1'b0; + load_regc = 1'b1; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b010; + sel_muxr = 1'b0; + next_state <= S7; + end + S7: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b1; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b011; + sel_muxb = 3'b011; + sel_muxr = 1'b0; + next_state <= S8; + end // case: S7 + S8: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b0; + next_state <= S9; + end // case: S7 + S9: // q,qm,qp + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b1; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b0; + next_state <= S10; + end // case: S9 + S10: // rem + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b1; + next_state <= S11; + end + S11: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b1; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b1; + next_state <= S12; + end // case: S11 + S12: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b0; + next_state <= S13; + end + S13: + begin + done = 1'b1; + divBusy = 1'b0; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b0; + next_state <= S14; + end + S14: + begin + done = 1'b0; + divBusy = 1'b0; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b0; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b0; + next_state <= S0; + end + // sqrt64 + S15: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b0; + next_state <= S16; + end + S16: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b1; + load_regb = 1'b0; + load_regc = 1'b1; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b001; + sel_muxb = 3'b100; + sel_muxr = 1'b0; + next_state <= S17; + end + S17: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b1; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b010; + sel_muxb = 3'b000; + sel_muxr = 1'b0; + next_state <= S18; + end + S18: // iteration 1 + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b1; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b011; + sel_muxr = 1'b0; + next_state <= S19; + end + S19: // iteration 1 + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b0; + next_state <= S20; + end + S20: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b1; + load_regb = 1'b0; + load_regc = 1'b1; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b100; + sel_muxb = 3'b010; + sel_muxr = 1'b0; + next_state <= S21; + end + S21: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b1; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b011; + sel_muxb = 3'b011; + sel_muxr = 1'b0; + next_state <= S22; + end + S22: // iteration 2 + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b1; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b011; + sel_muxr = 1'b0; + next_state <= S23; + end // case: S18 + S23: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b0; + next_state <= S24; + end + S24: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b1; + load_regb = 1'b0; + load_regc = 1'b1; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b100; + sel_muxb = 3'b010; + sel_muxr = 1'b0; + next_state <= S25; + end + S25: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b1; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b011; + sel_muxb = 3'b011; + sel_muxr = 1'b0; + next_state <= S26; + end + S26: // iteration 3 + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b1; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b011; + sel_muxr = 1'b0; + next_state <= S27; + end // case: S21 + S27: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b0; + next_state <= S28; + end + S28: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b1; + load_regb = 1'b0; + load_regc = 1'b1; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b100; + sel_muxb = 3'b010; + sel_muxr = 1'b0; + next_state <= S29; + end + S29: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b1; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b011; + sel_muxb = 3'b011; + sel_muxr = 1'b0; + next_state <= S30; + end // case: S23 + S30: // q,qm,qp + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b1; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b0; + next_state <= S31; + end + S31: // rem + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b011; + sel_muxb = 3'b110; + sel_muxr = 1'b1; + next_state <= S32; + end // case: S25 + S32: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b1; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b011; + sel_muxb = 3'b110; + sel_muxr = 1'b1; + next_state <= S33; + end // case: S34 + S33: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b0; + next_state <= S34; + end + S34: // done + begin + done = 1'b1; + divBusy = 1'b0; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b0; + next_state <= S35; + end // case: S34 + S34: + begin + done = 1'b0; + divBusy = 1'b0; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b0; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b0; + next_state <= S0; + end + // div32 + S36: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b1; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b001; + sel_muxb = 3'b001; + sel_muxr = 1'b0; + next_state <= S37; + end // case: S1 + S37: // iteration 1 + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b1; + load_regb = 1'b0; + load_regc = 1'b1; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b010; + sel_muxr = 1'b0; + next_state <= S38; + end + S38: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b1; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b011; + sel_muxb = 3'b011; + sel_muxr = 1'b0; + next_state <= S39; + end + S39: // iteration 2 + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b1; + load_regb = 1'b0; + load_regc = 1'b1; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b010; + sel_muxr = 1'b0; + next_state <= S40; + end + S40: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b1; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b011; + sel_muxb = 3'b011; + sel_muxr = 1'b0; + next_state <= S41; + end + S41: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b0; + next_state <= S42; + end + S42: // q,qm,qp + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b1; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b0; + next_state <= S43; + end // case: S9 + S43: // rem + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b1; + next_state <= S44; + end + S44: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b1; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b1; + next_state <= S45; + end // case: S11 + S45: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b0; + next_state <= S46; + end + S46: // done + begin + done = 1'b1; + divBusy = 1'b0; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b0; + next_state <= S47; + end + S47: + begin + done = 1'b0; + divBusy = 1'b0; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b0; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b0; + next_state <= S0; + end + // sqrt32 + S48: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b0; + next_state <= S49; + end + S49: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b1; + load_regb = 1'b0; + load_regc = 1'b1; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b001; + sel_muxb = 3'b100; + sel_muxr = 1'b0; + next_state <= S50; + end + S50: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b1; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b010; + sel_muxb = 3'b000; + sel_muxr = 1'b0; + next_state <= S51; + end + S51: // iteration 1 + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b1; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b011; + sel_muxr = 1'b0; + next_state <= S52; + end + S52: // iteration 1 + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b0; + next_state <= S53; + end + S53: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b1; + load_regb = 1'b0; + load_regc = 1'b1; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b100; + sel_muxb = 3'b010; + sel_muxr = 1'b0; + next_state <= S54; + end + S54: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b1; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b011; + sel_muxb = 3'b011; + sel_muxr = 1'b0; + next_state <= S55; + end + S55: // iteration 2 + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b1; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b011; + sel_muxr = 1'b0; + next_state <= S56; + end // case: S18 + S56: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b0; + next_state <= S57; + end + S57: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b1; + load_regb = 1'b0; + load_regc = 1'b1; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b100; + sel_muxb = 3'b010; + sel_muxr = 1'b0; + next_state <= S58; + end + S58: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b1; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b011; + sel_muxb = 3'b011; + sel_muxr = 1'b0; + next_state <= S59; + end + S59: // q,qm,qp + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b1; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b0; + next_state <= S60; + end + S60: // rem + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b011; + sel_muxb = 3'b110; + sel_muxr = 1'b1; + next_state <= S61; + end // case: S25 + S61: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b1; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b011; + sel_muxb = 3'b110; + sel_muxr = 1'b1; + next_state <= S62; + end // case: S34 + S62: + begin + done = 1'b0; + divBusy = 1'b1; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b0; + next_state <= S63; + end + S63: // done + begin + done = 1'b1; + divBusy = 1'b0; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b1; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b0; + next_state <= S64; + end // case: S34 + S64: + begin + done = 1'b0; + divBusy = 1'b0; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b0; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b0; + next_state <= S0; + end + default: + begin + done = 1'b0; + divBusy = 1'b0; + load_rega = 1'b0; + load_regb = 1'b0; + load_regc = 1'b0; + load_regd = 1'b0; + load_regr = 1'b0; + load_regs = 1'b0; + load_regp = 1'b0; + sel_muxa = 3'b000; + sel_muxb = 3'b000; + sel_muxr = 1'b0; + next_state <= S0; + end + endcase // case(current_state) + end // always @ (current_state or X) + +endmodule // fsm diff --git a/wally-pipelined/src/fpu/rounder_div.sv b/wally-pipelined/src/fpu/rounder_div.sv index 1d2ff1cc3..66bfe1d30 100755 --- a/wally-pipelined/src/fpu/rounder_div.sv +++ b/wally-pipelined/src/fpu/rounder_div.sv @@ -40,25 +40,25 @@ module rounder_div ( input logic XInfQ, input logic YInfQ, input logic op_type, - input logic [63:0] q1, - input logic [63:0] qm1, - input logic [63:0] qp1, - input logic [63:0] q0, - input logic [63:0] qm0, - input logic [63:0] qp0, - input logic [127:0] regr_out, + input logic [59:0] q1, + input logic [59:0] qm1, + input logic [59:0] qp1, + input logic [59:0] q0, + input logic [59:0] qm0, + input logic [59:0] qp0, + input logic [119:0] regr_out, output logic [63:0] Result, output logic [4:0] Flags ); - logic Rsign; - logic [10:0] Rexp; - logic [12:0] Texp; - logic [51:0] Rmant; - logic [63:0] Tmant; - logic [51:0] Smant; - logic Rzero; + logic Rsign; + logic [10:0] Rexp; + logic [12:0] Texp; + logic [51:0] Rmant; + logic [59:0] Tmant; + logic [51:0] Smant; + logic Rzero; logic Gdp, Gsp, G; logic UnFlow_SP, UnFlow_DP, UnderFlow; logic OvFlow_SP, OvFlow_DP, OverFlow; @@ -77,7 +77,7 @@ module rounder_div ( logic zero_rem; logic [1:0] mux_mant; logic sign_rem; - logic [63:0] q, qm, qp; + logic [59:0] q, qm, qp; logic exp_ovf; logic [50:0] NaN_out; @@ -87,10 +87,10 @@ module rounder_div ( // Remainder = 0? assign zero_rem = ~(|regr_out); // Remainder Sign - assign sign_rem = ~regr_out[127]; + assign sign_rem = ~regr_out[119]; // choose correct Guard bit [1,2) or [0,1) - assign Gdp = q1[63] ? q1[10] : q0[10]; - assign Gsp = q1[63] ? q1[39] : q0[39]; + assign Gdp = q1[59] ? q1[6] : q0[6]; + assign Gsp = q1[59] ? q1[35] : q0[35]; assign G = P ? Gsp : Gdp; // Selection of Rounding (from logic/switching) assign mux_mant[1] = (SignR&rm[1]&rm[0]&G) | (!SignR&rm[1]&!rm[0]&G) | @@ -102,18 +102,18 @@ module rounder_div ( (SignR&rm[1]&!rm[0]&!G&!zero_rem&sign_rem); // Which Q? - mux2 #(64) mx1 (q0, q1, q1[63], q); - mux2 #(64) mx2 (qm0, qm1, q1[63], qm); - mux2 #(64) mx3 (qp0, qp1, q1[63], qp); + mux2 #(60) mx1 (q0, q1, q1[59], q); + mux2 #(60) mx2 (qm0, qm1, q1[59], qm); + mux2 #(60) mx3 (qp0, qp1, q1[59], qp); // Choose Q, Q+1, Q-1 - mux3 #(64) mx4 (q, qm, qp, mux_mant, Tmant); - assign Smant = Tmant[62:11]; + mux3 #(60) mx4 (q, qm, qp, mux_mant, Tmant); + assign Smant = Tmant[58:7]; // Compute the value of the exponent // exponent is modified if we choose: // 1.) we choose any qm0, qp0, q0 (since we shift mant) // 2.) we choose qp and we overflow (for RU) - assign exp_ovf = |{qp[62:40], (qp[39:11] & {29{~P}})}; - assign Texp = exp_diff - {{13{1'b0}}, ~q1[63]} + {{13{1'b0}}, mux_mant[1]&qp1[63]&~exp_ovf}; + assign exp_ovf = |{qp[58:36], (qp[35:7] & {29{~P}})}; + assign Texp = exp_diff - {{12{1'b0}}, ~q1[59]} + {{12{1'b0}}, mux_mant[1]&qp1[59]&~exp_ovf}; // Overflow only occurs for double precision, if Texp[10] to Texp[0] are // all ones. To encourage sharing with single precision overflow detection, @@ -187,9 +187,9 @@ module rounder_div ( assign NaN_Sign_out = ~XNaNQ&YNaNQ ? Float2[63] : Float1[63]; assign Sign_out = (XZeroQ&YZeroQ | XInfQ&YInfQ)&~op_type | Rsign&~XNaNQ&~YNaNQ | NaN_Sign_out&(XNaNQ|YNaNQ); - // FIXME (jes) - Imperas gives sNaN a Sign=0 where x86 gives Sign=1 - // | Float1[63]&op_type; + // | Float1[63]&op_type; (logic to fix this but removed for now) + assign Rmant[51] = Largest | NaN | (Smant[51]&~Infinite&~Rzero); assign Rmant[50:0] = ({51{Largest}} | (Smant[50:0]&{51{~Infinite&Valid&~Rzero}}) | (NaN_out&{51{NaN}}))&({51{~(op_type&Float1[63]&~XZeroQ)}}); diff --git a/wally-pipelined/src/fpu/unpacking.sv b/wally-pipelined/src/fpu/unpacking.sv index 3f80ee031..bc9030444 100644 --- a/wally-pipelined/src/fpu/unpacking.sv +++ b/wally-pipelined/src/fpu/unpacking.sv @@ -75,6 +75,6 @@ module unpacking ( assign YZeroE = YExpZero & YFracZero; assign ZZeroE = ZExpZero & ZFracZero; - assign BiasE = 13'h3ff; // always use 1023 because exponents are unpacked to double precision + assign BiasE = 11'h3ff; // always use 1023 because exponents are unpacked to double precision endmodule \ No newline at end of file diff --git a/wally-pipelined/src/generic/flop.sv b/wally-pipelined/src/generic/flop.sv index cb583de2e..fc0bf430f 100644 --- a/wally-pipelined/src/generic/flop.sv +++ b/wally-pipelined/src/generic/flop.sv @@ -81,6 +81,18 @@ module flopenr #(parameter WIDTH = 8) ( else if (en) q <= #1 d; endmodule +// flop with enable, asynchronous set +module flopens #(parameter WIDTH = 8) ( + input logic clk, set, en, + input logic [WIDTH-1:0] d, + output logic [WIDTH-1:0] q); + + always_ff @(posedge clk, posedge set) + if (set) q <= #1 1; + else if (en) q <= #1 d; +endmodule + + // flop with enable, asynchronous load module flopenl #(parameter WIDTH = 8, parameter type TYPE=logic [WIDTH-1:0]) ( input logic clk, load, en, diff --git a/wally-pipelined/src/mmu/tlbramline.sv b/wally-pipelined/src/mmu/tlbramline.sv index d6d2523c8..98a954f85 100644 --- a/wally-pipelined/src/mmu/tlbramline.sv +++ b/wally-pipelined/src/mmu/tlbramline.sv @@ -25,7 +25,7 @@ `include "wally-config.vh" -module tlbramline #(parameter WIDTH) +module tlbramline #(parameter WIDTH = 22) (input logic clk, reset, input logic re, we, input logic [WIDTH-1:0] d, @@ -37,4 +37,4 @@ module tlbramline #(parameter WIDTH) flopenr #(WIDTH) pteflop(clk, reset, we, d, line); assign q = re ? line : 0; assign PTE_G = line[5]; // send global bit to CAM as part of ASID matching -endmodule \ No newline at end of file +endmodule diff --git a/wally-pipelined/src/muldiv/div/div64_sim/flop.sv b/wally-pipelined/src/muldiv/div/div64_sim/flop.sv index 8a9992474..7f20fb7fb 100644 --- a/wally-pipelined/src/muldiv/div/div64_sim/flop.sv +++ b/wally-pipelined/src/muldiv/div/div64_sim/flop.sv @@ -77,7 +77,7 @@ module flopenr #(parameter WIDTH = 8) ( if (reset) q <= #1 0; else if (en) q <= #1 d; endmodule - +/* // flop with enable, asynchronous load module flopenl #(parameter WIDTH = 8, parameter type TYPE=logic [WIDTH-1:0]) ( input logic clk, load, en, @@ -89,7 +89,7 @@ module flopenl #(parameter WIDTH = 8, parameter type TYPE=logic [WIDTH-1:0]) ( if (load) q <= #1 val; else if (en) q <= #1 d; endmodule - +*/ // flop with asynchronous reset, synchronous clear module floprc #(parameter WIDTH = 8) ( input logic clk, diff --git a/wally-pipelined/src/muldiv/intdivrestoring.sv b/wally-pipelined/src/muldiv/intdivrestoring.sv index 5928a5018..cf0d5341b 100644 --- a/wally-pipelined/src/muldiv/intdivrestoring.sv +++ b/wally-pipelined/src/muldiv/intdivrestoring.sv @@ -55,7 +55,7 @@ module intdivrestoring ( ////////////////////////////// // Divider control signals - assign DivStartE = DivE & (state == IDLE); + assign DivStartE = DivE & (state == IDLE) & ~StallM; assign DivBusyE = (state == BUSY) | DivStartE; // Handle sign extension for W-type instructions diff --git a/wally-pipelined/src/muldiv/mul.sv b/wally-pipelined/src/muldiv/mul.sv index cff07e675..5ab8b73ad 100644 --- a/wally-pipelined/src/muldiv/mul.sv +++ b/wally-pipelined/src/muldiv/mul.sv @@ -60,10 +60,6 @@ module mul ( // Execute Stage: Compute partial products ////////////////////////////// - // portions of product - //assign Pprime = {1'b0, SrcAE[`XLEN-2:0]} * {1'b0, SrcBE[`XLEN-2:0]}; - - // *** assumes unsigned multiplication assign Aprime = {1'b0, SrcAE[`XLEN-2:0]}; assign Bprime = {1'b0, SrcBE[`XLEN-2:0]}; redundantmul #(`XLEN) bigmul(.a(Aprime), .b(Bprime), .out0(PP0E), .out1(PP1E)); @@ -77,8 +73,6 @@ module mul ( // assign MULHU = (Funct3E == 2'b11); // signal unused // Handle signs -// assign PP0E = 0; -// assign PP1E = Pprime; // same for all flavors assign PP2E = {2'b00, (MULH | MULHSU) ? ~PA : PA, {(`XLEN-1){1'b0}}}; assign PP3E = {2'b00, (MULH) ? ~PB : PB, {(`XLEN-1){1'b0}}}; always_comb diff --git a/wally-pipelined/src/muldiv/mult_cs.sv b/wally-pipelined/src/muldiv/mult_cs.sv new file mode 100644 index 000000000..f297401c3 --- /dev/null +++ b/wally-pipelined/src/muldiv/mult_cs.sv @@ -0,0 +1,101 @@ +/////////////////////////////////////////// +// mul_cs.sv +// +// Written: james.stine@okstate.edu 17 October 2021 +// Modified: +// +// Purpose: Carry/Save Multiplier output with Wallace Reduction +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +module mult_cs #(parameter WIDTH = 8) + (a, b, tc, sum, carry); + + input logic [WIDTH-1:0] a; + input logic [WIDTH-1:0] b; + input logic tc; + + output logic [2*WIDTH-1:0] sum; + output logic [2*WIDTH-1:0] carry; + + // PP array + logic [2*WIDTH-1:0] pp_array [0:WIDTH-1]; + logic [2*WIDTH-1:0] next_pp_array [0:WIDTH-1]; + logic [2*WIDTH-1:0] tmp_sum, tmp_carry; + logic [2*WIDTH-1:0] temp_pp; + logic [2*WIDTH-1:0] tmp_pp_carry; + logic [WIDTH-1:0] temp_b; + logic temp_bitgroup; + integer bit_pair, height, i; + + always_comb + begin + // For each multiplicand PP generation + for (bit_pair=0; bit_pair < WIDTH; bit_pair=bit_pair+1) + begin + // Shift to the right via P&H + temp_b = (b >> (bit_pair)); + temp_bitgroup = temp_b[0]; + // PP generation + case (temp_bitgroup) + 1'b0 : temp_pp = {2*WIDTH-1{1'b0}}; + 1'b1 : temp_pp = a; + default : temp_pp = {2*WIDTH-1{1'b0}}; + endcase + // Shift to the left via P&H + temp_pp = temp_pp << (bit_pair); + pp_array[bit_pair] = temp_pp; + end + + // Height is multiplier + height = WIDTH; + + // Wallace Tree PP reduction + while (height > 2) + begin + for (i=0; i < (height/3); i=i+1) + begin + next_pp_array[i*2] = pp_array[i*3]^pp_array[i*3+1]^pp_array[i*3+2]; + tmp_pp_carry = (pp_array[i*3] & pp_array[i*3+1]) | + (pp_array[i*3+1] & pp_array[i*3+2]) | + (pp_array[i*3] & pp_array[i*3+2]); + next_pp_array[i*2+1] = tmp_pp_carry << 1; + end + // Reasssign not divisible by 3 rows to next_pp_array + if ((height % 3) > 0) + begin + for (i=0; i < (height % 3); i=i+1) + next_pp_array[2 * (height/3) + i] = pp_array[3 * (height/3) + i]; + end + // Put back values in pp_array to start again + for (i=0; i < WIDTH; i=i+1) + pp_array[i] = next_pp_array[i]; + // Reduce height + height = height - (height/3); + end + // Sum is first row in reduced array + tmp_sum = pp_array[0]; + // Carry is second row in reduced array + tmp_carry = pp_array[1]; + end + + assign sum = tmp_sum; + assign carry = tmp_carry; + +endmodule // mult_cs + diff --git a/wally-pipelined/src/muldiv/redundantmul.sv b/wally-pipelined/src/muldiv/redundantmul.sv index 6cbe936dd..9c8ade60a 100644 --- a/wally-pipelined/src/muldiv/redundantmul.sv +++ b/wally-pipelined/src/muldiv/redundantmul.sv @@ -26,16 +26,25 @@ `include "wally-config.vh" module redundantmul #(parameter WIDTH =8)( - input logic [WIDTH-1:0] a,b, + input logic [WIDTH-1:0] a,b, output logic [2*WIDTH-1:0] out0, out1); - generate - if (`DESIGN_COMPILER == 1) - DW02_multp #(WIDTH, WIDTH, 2*WIDTH) bigmul(.a, .b, .tc(1'b0), .out0, .out1); - else begin - assign out0 = 0; - assign out1 = a*b; - end + logic [2*WIDTH-1+2:0] tmp_out0; + logic [2*WIDTH-1+2:0] tmp_out1; + + generate + if (`DESIGN_COMPILER == 1) + begin + DW02_multp #(WIDTH, WIDTH, 2*WIDTH+2) mul(.a, .b, .tc(1'b0), .out0(tmp_out0), .out1(tmp_out1)); + assign out0 = tmp_out0[2*WIDTH-1:0]; + assign out1 = tmp_out1[2*WIDTH-1:0]; + end + else if (`DESIGN_COMPILER == 2) + mult_cs #(WIDTH) mul(.a, .b, .tc(1'b0), .sum(out0), .carry(out1)); + else begin // force a nonredunant multipler. This will simulate properly and also is appropriate for FPGAs. + assign out0 = a * b; + assign out1 = 0; + end endgenerate endmodule diff --git a/wally-pipelined/src/privileged/csrm.sv b/wally-pipelined/src/privileged/csrm.sv index c40801dcb..4f0fa138f 100644 --- a/wally-pipelined/src/privileged/csrm.sv +++ b/wally-pipelined/src/privileged/csrm.sv @@ -116,19 +116,17 @@ module csrm #(parameter assign IllegalCSRMWriteReadonlyM = CSRMWriteM && (CSRAdrM == MVENDORID || CSRAdrM == MARCHID || CSRAdrM == MIMPID || CSRAdrM == MHARTID); // CSRs - flopenl #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, `XLEN'b0, MTVEC_REGW); //busybear: changed reset value to 0 + flopenr #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, MTVEC_REGW); //busybear: changed reset value to 0 generate if (`S_SUPPORTED | (`U_SUPPORTED & `N_SUPPORTED)) begin // DELEG registers should exist - flopenl #(`XLEN) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM & MEDELEG_MASK /*12'h7FF*/, `XLEN'b0, MEDELEG_REGW); - flopenl #(`XLEN) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM & MIDELEG_MASK /*12'h222*/, `XLEN'b0, MIDELEG_REGW); + flopenr #(`XLEN) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM & MEDELEG_MASK /*12'h7FF*/, MEDELEG_REGW); + flopenr #(`XLEN) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM & MIDELEG_MASK /*12'h222*/, MIDELEG_REGW); end else begin assign MEDELEG_REGW = 0; assign MIDELEG_REGW = 0; end endgenerate -// flopenl #(`XLEN) MIPreg(clk, reset, WriteMIPM, CSRWriteValM, zero, MIP_REGW); -// flopenl #(`XLEN) MIEreg(clk, reset, WriteMIEM, CSRWriteValM, zero, MIE_REGW); flopenr #(`XLEN) MSCRATCHreg(clk, reset, WriteMSCRATCHM, CSRWriteValM, MSCRATCH_REGW); flopenr #(`XLEN) MEPCreg(clk, reset, WriteMEPCM, NextEPCM, MEPC_REGW); flopenr #(`XLEN) MCAUSEreg(clk, reset, WriteMCAUSEM, NextCauseM, MCAUSE_REGW); @@ -136,13 +134,13 @@ module csrm #(parameter else flopenr #(`XLEN) MTVALreg(clk, reset, WriteMTVALM, NextMtvalM, MTVAL_REGW); generate if (`BUSYBEAR == 1) - flopenl #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, {CSRWriteValM[31:2],1'b0,CSRWriteValM[0]}, 32'b0, MCOUNTEREN_REGW); + flopenr #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, {CSRWriteValM[31:2],1'b0,CSRWriteValM[0]}, MCOUNTEREN_REGW); else if (`BUILDROOT == 1) - flopenl #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], 32'h0, MCOUNTEREN_REGW); + flopenr #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW); else - flopenl #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], 32'hFFFFFFFF, MCOUNTEREN_REGW); + flopens #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW); endgenerate - flopenl #(32) MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], 32'h0, MCOUNTINHIBIT_REGW); + flopenr #(32) MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], MCOUNTINHIBIT_REGW); // There are PMP_ENTRIES = 0, 16, or 64 PMPADDR registers, each of which has its own flop diff --git a/wally-pipelined/src/privileged/csrs.sv b/wally-pipelined/src/privileged/csrs.sv index c70e3a1c5..c3e42f563 100644 --- a/wally-pipelined/src/privileged/csrs.sv +++ b/wally-pipelined/src/privileged/csrs.sv @@ -87,10 +87,10 @@ module csrs #(parameter assign WriteSCOUNTERENM = CSRSWriteM && (CSRAdrM == SCOUNTEREN) && ~StallW; // CSRs - flopenl #(`XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, `XLEN'b0, STVEC_REGW); //busybear: change reset to 0 + flopenr #(`XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, STVEC_REGW); //busybear: change reset to 0 flopenr #(`XLEN) SSCRATCHreg(clk, reset, WriteSSCRATCHM, CSRWriteValM, SSCRATCH_REGW); flopenr #(`XLEN) SEPCreg(clk, reset, WriteSEPCM, NextEPCM, SEPC_REGW); - flopenl #(`XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, NextCauseM, `XLEN'b0, SCAUSE_REGW); + flopenr #(`XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, NextCauseM, SCAUSE_REGW); if(`QEMU) assign STVAL_REGW = `XLEN'b0; else flopenr #(`XLEN) STVALreg(clk, reset, WriteSTVALM, NextMtvalM, STVAL_REGW); if (`MEM_VIRTMEM) @@ -98,17 +98,17 @@ module csrs #(parameter else assign SATP_REGW = 0; // hardwire to zero if virtual memory not supported if (`BUSYBEAR == 1) - flopenl #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, {CSRWriteValM[31:2],1'b0,CSRWriteValM[0]}, 32'b0, SCOUNTEREN_REGW); + flopenr #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, {CSRWriteValM[31:2],1'b0,CSRWriteValM[0]}, SCOUNTEREN_REGW); else if (`BUILDROOT == 1) - flopenl #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], 32'h0, SCOUNTEREN_REGW); + flopenr #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW); else - flopenl #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], 32'hFFFFFFFF, SCOUNTEREN_REGW); + flopens #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW); if (`N_SUPPORTED) begin logic WriteSEDELEGM, WriteSIDELEGM; assign WriteSEDELEGM = CSRSWriteM && (CSRAdrM == SEDELEG); assign WriteSIDELEGM = CSRSWriteM && (CSRAdrM == SIDELEG); - flopenl #(`XLEN) SEDELEGreg(clk, reset, WriteSEDELEGM, CSRWriteValM & SEDELEG_MASK /* 12'h1FF */, `XLEN'b0, SEDELEG_REGW); - flopenl #(`XLEN) SIDELEGreg(clk, reset, WriteSIDELEGM, CSRWriteValM, `XLEN'b0, SIDELEG_REGW); + flopenr #(`XLEN) SEDELEGreg(clk, reset, WriteSEDELEGM, CSRWriteValM & SEDELEG_MASK, SEDELEG_REGW); + flopenr #(`XLEN) SIDELEGreg(clk, reset, WriteSIDELEGM, CSRWriteValM, SIDELEG_REGW); end else begin assign SEDELEG_REGW = 0; assign SIDELEG_REGW = 0; diff --git a/wally-pipelined/src/wally/wallypipelinedsoc.sv b/wally-pipelined/src/wally/wallypipelinedsoc.sv index 93710b55d..87b39533e 100644 --- a/wally-pipelined/src/wally/wallypipelinedsoc.sv +++ b/wally-pipelined/src/wally/wallypipelinedsoc.sv @@ -92,9 +92,19 @@ module wallypipelinedsoc ( //assign SDCDatIn = SDCDat; // when write supported this will be a tristate // instantiate processor and memories - wallypipelinedhart hart(.*); + wallypipelinedhart hart(.clk, .reset, + .PCF, .TimerIntM, .ExtIntM, .SwIntM, .DataAccessFaultM, + .MTIME_CLINT, .MTIMECMP_CLINT, .rd2, + .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, + .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, + .HSELRegions, .HADDRD, .HSIZED, .HWRITED + ); // instructions now come from uncore memory. This line can be removed at any time. // imem imem(.AdrF(PCF[`XLEN-1:1]), .*); // temporary until uncore memory is finished*** - uncore uncore(.HWDATAIN(HWDATA), .*); + uncore uncore(.HCLK, .HRESETn, + .HADDR, .HWDATAIN(HWDATA), .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, + .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HADDRD, .HSIZED, .HWRITED, + .TimerIntM, .SwIntM, .ExtIntM, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT, .MTIMECMP_CLINT +); endmodule diff --git a/wally-pipelined/srt/Makefile b/wally-pipelined/srt/Makefile new file mode 100644 index 000000000..73a0b75fa --- /dev/null +++ b/wally-pipelined/srt/Makefile @@ -0,0 +1,7 @@ +all: sqrttestgen testgen + +sqrttestgen: sqrttestgen.c + gcc sqrttestgen.c -lm -o sqrttestgen + +testgen: testgen.c + gcc testgen.c -lm -o testgen diff --git a/wally-pipelined/srt/sim-srt b/wally-pipelined/srt/sim-srt new file mode 100755 index 000000000..d0d5236a8 --- /dev/null +++ b/wally-pipelined/srt/sim-srt @@ -0,0 +1,2 @@ +vsim -do "do srt.do" + diff --git a/wally-pipelined/srt/sqrttestgen.c b/wally-pipelined/srt/sqrttestgen.c new file mode 100644 index 000000000..7b8cacd3f --- /dev/null +++ b/wally-pipelined/srt/sqrttestgen.c @@ -0,0 +1,89 @@ +/* sqrttestgen.c */ + +/* Written 19 October 2021 David_Harris@hmc.edu + + This program creates test vectors for mantissa component + of an IEEE floating point square root. + */ + +/* #includes */ + +#include +#include +#include + +/* Constants */ + +#define ENTRIES 17 +#define RANDOM_VECS 500 + +/* Prototypes */ + +void output(FILE *fptr, double a, double r); +void printhex(FILE *fptr, double x); +double random_input(void); + +/* Main */ + +void main(void) +{ + FILE *fptr; + double a, b, r; + double list[ENTRIES] = {1, 1.5, 1.25, 1.125, 1.0625, + 1.75, 1.875, 1.99999, + 1.1, 1.2, 1.01, 1.001, 1.0001, + 1/1.1, 1/1.5, 1/1.25, 1/1.125}; + int i, j; + + if ((fptr = fopen("sqrttestvectors","w")) == NULL) { + fprintf(stderr, "Couldn't write sqrttestvectors file\n"); + exit(1); + } + + for (i=0; i2) m /= 2; + for (i=0; i<52; i+=4) { + m = m - floor(m); + m = m * 16; + val = (int)(m)%16; + fprintf(fptr, "%x", val); + } +} + +double random_input(void) +{ + return 1.0 + rand()/32767.0; +} + diff --git a/wally-pipelined/srt/sqrttestvectors b/wally-pipelined/srt/sqrttestvectors new file mode 100644 index 000000000..392053b93 --- /dev/null +++ b/wally-pipelined/srt/sqrttestvectors @@ -0,0 +1,517 @@ +0000000000000_0000000000000 +8000000000000_3988e1409212e +4000000000000_1e3779b97f4a8 +2000000000000_0f876ccdf6cd9 +1000000000000_07e0f66afed07 +c000000000000_52a7fa9d2f8ea +e000000000000_5e8add236a58f +ffff583a53b8e_6a09ab16ee3d0 +199999999999a_0c7ebc96a56f6 +3333333333333_186f174f88472 +028f5c28f5c29_0146dd68287f3 +004189374bc6a_0020c2830b9c7 +00068db8bac71_000346d6ff116 +d1745d1745d17_e82c3f9d89e1c +5555555555555_a20bd700c2c3e +999999999999a_c9f25c5bfedd9 +c71c71c71c71c_e2b7dddfefa66 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file mode 100644 index 000000000..c86a0dbfd --- /dev/null +++ b/wally-pipelined/srt/srt.do @@ -0,0 +1,28 @@ +# srt.do +# +# David_Harris@hmc.edu 19 October 2021 + +# Use this wally-pipelined.do file to run this example. +# Either bring up ModelSim and type the following at the "ModelSim>" prompt: +# do wally-pipelined.do +# or, to run from a shell, type the following at the shell prompt: +# vsim -do wally-pipelined.do -c +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +# create library +if [file exists work] { + vdel -all +} +vlib work + +vlog srt.sv +vopt +acc work.testbench -o workopt +vsim workopt + +-- display input and output signals as hexidecimal values +do ./srt-waves.do + +-- Run the Simulation +run -all diff --git a/wally-pipelined/srt/srt.sv b/wally-pipelined/srt/srt.sv new file mode 100644 index 000000000..707840cee --- /dev/null +++ b/wally-pipelined/srt/srt.sv @@ -0,0 +1,355 @@ +/////////////////////////////////////////////////////// +// srt.sv // +// // +// Written 10/31/96 by David Harris harrisd@leland // +// Updated 10/19/21 David_Harris@hmc.edu // +// // +// This file models a simple Radix 2 SRT divider. // +// // +/////////////////////////////////////////////////////// + +// This Verilog file models a radix 2 SRT divider which +// produces one quotient digit per cycle. The divider +// keeps the partial remainder in carry-save form. + +///////// +// srt // +///////// +module srt(input logic clk, + input logic req, + input logic sqrt, // 1 to compute sqrt(a), 0 to compute a/b + input logic [51:0] a, b, + output logic [54:0] rp, rm); + + // A simple Radix 2 SRT divider/sqrt + + + // Internal signals + + logic [55:0] ps, pc; // partial remainder in carry-save form + logic [55:0] d; // divisor + logic [55:0] psa, pca; // partial remainder result of csa + logic [55:0] psn, pcn; // partial remainder for next cycle + logic [55:0] dn; // divisor for next cycle + logic [55:0] dsel; // selected divisor multiple + logic qp, qz, qm; // quotient is +1, 0, or -1 + logic [55:0] d_b; // inverse of divisor + + // Top Muxes and Registers + // When start is asserted, the inputs are loaded into the divider. + // Otherwise, the divisor is retained and the partial remainder + // is fed back for the next iteration. + mux2 psmux({psa[54:0], 1'b0}, {4'b0001, a}, req, psn); + flop psflop(clk, psn, ps); + mux2 pcmux({pca[54:0], 1'b0}, 56'b0, req, pcn); + flop pcflop(clk, pcn, pc); + mux2 dmux(d, {4'b0001, b}, req, dn); + flop dflop(clk, dn, d); + + // Quotient Selection logic + // Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm) + // Accumulate quotient digits in a shift register + qsel qsel(ps[55:52], pc[55:52], qp, qz, qm); + qacc qacc(clk, req, qp, qz, qm, rp, rm); + + // Divisor Selection logic + inv dinv(d, d_b); + mux3 divisorsel(d_b, 56'b0, d, qp, qz, qm, dsel); + + // Partial Product Generation + csa csa(ps, pc, dsel, qp, psa, pca); +endmodule + +////////// +// mux2 // +////////// +module mux2(input logic [55:0] in0, in1, + input logic sel, + output logic [55:0] out); + + assign #1 out = sel ? in1 : in0; +endmodule + +////////// +// flop // +////////// +module flop(clk, in, out); + input clk; + input [55:0] in; + output [55:0] out; + + logic [55:0] state; + + always @(posedge clk) + state <= #1 in; + + assign #1 out = state; +endmodule + +////////// +// qsel // +////////// +module qsel(input logic [55:52] ps, pc, + output logic qp, qz, qm); + + logic [55:52] p, g; + logic magnitude, sign, cout; + + // The quotient selection logic is presented for simplicity, not + // for efficiency. You can probably optimize your logic to + // select the proper divisor with less delay. + + // Quotient equations from EE371 lecture notes 13-20 + assign p = ps ^ pc; + assign g = ps & pc; + + assign #1 magnitude = ~(&p[54:52]); + assign #1 cout = g[54] | (p[54] & (g[53] | p[53] & g[52])); + assign #1 sign = p[55] ^ cout; +/* assign #1 magnitude = ~((ps[54]^pc[54]) && (ps[53]^pc[53]) && + (ps[52]^pc[52])); + assign #1 sign = (ps[55]^pc[55])^ + (ps[54] && pc[54] || ((ps[54]^pc[54]) && + (ps[53]&&pc[53] || ((ps[53]^pc[53]) && + (ps[52]&&pc[52]))))); */ + + // Produce quotient = +1, 0, or -1 + assign #1 qp = magnitude && ~sign; + assign #1 qz = ~magnitude; + assign #1 qm = magnitude && sign; +endmodule + +////////// +// qacc // +////////// +module qacc(clk, req, qp, qz, qm, rp, rm); + input clk; + input req; + input qp; + input qz; + input qm; + output [54:0] rp; + output [54:0] rm; + + logic [54:0] rp, rm; // quotient bit is +/- 1; + logic [7:0] count; + + always @(posedge clk) + begin + if (req) + begin + rp <= #1 0; + rm <= #1 0; + end + else + begin + rp <= #1 {rp[54:0], qp}; + rm <= #1 {rm[54:0], qm}; + end + end +endmodule + +///////// +// inv // +///////// +module inv(input logic [55:0] in, + output logic [55:0] out); + + assign #1 out = ~in; +endmodule + +////////// +// mux3 // +////////// +module mux3(in0, in1, in2, sel0, sel1, sel2, out); + input [55:0] in0; + input [55:0] in1; + input [55:0] in2; + input sel0; + input sel1; + input sel2; + output [55:0] out; + + // lazy inspection of the selects + // really we should make sure selects are mutually exclusive + assign #1 out = sel0 ? in0 : (sel1 ? in1 : in2); +endmodule + +///////// +// csa // +///////// +module csa(in1, in2, in3, cin, out1, out2); + input [55:0] in1; + input [55:0] in2; + input [55:0] in3; + input cin; + output [55:0] out1; + output [55:0] out2; + + // This block adds in1, in2, in3, and cin to produce + // a result out1 / out2 in carry-save redundant form. + // cin is just added to the least significant bit and + // is required to handle adding a negative divisor. + // Fortunately, the carry (out2) is shifted left by one + // bit, leaving room in the least significant bit to + // insert cin. + + assign #1 out1 = in1 ^ in2 ^ in3; + assign #1 out2 = {in1[54:0] & (in2[54:0] | in3[54:0]) | + (in2[54:0] & in3[54:0]), cin}; +endmodule + +////////////// +// finaladd // +////////////// +module finaladd(rp, rm, r); + input [54:0] rp; + input [54:0] rm; + output [51:0] r; + + logic [54:0] diff; + + // this magic block performs the final addition for you + // to convert the positive and negative quotient digits + // into a normalized mantissa. It returns the 52 bit + // mantissa after shifting to guarantee a leading 1. + // You can assume this block operates in one cycle + // and do not need to budget it in your area and power + // calculations. + + // Since no rounding is performed, the result may be too + // small by one unit in the least significant place (ulp). + // The checker ignores such an error. + + assign #1 diff = rp - rm; + assign #1 r = diff[54] ? diff[53:2] : diff[52:1]; +endmodule + +///////////// +// counter // +///////////// +module counter(input logic clk, + input logic req, + output logic done); + + logic [5:0] count; + + // This block of control logic sequences the divider + // through its iterations. You may modify it if you + // build a divider which completes in fewer iterations. + // You are not responsible for the (trivial) circuit + // design of the block. + + always @(posedge clk) + begin + if (count == 54) done <= #1 1; + else if (done || req) done <= #1 0; + if (req) count <= #1 0; + else count <= #1 count+1; + end +endmodule + +/////////// +// clock // +/////////// +module clock(clk); + output clk; + + // Internal clk signal + logic clk; + +endmodule + +////////// +// testbench // +////////// +module testbench; + logic clk; + logic req; + logic done; + logic [51:0] a; + logic [51:0] b; + logic [51:0] r; + logic [54:0] rp, rm; // positive quotient digits + + // Test parameters + parameter MEM_SIZE = 40000; + parameter MEM_WIDTH = 52+52+52; + + `define memr 51:0 + `define memb 103:52 + `define mema 155:104 + + // Test logicisters + logic [MEM_WIDTH-1:0] Tests [0:MEM_SIZE]; // Space for input file + logic [MEM_WIDTH-1:0] Vec; // Verilog doesn't allow direct access to a + // bit field of an array + logic [51:0] correctr, nextr; + integer testnum, errors; + + // Divider + srt srt(clk, req, a, b, rp, rm); + + // Final adder converts quotient digits to 2's complement & normalizes + finaladd finaladd(rp, rm, r); + + // Counter + counter counter(clk, req, done); + + + initial + forever + begin + clk = 1; #17; + clk = 0; #16; + end + + + // Read test vectors from disk + initial + begin + testnum = 0; + errors = 0; + $readmemh ("testvectors", Tests); + Vec = Tests[testnum]; + a = Vec[`mema]; + b = Vec[`memb]; + nextr = Vec[`memr]; + req <= #5 1; + end + + // Apply directed test vectors read from file. + + always @(posedge clk) + begin + if (done) + begin + req <= #5 1; + $display("result was %h, should be %h\n", r, correctr); + if ((correctr - r) > 1) // check if accurate to 1 ulp + begin + errors = errors+1; + $display("failed\n"); + $stop; + end + if (a === 52'hxxxxxxxxxxxxx) + begin + $display("Tests completed successfully"); + $stop; + end + end + if (req) + begin + req <= #5 0; + correctr = nextr; + testnum = testnum+1; + Vec = Tests[testnum]; + $display("a = %h b = %h",a,b); + a = Vec[`mema]; + b = Vec[`memb]; + nextr = Vec[`memr]; + end + end + +endmodule + diff --git a/wally-pipelined/srt/testgen.c b/wally-pipelined/srt/testgen.c new file mode 100644 index 000000000..98d52819b --- /dev/null +++ b/wally-pipelined/srt/testgen.c @@ -0,0 +1,94 @@ +/* testgen.c */ + +/* Written 10/31/96 by David Harris + + This program creates test vectors for mantissa component + of an IEEE floating point divider. + */ + +/* #includes */ + +#include +#include +#include + +/* Constants */ + +#define ENTRIES 17 +#define RANDOM_VECS 500 + +/* Prototypes */ + +void output(FILE *fptr, double a, double b, double r); +void printhex(FILE *fptr, double x); +double random_input(void); + +/* Main */ + +void main(void) +{ + FILE *fptr; + double a, b, r; + double list[ENTRIES] = {1, 1.5, 1.25, 1.125, 1.0625, + 1.75, 1.875, 1.99999, + 1.1, 1.2, 1.01, 1.001, 1.0001, + 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b/wally-pipelined/testbench/testbench-f64.sv index a9dd9ad2a..e3cdc84d9 100755 --- a/wally-pipelined/testbench/testbench-f64.sv +++ b/wally-pipelined/testbench/testbench-f64.sv @@ -30,7 +30,7 @@ module testbench (); logic XExpMaxE; logic XNormE; logic FDivBusyE; - + logic start; logic reset; @@ -49,7 +49,6 @@ module testbench (); integer handle3; integer desc3; - integer desc4; // instantiate device under test unpacking unpacking(.X(op1), .Y(op2), .Z(64'h0), .FOpCtrlE, .FmtE, @@ -57,16 +56,13 @@ module testbench (); .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .BiasE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .XNormE); fpdiv fdivsqrt (.op1, .op2, .rm(FrmE[1:0]), .op_type(FOpCtrlE[0]), - .reset, .clk, .start, .P(FmtE), .OvEn(1'b1), .UnEn(1'b1), + .reset, .clk, .start, .P(~FmtE), .OvEn(1'b0), .UnEn(1'b0), .XNaNQ(XNaNE), .YNaNQ(YNaNE), .XInfQ(XInfE), .YInfQ(YInfE), .XZeroQ(XZeroE), .YZeroQ(YZeroE), .FDivBusyE, .done(done), .AS_Result(AS_Result), .Flags(Flags)); + // current fpdivsqrt does not operation on denorms yet - assign XZeroM = (op1[51:0] == 52'h0); - assign YZeroM = (op2[51:0] == 52'h0); - assign XDenorm = XZeroE & ~XZeroM; - assign YDenorm = YZeroE & ~YZeroM; - assign Denorm = XDenorm | YDenorm; + assign Denorm = XDenormE | YDenormE | Flags[3]; // generate clock to sequence tests always @@ -77,7 +73,7 @@ module testbench (); initial begin handle3 = $fopen("f64_div_rne.out"); - $readmemh("../testbench/fp/f64_div_rne.tv", testvectors); + $readmemh("../testbench/fp/vectors/f64_div_rne.tv", testvectors); vectornum = 0; errors = 0; start = 1'b0; // reset @@ -90,7 +86,7 @@ module testbench (); // Operation (if applicable) #0 op_type = 1'b0; // Precision (32-bit or 64-bit) - #0 FmtE = 1'b0; + #0 FmtE = 1'b1; // From fctrl logic to dictate operation #0 FOpCtrlE = 3'b000; // Rounding Mode @@ -114,8 +110,6 @@ module testbench (); @(posedge clk); $fdisplay(desc3, "%h_%h_%h_%b_%b | %h_%b", op1, op2, AS_Result, Flags, Denorm, yexpected, (AS_Result==yexpected)); vectornum = vectornum + 1; - if (vectornum == 1) - $finish; if (testvectors[vectornum] === 200'bx) begin $display("%d tests completed", vectornum); $finish; diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index 10987f526..5b94bbc8c 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -38,7 +38,7 @@ module testbench(); - parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*3100000; // # of instructions at which to turn on waves in graphical sim + parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*6300000; // # of instructions at which to turn on waves in graphical sim string ProgramAddrMapFile, ProgramLabelMapFile; /////////////////////////////////////////////////////////////////////////////// diff --git a/wally-pipelined/testbench/tests.vh b/wally-pipelined/testbench/tests.vh index 86746150b..ac1136265 100644 --- a/wally-pipelined/testbench/tests.vh +++ b/wally-pipelined/testbench/tests.vh @@ -27,22 +27,22 @@ `define RISCVARCHTEST "1" string tvpaths[] = '{ - "../../imperas-riscv-tests/work/", - "/home/harris/github/riscv-arch-test/work/" + "../../tests/imperas-riscv-tests/work/", + "../../addins/riscv-arch-test/work/" }; string imperas32mmu[] = '{ `IMPERASTEST, "rv32mmu/WALLY-MMU-SV32", "3000" - //"rv32mmu/WALLY-PMA", "3000", + //"rv32mmu/WALLY-PMP", "3000", //"rv32mmu/WALLY-PMA", "3000" }; string imperas64mmu[] = '{ `IMPERASTEST, "rv64mmu/WALLY-MMU-SV48", "3000", - "rv64mmu/WALLY-MMU-SV39", "3000" - //"rv64mmu/WALLY-PMA", "3000", + "rv64mmu/WALLY-MMU-SV39", "3000", + "rv64mmu/WALLY-PMP", "3000" //"rv64mmu/WALLY-PMA", "3000" };