From 604c40243b0500af388bd132613819b192b238d1 Mon Sep 17 00:00:00 2001
From: Jacob Pease <jacobpease@protonmail.com>
Date: Wed, 23 Aug 2023 10:22:55 -0500
Subject: [PATCH 01/32] Updated README to explain usage of flash-sd.sh

---
 linux/README.MD | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/linux/README.MD b/linux/README.MD
index 68de94f03..2b9ec3ab3 100644
--- a/linux/README.MD
+++ b/linux/README.MD
@@ -49,4 +49,13 @@ You'll find the resulting disassembled files in `<BUILDROOT>/output/images/disas
 
 ## Creating a Bootable SD Card <a name="sdcard"></a>
 
+To flash a bootable sd card for Wally's bootloader, use the `flash-sd.sh` script located in `<WALLY>/linux/sdcard`. The script allows you to specify which buildroot directory you would like to use and to specify the device tree. By default it is set up for the default location of buildroot in `/opt/riscv` and uses the vcu108 device tree. To use the script with your own buildroot directory and device tree, type:
+
+    $ cd sdcard
+    $ ./flash-sd.sh -b <path/to/buildroot> -d <device tree name> <DEVICE>
+    
+    for example
+    
+    $ ./flash-sd.sh -b ~/repos/buildroot -d wally-vcu118.dtb /dev/sdb
+    
 

From 494efe16ac4ff3023abe8c18e79e464b484969ac Mon Sep 17 00:00:00 2001
From: Jacob Pease <jacobpease@protonmail.com>
Date: Wed, 23 Aug 2023 10:54:35 -0500
Subject: [PATCH 02/32] Minor formatting adjustments.

---
 linux/sdcard/flash-sd.sh | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/linux/sdcard/flash-sd.sh b/linux/sdcard/flash-sd.sh
index 8b1b6ebdc..7f58f6d45 100755
--- a/linux/sdcard/flash-sd.sh
+++ b/linux/sdcard/flash-sd.sh
@@ -22,6 +22,7 @@ BOLDYELLOW="\e[1;33m"
 NC="\e[0m"
 NAME="$BOLDGREEN"${0:2}:"$NC"
 ERRORTEXT="$BOLDRED"ERROR:"$NC"
+WARNINGTEXT="$BOLDYELLOW"Warning:"$NC"
 
 # Default values for buildroot and device tree
 RISCV=/opt/riscv
@@ -150,16 +151,16 @@ if [[ $REPLY =~ ^[Yy]$ ]] ; then
 
     sleep 3
 
-    echo -e "$NAME: Copying binaries into their partitions."
+    echo -e "$NAME Copying binaries into their partitions."
     DD_FLAGS="bs=4k iflag=fullblock oflag=direct conv=fsync status=progress"
 
-    echo -e "$NAME: Copying device tree"
+    echo -e "$NAME Copying device tree"
     sudo dd if=$DEVICE_TREE of="$SDCARD"1 $DD_FLAGS
 
-    echo -e "$NAME: Copying OpenSBI"
+    echo -e "$NAME Copying OpenSBI"
     sudo dd if=$FW_JUMP of="$SDCARD"2 $DD_FLAGS
 
-    echo -e "$NAME: Copying Kernel"
+    echo -e "$NAME Copying Kernel"
     sudo dd if=$LINUX_KERNEL of="$SDCARD"3 $DD_FLAGS
 
     sudo mkfs.ext4 "$SDCARD"4

From 1e834f2d5facf46ff456b1797a2b20a495366314 Mon Sep 17 00:00:00 2001
From: Jacob Pease <jacobpease@protonmail.com>
Date: Wed, 23 Aug 2023 12:42:20 -0500
Subject: [PATCH 03/32] Minor color adjustment

---
 linux/sdcard/flash-sd.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/linux/sdcard/flash-sd.sh b/linux/sdcard/flash-sd.sh
index 7f58f6d45..9e00e0600 100755
--- a/linux/sdcard/flash-sd.sh
+++ b/linux/sdcard/flash-sd.sh
@@ -111,7 +111,7 @@ echo -e "$NAME Device tree block size:     $DST_SIZE"
 echo -e "$NAME OpenSBI FW_JUMP block size: $FW_JUMP_SIZE"
 echo -e "$NAME Kernel block size:          $KERNEL_SIZE"
 
-read -p "Warning: Doing this will replace all data on this card. Continue? y/n: " -n 1 -r
+read -p $'\e[1;33mWarning:\e[0m Doing this will replace all data on this card. Continue? y/n: ' -n 1 -r
 echo
 if [[ $REPLY =~ ^[Yy]$ ]] ; then
     DEVBASENAME=$(basename $SDCARD)

From 8a62a4513736efc26f912c8b76d333631e883aaf Mon Sep 17 00:00:00 2001
From: Jacob Pease <jacobpease@protonmail.com>
Date: Fri, 25 Aug 2023 17:44:06 -0500
Subject: [PATCH 04/32] Set default baud rate of serial output to 115200 for
 the VCU108.

---
 linux/devicetree/wally-vcu108.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/linux/devicetree/wally-vcu108.dts b/linux/devicetree/wally-vcu108.dts
index add2920bd..8c9182c6c 100644
--- a/linux/devicetree/wally-vcu108.dts
+++ b/linux/devicetree/wally-vcu108.dts
@@ -9,7 +9,7 @@
 	chosen {
 		linux,initrd-end = <0x85c43a00>;
 		linux,initrd-start = <0x84200000>;
-		bootargs = "root=/dev/vda ro";
+		bootargs = "console=ttyS0,115200 root=/dev/vda ro";
 		stdout-path = "/soc/uart@10000000";
 	};
 

From 12c3c98824db1b0c5f72d89ca72c048534702720 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 30 Aug 2023 11:29:44 -0500
Subject: [PATCH 05/32] Extended the CBOM test to cover a 4 way set associative
 cache with 4KiB ways.

---
 .../references/WALLY-cbom-01.reference_output |   8 +
 .../rv64i_m/privilege/src/WALLY-cbom-01.S     | 162 +++++++++++++++++-
 2 files changed, 168 insertions(+), 2 deletions(-)

diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-cbom-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-cbom-01.reference_output
index 9dd00bf9b..8d394ca19 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-cbom-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-cbom-01.reference_output
@@ -436,6 +436,14 @@ ffffffff
 ffffffff
 ffffffff
 ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
+ffffffff
 0bad0bad # controls
 0bad0bad  
 0bad0bad
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S
index 4a45ec676..edad0406a 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S
@@ -125,6 +125,164 @@ CBOMTest_inval_step4_all:
         sd a0, 0(s0)    # should be -1
         addi s0, s0, 8
 
+        ################################################################################
+        # INVALIDATE  all ways D$
+        ################################################################################
+
+        # theory of operation
+        # 1. Read several cachelines of data from memory into the d cache and copy to a second region of memory
+        # 2. Then verify the second region has the same data
+        # 3. Invalidate the second region
+        # 4. Verify the second region has the original invalid data
+        # DON'T batch each step.  We want to see the transition between cachelines. The current should be invalidated
+        # but the next should have the copied data.
+	
+        # step 0 copy deadbeef to remote regions spaced 4KiB apart
+CBOMTest_way_inval_4096_step0: 
+        la a0, DeadBeafData1
+        la a1, Destination1+4096
+        li a2, 8
+        jal ra, memcpy8
+CBOMTest_way_inval_8192_step0: 
+        la a0, DeadBeafData1
+        la a1, Destination1+8192
+        li a2, 8
+        jal ra, memcpy8
+CBOMTest_way_inval_12288_step0: 
+        la a0, DeadBeafData1
+        la a1, Destination1+12288
+        li a2, 8
+        jal ra, memcpy8
+CBOMTest_way_inval_16384_step0:       
+        la a0, DeadBeafData1
+        la a1, Destination1+16384
+        li a2, 8
+        jal ra, memcpy8
+        # one of the following will force an eviction of each of the previous
+CBOMTest_way_inval_20480_step0:       # this one should force eviction of _4096
+        la a0, DeadBeafData1
+        la a1, Destination1+20480
+        li a2, 8
+        jal ra, memcpy8
+CBOMTest_way_inval_24576_step0:       # this one should force eviction of _4096
+        la a0, DeadBeafData1
+        la a1, Destination1+24576
+        li a2, 8
+        jal ra, memcpy8
+CBOMTest_way_inval_28672_step0:       # this one should force eviction of _4096
+        la a0, DeadBeafData1
+        la a1, Destination1+28672
+        li a2, 8
+        jal ra, memcpy8
+CBOMTest_way_inval_32768_step0:       # this one should force eviction of _4096
+        la a0, DeadBeafData1
+        la a1, Destination1+32768
+        li a2, 8
+        jal ra, memcpy8
+        
+        # step 1
+CBOMTest_way_inval_4096_step1: 
+        la a0, SourceData
+        la a1, Destination1+4096
+        li a2, 8
+        jal ra, memcpy8
+
+CBOMTest_way_inval_8192_step1: 
+        la a0, SourceData
+        la a1, Destination1+8192
+        li a2, 8
+        jal ra, memcpy8
+
+CBOMTest_way_inval_12288_step1: 
+        la a0, SourceData
+        la a1, Destination1+12288
+        li a2, 8
+        jal ra, memcpy8
+        
+CBOMTest_way_inval_16384_step1: 
+        la a0, SourceData
+        la a1, Destination1+16384
+        li a2, 8
+        jal ra, memcpy8
+
+        # don't want to ca      use a write back for the previous writes since we want to invalidate them
+	
+        # step 2
+CBOMTest_way_inval_4096_step2: 
+        la a0, SourceData
+        la a1, Destination1+4096
+        li a2, 8
+        jal ra, memcmp8
+        sd a0, 0(s0)     # should be -1
+        addi s0, s0, 8
+	
+CBOMTest_way_inval_8192_step2: 
+        la a0, SourceData
+        la a1, Destination1+8192
+        li a2, 8
+        jal ra, memcmp8
+        sd a0, 0(s0)     # should be -1
+        addi s0, s0, 8
+
+CBOMTest_way_inval_12288_step2: 
+        la a0, SourceData
+        la a1, Destination1+12288
+        li a2, 8
+        jal ra, memcmp8
+        sd a0, 0(s0)     # should be -1
+        addi s0, s0, 8
+
+CBOMTest_way_inval_16384_step2: 
+        la a0, SourceData
+        la a1, Destination1+16384
+        li a2, 8
+        jal ra, memcmp8
+        sd a0, 0(s0)     # should be -1
+        addi s0, s0, 8
+
+CBOMTest_way_inval_step3_all_again: 
+        la a1, Destination1+4096
+        la a2, Destination1+8192
+        la a3, Destination1+12288
+        la a4, Destination1+16384
+        cbo.inval (a1)
+        cbo.inval (a2)          
+        cbo.inval (a3)
+        cbo.inval (a4)          
+        
+        # step 4 All should be invalid
+CBOMTest_way_inval_4096_step4_all: 
+        la a0, DeadBeafData1
+        la a1, Destination1+4096
+        li a2, 8
+        jal ra, memcmp8
+        sd a0, 0(s0)    # should be -1
+        addi s0, s0, 8
+
+CBOMTest_way_inval_8192_step4_all: 
+        la a0, DeadBeafData1
+        la a1, Destination1+8192
+        li a2, 8
+        jal ra, memcmp8
+        sd a0, 0(s0)    # should be -1
+        addi s0, s0, 8
+
+CBOMTest_way_inval_12288_step4_all: 
+        la a0, DeadBeafData1
+        la a1, Destination1+12288
+        li a2, 8
+        jal ra, memcmp8
+        sd a0, 0(s0)    # should be -1
+        addi s0, s0, 8
+	
+CBOMTest_way_inval_16384_step4_all: 
+        la a0, DeadBeafData1
+        la a1, Destination1+16384
+        li a2, 8
+        jal ra, memcmp8
+        sd a0, 0(s0)    # should be -1
+        addi s0, s0, 8
+	
         ################################################################################
         # Clean D$
         ################################################################################
@@ -151,7 +309,7 @@ CBOMTest_clean_step1:
 
         # step 2
 CBOMTest_clean_step2:
-         la a0, SourceData
+        la a0, SourceData
         la a1, Destination2
         li a2, 64
         jal ra, memcmp8
@@ -466,7 +624,7 @@ Destination2:
 Destination3:
         .fill 128, 4, 0xdeadbeef
 signature:
-        .fill 32, 4, 0x0bad0bad
+        .fill 40, 4, 0x0bad0bad
 	
 RVMODEL_DATA_END
 

From eb07e8917eb952394eca5dcf40bcb9086c2f10d3 Mon Sep 17 00:00:00 2001
From: Jacob Pease <jacobpease@protonmail.com>
Date: Thu, 31 Aug 2023 23:58:10 -0500
Subject: [PATCH 06/32] Linux Makefile can now dynamically find binaries for
 object dumps.

---
 linux/Makefile | 32 ++++++++++++++++++++++++--------
 1 file changed, 24 insertions(+), 8 deletions(-)

diff --git a/linux/Makefile b/linux/Makefile
index abbf4a51a..95a849fcf 100644
--- a/linux/Makefile
+++ b/linux/Makefile
@@ -5,6 +5,7 @@ WALLY := $(shell dirname $(shell pwd))
 WALLYLINUX := $(shell pwd)
 DIS := ${IMAGES}/disassembly
 BRPACKAGES := $(WALLYLINUX)/buildroot-packages
+BR2023 := $(WALLYLINUX)/buildroot-config-src/buildroot-2023.05.1
 
 # Buildroot Config Stuff
 WALLYBOARDSRC := $(WALLYLINUX)/buildroot-config-src/wally
@@ -26,6 +27,14 @@ BINARIES := fw_jump.elf vmlinux busybox
 OBJDUMPS := $(foreach name, $(BINARIES), $(basename $(name) .elf))
 OBJDUMPS := $(foreach name, $(OBJDUMPS), $(DIS)/$(name).objdump)
 
+# LINUXDIR := $(shell ls $(BUILDROOT)/output/build | grep -e '^linux-[0-9]\+\.[0-9]\+\.[0-9]\+$$' )
+# LINUXDIR := $(BUILDROOT)/output/build/$(LINUXDIR)
+# BUSYBOXDIR := $(shell ls $(BUILDROOT)/output/build | grep -e '^linux-[0-9]\+\.[0-9]\+\.[0-9]\+$$' )
+# BUSYBOXDIR := $(BUILDROOT)/output/build/$(BUSYBOXDIR)
+
+LINUXDIR := $(shell find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/linux-[0-9]+\.[0-9]+\.[0-9]+$$")
+BUSYBOXDIR := $(shell find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/busybox-[0-9]+\.[0-9]+\.[0-9]+$$")
+
 .PHONY: all generate disassemble install clean cleanDTB cleanDriver test
 
 # Generate all device trees -------------------------------------------
@@ -41,7 +50,8 @@ all:
 
 # Temp rule for debugging
 test:
-	@echo $(OBJDUMPS)
+	@echo $(LINUXDIR)
+	@echo $(BUSYBOXDIR)
 
 generate: $(DTB) $(IMAGES)
 
@@ -68,10 +78,10 @@ $(DIS)/%.objdump: $(IMAGES)/%.elf
 $(DIS)/%.objdump: $(IMAGES)/%
 	riscv64-unknown-elf-objdump -S $< >> $@
 
-$(IMAGES)/vmlinux: $(BUILDROOT)/output/build/linux-5.10.7/vmlinux
+$(IMAGES)/vmlinux: $(LINUXDIR)/vmlinux
 	cp $< $@
 
-$(IMAGES)/busybox: $(BUILDROOT)/output/build/busybox-1.33.0/busybox
+$(IMAGES)/busybox: $(BUSYBOXDIR)/busybox
 	cp $< $@
 
 # Generating new Buildroot directories --------------------------------
@@ -87,10 +97,16 @@ install: $(BUILDROOT)/package/fpga-axi-sdc $(WALLYBOARD) $(DRIVER)
 # $(WALLYBOARD)/linux.config: $(BRPACKAGES)/linux.config $(WALLYBOARD)
 # 	cp $(BRPACKAGES)/linux.config $@
 
+# $(WALLYBOARD): $(BUILDROOT)
+# 	cp -r $(WALLYBOARDSRC) $(BUILDROOT)/board
+# 	cp $(BRPACKAGES)/wally.config $(WALLYBOARD)/main.config
+# 	cp $(BRPACKAGES)/linux.config $(WALLYBOARD)/linux.config
+
+# CONFIG DEPENDENCIES 2023.05.1 ---------------------------------------
 $(WALLYBOARD): $(BUILDROOT)
 	cp -r $(WALLYBOARDSRC) $(BUILDROOT)/board
-	cp $(BRPACKAGES)/wally.config $(WALLYBOARD)/main.config
-	cp $(BRPACKAGES)/linux.config $(WALLYBOARD)/linux.config
+	cp $(BR2023)/main.config $(WALLYBOARD)/main.config
+	cp $(BR2023)/linux.config $(WALLYBOARD)/linux.config
 
 # Buildroot Package ---------------------------------------------------
 $(BUILDROOT)/package/fpga-axi-sdc: $(BUILDROOT) $(PATCHFILE) $(BRPACKAGES)/fpga-axi-sdc
@@ -103,14 +119,14 @@ $(PATCHFILE):
 
 $(BUILDROOT):
 	git clone https://github.com/buildroot/buildroot.git $@
-	# cd $@; git checkout 2023.05.x
-	cd $@; git checkout 2021.05
+	cd $@; git checkout 2023.05.x
+	#cd $@; git checkout 2021.05
 
 $(DRIVER):
 	@ if [ -d "$(WALLY)/addins/vivado-risc-v" ] ; then git submodule update --init $(WALLY)/addins/vivado-risc-v; fi
 	cp ../addins/vivado-risc-v/patches/fpga-axi-sdc.c $@
 	# For 2021.05
-	sed -i "s|card_hw_reset|hw_reset|1" $@
+	#sed -i "s|card_hw_reset|hw_reset|1" $@
 
 # ---------------------------------------------------------------------
 

From de54b5c4d8e98b4113e4903fd3821511f1f5f971 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Tue, 5 Sep 2023 11:11:56 -0500
Subject: [PATCH 07/32] Updated wavefile

---
 sim/wave.do | 649 +++++++++++++++++++++++++++-------------------------
 1 file changed, 332 insertions(+), 317 deletions(-)

diff --git a/sim/wave.do b/sim/wave.do
index 6fd560251..587582a8e 100644
--- a/sim/wave.do
+++ b/sim/wave.do
@@ -48,11 +48,11 @@ add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpi
 add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
 add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE
 add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM
-add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF
-add wave -noupdate -group PCS /testbench/dut/core/ifu/PCF
-add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD
-add wave -noupdate -group PCS /testbench/dut/core/PCE
-add wave -noupdate -group PCS /testbench/dut/core/PCM
+add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCNextF
+add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCF
+add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCD
+add wave -noupdate -expand -group PCS /testbench/dut/core/PCE
+add wave -noupdate -expand -group PCS /testbench/dut/core/PCM
 add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD
 add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD
 add wave -noupdate -group {Decode Stage} /testbench/InstrDName
@@ -84,6 +84,7 @@ add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIP_REGW
 add wave -noupdate -group CSRs {/testbench/dut/core/priv/priv/csr/MSTATUS_REGW[21]}
 add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MSTATUS_REGW
 add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MTVEC_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MENVCFG_REGW
 add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPADDR_ARRAY_REGW
 add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_REGW
 add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW
@@ -91,6 +92,7 @@ add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW
 add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW
 add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW
 add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SENVCFG_REGW
 add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FRM_REGW
 add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FFLAGS_REGW
 add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS
@@ -178,216 +180,224 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM
-add wave -noupdate -expand -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/FWriteDataM
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IgnoreRequestTLB
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW
-add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/ebu/ebu/HCLK
-add wave -noupdate -expand -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState
-add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY
-add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/BusStall
-add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS
-add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer
-add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA
-add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUHWDATA
-add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall
-add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW
-add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck
-add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
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-add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
-add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
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-add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
-add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CacheSet
-add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
-add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
-add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate
-add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate
-add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded
-add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
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-add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag
-add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn
-add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn
-add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag
-add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM[62]}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ClearValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ClearValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ClearValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/TagWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/TagWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/TagWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/TagWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextSet
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusRW
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
-add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
-add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
-add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
-add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
-add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
-add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
-add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
-add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
-add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
-add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
-add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
-add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
-add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
-add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk
-add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/DCacheStallM
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault
+add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
+add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM
+add wave -noupdate -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/FWriteDataM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
+add wave -noupdate -group lsu /testbench/dut/core/lsu/IgnoreRequestTLB
+add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
+add wave -noupdate -group lsu -group bus /testbench/dut/core/ebu/ebu/HCLK
+add wave -noupdate -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/BusStall
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUHWDATA
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOp
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOZeroHit
+add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
+add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
+add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelFlush
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelWriteback
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/TagWay
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/Tag
+add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
+add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
+add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CacheSet
+add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
+add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
+add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
+add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay
+add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate
+add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate
+add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded
+add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
+add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
+add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
+add wave -noupdate -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
+add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag
+add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn
+add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn
+add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag
+add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay
+add wave -noupdate -group lsu -expand -group dcache -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelData}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearValidWay}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM[62]}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelNotHit2}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelNonHit}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelData}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ClearValidWay}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ClearValidWay}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ClearValidWay}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/TagWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/TagWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/TagWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/TagWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextSet
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusRW
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
+add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
+add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
+add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
+add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
+add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
+add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk
+add wave -noupdate -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE
+add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
+add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
+add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF
+add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM
+add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM
+add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/DCacheStallM
+add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF
+add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM
+add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM
+add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM
+add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM
+add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault
 add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr
 add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr
 add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/MExtInt
@@ -454,106 +464,111 @@ add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/du
 add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/core/FlushW
 add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/PCM
 add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM
-add wave -noupdate -group ifu /testbench/dut/core/ifu/InstrRawF
-add wave -noupdate -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF
-add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUStallF
-add wave -noupdate -group ifu -group Spill /testbench/dut/core/ifu/Spill/spill/CurrState
-add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/SpillF
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+add wave -noupdate -expand -group ifu -expand -group icache -group way2 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/CacheTagMem/RAM}
+add wave -noupdate -expand -group ifu -expand -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/ValidBits}
+add wave -noupdate -expand -group ifu -expand -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/dout}
+add wave -noupdate -expand -group ifu -expand -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/dout}
+add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/dout}
+add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/dout}
+add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/RAM}
+add wave -noupdate -expand -group ifu -expand -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/HitWay}
+add wave -noupdate -expand -group ifu -expand -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/SelectedWriteWordEn}
+add wave -noupdate -expand -group ifu -expand -group icache -group way1 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/CacheTagMem/RAM}
+add wave -noupdate -expand -group ifu -expand -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/ValidBits}
+add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/dout}
+add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/dout}
+add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/dout}
+add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/dout}
+add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/RAM}
+add wave -noupdate -expand -group ifu -expand -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/SelectedWriteWordEn}
+add wave -noupdate -expand -group ifu -expand -group icache -group way0 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/CacheTagMem/RAM}
+add wave -noupdate -expand -group ifu -expand -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/ValidBits}
+add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/dout}
+add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/dout}
+add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/dout}
+add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/dout}
+add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM}
+add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
+add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF
+add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/VAdr
+add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
+add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/Matches
+add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/InstrPageFaultF
+add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/TLBFlush
+add wave -noupdate -expand -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Valid}
+add wave -noupdate -expand -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/PageType}
+add wave -noupdate -expand -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key}
+add wave -noupdate -expand -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key0}
+add wave -noupdate -expand -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key1}
+add wave -noupdate -expand -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query0}
+add wave -noupdate -expand -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query1}
+add wave -noupdate -expand -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Valid}
+add wave -noupdate -expand -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageTypeWriteVal}
+add wave -noupdate -expand -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageType}
+add wave -noupdate -expand -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key}
+add wave -noupdate -expand -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key0}
+add wave -noupdate -expand -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1}
+add wave -noupdate -expand -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0}
+add wave -noupdate -expand -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1}
 add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
 add wave -noupdate -group {Performance Counters} -label MINSTRET -radix hexadecimal {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
 add wave -noupdate -group {Performance Counters} -group BP -label Branch -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
@@ -646,7 +661,7 @@ add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/FlushStage
 add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/CacheEn
 add wave -noupdate /testbench/dut/core/ifu/CacheableF
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {172636 ns} 1} {{Cursor 4} {152124 ns} 0} {{Cursor 3} {152766 ns} 1}
+WaveRestoreCursors {{Cursor 4} {172636 ns} 1} {{Cursor 4} {740727 ns} 0} {{Cursor 3} {152766 ns} 1}
 quietly wave cursor active 2
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 194
@@ -662,4 +677,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {152015 ns} {152227 ns}
+WaveRestoreZoom {740593 ns} {740859 ns}

From 11a3fd9314fefb098da2fa693a989731fcc5d8cc Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Tue, 5 Sep 2023 14:07:58 -0500
Subject: [PATCH 08/32] Slight modification to cachefsm.

---
 src/cache/cachefsm.sv | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv
index 099077cf4..cd35697fd 100644
--- a/src/cache/cachefsm.sv
+++ b/src/cache/cachefsm.sv
@@ -171,9 +171,9 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
   assign ClearValid = P.ZICBOM_SUPPORTED & ((CurrState == STATE_READY & CMOp[0] & CacheHit) |
                       (CurrState == STATE_CMO_WRITEBACK & CMOp[2] & CacheBusAck));
   // coverage off -item e 1 -fecexprrow 8
-  assign LRUWriteEn = ((CurrState == STATE_READY & (AnyHit | CMOZeroNoEviction)) |
-                      (P.ZICBOZ_SUPPORTED & CurrState == STATE_WRITEBACK & CMOp[3] & CacheBusAck) | 
-                      (CurrState == STATE_WRITE_LINE)) & ~FlushStage;
+  assign LRUWriteEn = (((CurrState == STATE_READY & (AnyHit | CMOZeroNoEviction)) |
+                       (CurrState == STATE_WRITE_LINE)) & ~FlushStage) |
+                      (P.ZICBOZ_SUPPORTED & CurrState == STATE_WRITEBACK & CMOp[3] & CacheBusAck);
   // exclusion-tag-start: icache flushdirtycontrols
   assign SetDirty = (CurrState == STATE_READY & (AnyUpdateHit | CMOZeroNoEviction)) |         // exclusion-tag: icache SetDirty  
                     (CurrState == STATE_WRITE_LINE & (CacheRW[0])) |

From 95c653e7df0f72493442bcb832b15db289a63419 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Fri, 15 Sep 2023 14:05:26 -0500
Subject: [PATCH 09/32] Fixes the bpred-sim.py to support command line
 parameterization of the branch predictor while using the new
 parameterization.  This is definitely a hack, but I don't see a better way.

---
 config/rv32gc/config.vh |   8 +-
 sim/bpred-sim.py        |  48 +--
 sim/wave.do             | 712 ++++++++++++++++++++--------------------
 3 files changed, 391 insertions(+), 377 deletions(-)

diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh
index 07f005f43..46d3ed22a 100644
--- a/config/rv32gc/config.vh
+++ b/config/rv32gc/config.vh
@@ -141,8 +141,14 @@ localparam PLIC_UART_ID = 32'd10;
 localparam PLIC_SDC_ID = 32'd9;
 
 localparam BPRED_SUPPORTED = 1;
+// this is an annoying hack for the branch predictor parameterization override.
+`ifdef BPRED_OVERRIDE
+localparam BPRED_TYPE = `BPRED_TYPE;
+localparam BPRED_SIZE = `BPRED_SIZE;
+`else
 localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
-localparam BPRED_SIZE = 32'd16;
+localparam BPRED_SIZE = 32'd10;
+`endif
 localparam BPRED_NUM_LHR = 32'd6;
 localparam BTB_SIZE = 32'd10;
 
diff --git a/sim/bpred-sim.py b/sim/bpred-sim.py
index 4f1757cb8..4ec9324a3 100755
--- a/sim/bpred-sim.py
+++ b/sim/bpred-sim.py
@@ -46,33 +46,33 @@ configs = [
     )
 ]
 
-# bpdSize = [6, 8, 10, 12, 14, 16]
-# bpdType = ['twobit', 'gshare', 'global', 'gshare_basic', 'global_basic', 'local_basic']
-# for CurrBPType in bpdType:
-#     for CurrBPSize in bpdSize:
-#         name = CurrBPType+str(CurrBPSize)
-#         configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_TYPE=\"BP_" + CurrBPType.upper() + "\" +define+BPRED_SIZE=" + str(CurrBPSize)
-#         tc = TestCase(
-#             name=name,
-#             variant="rv32gc",
-#             cmd="vsim > {} -c <<!\ndo wally-batch.do  rv32gc configOptions " + name + " embench " + configOptions,
-#             grepstr="")
-#         configs.append(tc)
-
 bpdSize = [6, 8, 10, 12, 14, 16]
-LHRSize = [4, 8, 10]
-bpdType = ['local_repair']
+bpdType = ['twobit', 'gshare', 'global', 'gshare_basic', 'global_basic', 'local_basic']
 for CurrBPType in bpdType:
     for CurrBPSize in bpdSize:
-        for CurrLHRSize in  LHRSize:
-            name = str(CurrLHRSize)+CurrBPType+str(CurrBPSize)
-            configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_TYPE=\"BP_" + CurrBPType.upper() + "\" +define+BPRED_SIZE=" + str(CurrBPSize) + " +define+BPRED_NUM_LHR=" + str(CurrLHRSize) + " "
-            tc = TestCase(
-                name=name,
-                variant="rv32gc",
-                cmd="vsim > {} -c <<!\ndo wally-batch.do  rv32gc configOptions " + name + " embench " + configOptions,
-                grepstr="")
-            configs.append(tc)
+        name = CurrBPType+str(CurrBPSize)
+        configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_OVERRIDE +define+BPRED_TYPE=" + str(bpdType.index(CurrBPType)) + "+define+BPRED_SIZE=" + str(CurrBPSize)
+        tc = TestCase(
+            name=name,
+            variant="rv32gc",
+            cmd="vsim > {} -c <<!\ndo wally-batch.do  rv32gc configOptions " + name + " embench " + configOptions,
+            grepstr="")
+        configs.append(tc)
+
+# bpdSize = [6, 8, 10, 12, 14, 16]
+# LHRSize = [4, 8, 10]
+# bpdType = ['local_repair']
+# for CurrBPType in bpdType:
+#     for CurrBPSize in bpdSize:
+#         for CurrLHRSize in  LHRSize:
+#             name = str(CurrLHRSize)+CurrBPType+str(CurrBPSize)
+#             configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_TYPE=\"BP_" + CurrBPType.upper() + "\" +define+BPRED_SIZE=" + str(CurrBPSize) + " +define+BPRED_NUM_LHR=" + str(CurrLHRSize) + " "
+#             tc = TestCase(
+#                 name=name,
+#                 variant="rv32gc",
+#                 cmd="vsim > {} -c <<!\ndo wally-batch.do  rv32gc configOptions " + name + " embench " + configOptions,
+#                 grepstr="")
+#             configs.append(tc)
 
 import os
 from multiprocessing import Pool, TimeoutError
diff --git a/sim/wave.do b/sim/wave.do
index 62234f06b..b55a44d4c 100644
--- a/sim/wave.do
+++ b/sim/wave.do
@@ -48,11 +48,11 @@ add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpi
 add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
 add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE
 add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM
-add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCNextF
-add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCF
-add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCD
-add wave -noupdate -expand -group PCS /testbench/dut/core/PCE
-add wave -noupdate -expand -group PCS /testbench/dut/core/PCM
+add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF
+add wave -noupdate -group PCS /testbench/dut/core/ifu/PCF
+add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD
+add wave -noupdate -group PCS /testbench/dut/core/PCE
+add wave -noupdate -group PCS /testbench/dut/core/PCM
 add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD
 add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD
 add wave -noupdate -group {Decode Stage} /testbench/InstrDName
@@ -68,17 +68,255 @@ add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValid
 add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcAE
 add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcBE
 add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ALUResultE
+add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ResultW
 add wave -noupdate -expand -group {Memory Stage} /testbench/FunctionName/FunctionName/FunctionName
 add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrValidM
 add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
 add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
 add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
 add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/WriteDataM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/WriteDataM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
+add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM
+add wave -noupdate -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/FWriteDataM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
+add wave -noupdate -group lsu /testbench/dut/core/lsu/IgnoreRequestTLB
+add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
+add wave -noupdate -group lsu -group bus /testbench/dut/core/ebu/ebu/HCLK
+add wave -noupdate -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/BusStall
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUHWDATA
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOp
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOZeroHit
+add wave -noupdate -group lsu -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrE
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
+add wave -noupdate -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
+add wave -noupdate -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelFlush
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelWriteback
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/TagWay
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/Tag
+add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
+add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
+add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CacheSet
+add wave -noupdate -group lsu -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
+add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
+add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
+add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay
+add wave -noupdate -group lsu -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate
+add wave -noupdate -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate
+add wave -noupdate -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded
+add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
+add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
+add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
+add wave -noupdate -group lsu -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
+add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag
+add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn
+add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn
+add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag
+add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay
+add wave -noupdate -group lsu -group dcache -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelData}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearValidWay}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM[62]}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelNotHit2}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelNonHit}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelData}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ClearValidWay}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ClearValidWay}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ClearValidWay}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/TagWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/TagWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/TagWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/TagWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
+add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextSet
+add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusRW
+add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
+add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
+add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
+add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
+add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
+add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
+add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
+add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
+add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk
+add wave -noupdate -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE
+add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
+add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
+add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF
+add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM
+add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM
+add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/DCacheStallM
+add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF
+add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM
+add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM
+add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM
+add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM
+add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault
 add wave -noupdate -group {WriteBack stage} /testbench/InstrW
 add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
-add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ResultW
+add wave -noupdate -group Bpred -expand -group {branch update selection inputs} -divider {class check}
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
+add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F
+add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a3
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd1
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd2
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/we3
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/wd3
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ReadDataW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/CSRReadValW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultSrcW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MISA_REGW
 add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MCAUSE_REGW
 add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW
 add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW
@@ -102,25 +340,6 @@ add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SENVCFG_REGW
 add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FRM_REGW
 add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FFLAGS_REGW
 add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} -divider {class check}
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
-add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
-add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
-add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE
-add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
-add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F
-add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf
-add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1
-add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2
-add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a3
-add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd1
-add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd2
-add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/we3
-add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/wd3
-add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ReadDataW
-add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/CSRReadValW
-add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultSrcW
-add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultW
 add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/A
 add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/B
 add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/ALUResult
@@ -186,224 +405,6 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK
-add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
-add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM
-add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
-add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM
-add wave -noupdate -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM
-add wave -noupdate -group lsu /testbench/dut/core/lsu/FWriteDataM
-add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
-add wave -noupdate -group lsu /testbench/dut/core/lsu/IgnoreRequestTLB
-add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
-add wave -noupdate -group lsu -group bus /testbench/dut/core/ebu/ebu/HCLK
-add wave -noupdate -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState
-add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY
-add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/BusStall
-add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS
-add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer
-add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA
-add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUHWDATA
-add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall
-add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW
-add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck
-add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOp
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOZeroHit
-add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
-add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
-add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelFlush
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelWriteback
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/TagWay
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/Tag
-add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
-add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
-add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CacheSet
-add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
-add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
-add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
-add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay
-add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate
-add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate
-add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded
-add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
-add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
-add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
-add wave -noupdate -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
-add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag
-add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn
-add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn
-add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag
-add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay
-add wave -noupdate -group lsu -expand -group dcache -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelData}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearValidWay}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM[62]}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelNotHit2}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelNonHit}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelData}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ClearValidWay}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ClearValidWay}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ClearValidWay}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/TagWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/TagWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/TagWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/TagWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
-add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextSet
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusRW
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
-add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
-add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
-add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
-add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
-add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
-add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
-add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
-add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
-add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
-add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
-add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
-add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
-add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
-add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
-add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
-add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
-add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
-add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
-add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
-add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
-add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
-add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
-add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
-add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
-add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
-add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
-add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
-add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW
-add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall
-add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk
-add wave -noupdate -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState
-add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr
-add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE
-add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType
-add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType
-add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE
-add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
-add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
-add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF
-add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM
-add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM
-add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/DCacheStallM
-add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF
-add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM
-add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM
-add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM
-add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM
-add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault
 add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr
 add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr
 add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/MExtInt
@@ -470,111 +471,111 @@ add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/du
 add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/core/FlushW
 add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/PCM
 add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM
-add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/InstrRawF
-add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF
-add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUStallF
-add wave -noupdate -expand -group ifu -group Spill /testbench/dut/core/ifu/Spill/spill/CurrState
-add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/SpillF
-add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallF
-add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissF
-add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/TakeSpillF
-add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE
-add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST
-add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS
-add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE
-add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR
-add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush
-add wave -noupdate -expand -group ifu -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState
-add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HRDATA
-add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall
-add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/FlushStage
-add wave -noupdate -expand -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState
-add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF
-add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr
-add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF
-add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF
-add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss
-add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/CacheRW
-add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall
-add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/CacheAccess
-add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay
-add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF
-add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr
-add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck
-add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay
-add wave -noupdate -expand -group ifu -expand -group icache -color Gold -radix unsigned /testbench/dut/core/ifu/bus/icache/icache/CacheSet
-add wave -noupdate -expand -group ifu -expand -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/FlushStage
-add wave -noupdate -expand -group ifu -expand -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUWriteEn
-add wave -noupdate -expand -group ifu -expand -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUUpdate
-add wave -noupdate -expand -group ifu -expand -group icache -expand -group lru {/testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory[50]}
-add wave -noupdate -expand -group ifu -expand -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory
-add wave -noupdate -expand -group ifu -expand -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/SelectedWriteWordEn}
-add wave -noupdate -expand -group ifu -expand -group icache -group way3 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/CacheTagMem/RAM}
-add wave -noupdate -expand -group ifu -expand -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/ValidBits}
-add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/dout}
-add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/dout}
-add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/dout}
-add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/dout}
-add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group ifu -expand -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/SelectedWriteWordEn}
-add wave -noupdate -expand -group ifu -expand -group icache -group way2 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/CacheTagMem/RAM}
-add wave -noupdate -expand -group ifu -expand -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/ValidBits}
-add wave -noupdate -expand -group ifu -expand -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/dout}
-add wave -noupdate -expand -group ifu -expand -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/dout}
-add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/dout}
-add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/dout}
-add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group ifu -expand -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/HitWay}
-add wave -noupdate -expand -group ifu -expand -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/SelectedWriteWordEn}
-add wave -noupdate -expand -group ifu -expand -group icache -group way1 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/CacheTagMem/RAM}
-add wave -noupdate -expand -group ifu -expand -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/ValidBits}
-add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/dout}
-add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/dout}
-add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/dout}
-add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/dout}
-add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group ifu -expand -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/SelectedWriteWordEn}
-add wave -noupdate -expand -group ifu -expand -group icache -group way0 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/CacheTagMem/RAM}
-add wave -noupdate -expand -group ifu -expand -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/ValidBits}
-add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/dout}
-add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/dout}
-add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/dout}
-add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/dout}
-add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
-add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF
-add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/VAdr
-add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
-add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/Matches
-add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/InstrPageFaultF
-add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/TLBFlush
-add wave -noupdate -expand -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Valid}
-add wave -noupdate -expand -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/PageType}
-add wave -noupdate -expand -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key}
-add wave -noupdate -expand -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key0}
-add wave -noupdate -expand -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key1}
-add wave -noupdate -expand -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query0}
-add wave -noupdate -expand -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query1}
-add wave -noupdate -expand -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Valid}
-add wave -noupdate -expand -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageTypeWriteVal}
-add wave -noupdate -expand -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageType}
-add wave -noupdate -expand -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key}
-add wave -noupdate -expand -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key0}
-add wave -noupdate -expand -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1}
-add wave -noupdate -expand -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0}
-add wave -noupdate -expand -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1}
+add wave -noupdate -group ifu /testbench/dut/core/ifu/InstrRawF
+add wave -noupdate -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF
+add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUStallF
+add wave -noupdate -group ifu -group Spill /testbench/dut/core/ifu/Spill/spill/CurrState
+add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/SpillF
+add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallF
+add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissF
+add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/TakeSpillF
+add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE
+add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST
+add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS
+add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE
+add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR
+add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush
+add wave -noupdate -group ifu -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState
+add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HRDATA
+add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall
+add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/FlushStage
+add wave -noupdate -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState
+add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF
+add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr
+add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF
+add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF
+add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss
+add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/CacheRW
+add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall
+add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/CacheAccess
+add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay
+add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF
+add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr
+add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck
+add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay
+add wave -noupdate -group ifu -expand -group icache -color Gold -radix unsigned /testbench/dut/core/ifu/bus/icache/icache/CacheSet
+add wave -noupdate -group ifu -expand -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/FlushStage
+add wave -noupdate -group ifu -expand -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUWriteEn
+add wave -noupdate -group ifu -expand -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUUpdate
+add wave -noupdate -group ifu -expand -group icache -expand -group lru {/testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory[50]}
+add wave -noupdate -group ifu -expand -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory
+add wave -noupdate -group ifu -expand -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/SelectedWriteWordEn}
+add wave -noupdate -group ifu -expand -group icache -group way3 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/CacheTagMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/ValidBits}
+add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/SelectedWriteWordEn}
+add wave -noupdate -group ifu -expand -group icache -group way2 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/CacheTagMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/ValidBits}
+add wave -noupdate -group ifu -expand -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/HitWay}
+add wave -noupdate -group ifu -expand -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/SelectedWriteWordEn}
+add wave -noupdate -group ifu -expand -group icache -group way1 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/CacheTagMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/ValidBits}
+add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/SelectedWriteWordEn}
+add wave -noupdate -group ifu -expand -group icache -group way0 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/CacheTagMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/ValidBits}
+add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
+add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF
+add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/VAdr
+add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
+add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/Matches
+add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/InstrPageFaultF
+add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/TLBFlush
+add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Valid}
+add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/PageType}
+add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key}
+add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key0}
+add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key1}
+add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query0}
+add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query1}
+add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Valid}
+add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageTypeWriteVal}
+add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageType}
+add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key}
+add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key0}
+add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1}
+add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0}
+add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1}
 add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
 add wave -noupdate -group {Performance Counters} -label MINSTRET -radix hexadecimal {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
 add wave -noupdate -group {Performance Counters} -group BP -label Branch -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
@@ -666,8 +667,15 @@ add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/LRUWriteEn
 add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/FlushStage
 add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/CacheEn
 add wave -noupdate /testbench/dut/core/ifu/CacheableF
+add wave -noupdate /testbench/loggers/BeginSample
+add wave -noupdate /testbench/loggers/StartSample
+add wave -noupdate /testbench/loggers/reset
+add wave -noupdate -radix ascii /testbench/loggers/TEST
+add wave -noupdate /testbench/dut/core/fpu/fpu/fctrl/IllegalFPUInstrD
+add wave -noupdate /testbench/dut/core/fpu/fpu/fctrl/STATUS_FS
+add wave -noupdate /testbench/dut/core/priv/priv/csr/csrsr/STATUS_FS_INT
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {172636 ns} 1} {{Cursor 4} {740727 ns} 0} {{Cursor 3} {152766 ns} 1}
+WaveRestoreCursors {{Cursor 4} {172636 ns} 1} {{Cursor 4} {578 ns} 0} {{Cursor 3} {152766 ns} 1}
 quietly wave cursor active 2
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 194
@@ -683,4 +691,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {740593 ns} {740859 ns}
+WaveRestoreZoom {526 ns} {696 ns}

From 60ddbe31f8b7fafea74a294302dd2b052548b02a Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 18 Sep 2023 16:59:20 -0500
Subject: [PATCH 10/32] Updated the branch predictor simulator's parseHPMC.py
 results. In a future commit I will update the branch predictor simulator with
 the fix for the gshare and then update the commit pointing their repo.

---
 bin/SeparateBranch.sh |   5 +-
 bin/parseHPMC.py      |  15 +++--
 sim/wave.do           | 126 +++++++++++++++++++++---------------------
 3 files changed, 78 insertions(+), 68 deletions(-)

diff --git a/bin/SeparateBranch.sh b/bin/SeparateBranch.sh
index c5ebb5de0..eb4ee4494 100755
--- a/bin/SeparateBranch.sh
+++ b/bin/SeparateBranch.sh
@@ -6,7 +6,10 @@
 ## Modified: 
 ##
 ## Purpose: Converts a single branch.log containing multiple benchmark branch outcomes into
-##          separate files, one for each program.x4
+##          separate files, one for each program.
+## Input:   branch log file generated by modelsim
+## output:  outputs to directory branch a collection of files with the branch outcomes
+##          separated by benchmark application.  Example names are aha-mot64bd_sizeopt_speed_branch.log
 ##
 ## A component of the CORE-V-WALLY configurable RISC-V project.
 ##
diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py
index 9e08f2c7a..8bf98ef5a 100755
--- a/bin/parseHPMC.py
+++ b/bin/parseHPMC.py
@@ -36,10 +36,15 @@ import re
 #                           [14.5859173702079, 12.3634674403619, 10.5806018170154, 8.38831266973592, 6.37097544620762, 3.52638362703015])
 #}
 
-RefData = [('twobitCModel6', 11.0501534891674), ('twobitCModel8', 8.51829052266352), ('twobitCModel10', 7.56775222626483),
-           ('twobitCModel12', 6.31366834586515), ('twobitCModel14', 5.72699936834177), ('twobitCModel16', 5.72699936834177),
-           ('gshareCModel6', 14.5731555979574), ('gshareCModel8', 12.3155658100497), ('gshareCModel10', 10.4589596630561),
-           ('gshareCModel12', 8.25796055444401), ('gshareCModel14', 6.23093702707613), ('gshareCModel16', 3.34001125650374)]
+#RefData = [('twobitCModel6', 11.0501534891674), ('twobitCModel8', 8.51829052266352), ('twobitCModel10', 7.56775222626483),
+#           ('twobitCModel12', 6.31366834586515), ('twobitCModel14', 5.72699936834177), ('twobitCModel16', 5.72699936834177),
+#           ('gshareCModel6', 14.5731555979574), ('gshareCModel8', 12.3155658100497), ('gshareCModel10', 10.4589596630561),
+#           ('gshareCModel12', 8.25796055444401), ('gshareCModel14', 6.23093702707613), ('gshareCModel16', 3.34001125650374)]
+
+RefData = [('twobitCModel6', 9.65280765420711), ('twobitCModel8', 8.75120245829945), ('twobitCModel10', 8.1318382397263),
+           ('twobitCModel12', 7.53026646633342), ('twobitCModel14', 6.07679338544009), ('twobitCModel16', 6.07679338544009),
+           ('gshareCModel6', 10.6602835418646), ('gshareCModel8', 8.38384710559667), ('gshareCModel10', 6.36847432155534),
+           ('gshareCModel12', 3.91108491151983), ('gshareCModel14', 2.83926519215395), ('gshareCModel16', .60213659066941)]
 
 
 def ComputeCPI(benchmark):
@@ -255,7 +260,7 @@ if(sys.argv[1] == '-b'):
     else:
         combined = benchmarkDict['All_']
         # merge the reference data into rtl data
-        combined.extend(RefData)
+        # combined.extend(RefData)
         (name, value) = FormatToPlot(combined)
         lst = []
         dct = {}
diff --git a/sim/wave.do b/sim/wave.do
index b55a44d4c..62ba0108f 100644
--- a/sim/wave.do
+++ b/sim/wave.do
@@ -11,38 +11,38 @@ add wave -noupdate /testbench/FunctionName/FunctionName/FunctionAddr
 add wave -noupdate /testbench/FunctionName/FunctionName/ProgramAddrIndex
 add wave -noupdate /testbench/FunctionName/FunctionName/FunctionName
 add wave -noupdate /testbench/FunctionName/FunctionName/ProgramAddrMapLineCount
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
-add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/BPWrongE
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/MDUStallD
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM
-add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD
-add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE
-add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM
-add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW
-add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallF
-add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallD
-add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallE
-add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallM
-add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallW
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
+add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPWrongE
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/MDUStallD
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE
+add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM
+add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM
+add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD
+add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE
+add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM
+add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW
+add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallF
+add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallD
+add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallE
+add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallM
+add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallW
 add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
 add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF
 add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
@@ -297,9 +297,11 @@ add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/d
 add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault
 add wave -noupdate -group {WriteBack stage} /testbench/InstrW
 add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} -divider {class check}
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
-add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
+add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM
+add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} -label PHT /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/mem
+add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} -divider {class check}
+add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
+add wave -noupdate -expand -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
 add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
 add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE
 add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
@@ -576,31 +578,31 @@ add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/c
 add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1}
 add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0}
 add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1}
-add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
-add wave -noupdate -group {Performance Counters} -label MINSTRET -radix hexadecimal {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
-add wave -noupdate -group {Performance Counters} -group BP -label Branch -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
-add wave -noupdate -group {Performance Counters} -group BP -label {BP Dir Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
-add wave -noupdate -group {Performance Counters} -group BP -label {Jump (Not Return)} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]}
-add wave -noupdate -group {Performance Counters} -group BP -label Return -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]}
-add wave -noupdate -group {Performance Counters} -group BP -label {BP Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]}
-add wave -noupdate -group {Performance Counters} -group BP -label {BTA Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]}
-add wave -noupdate -group {Performance Counters} -group BP -label {RAS Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]}
-add wave -noupdate -group {Performance Counters} -group BP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]}
-add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {I Cache Access} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[16]}
-add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {I Cache Miss} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[17]}
-add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {I Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[18]}
-add wave -noupdate -group {Performance Counters} -group DCACHE -label {Load Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
-add wave -noupdate -group {Performance Counters} -group DCACHE -label {Store Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
-add wave -noupdate -group {Performance Counters} -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
-add wave -noupdate -group {Performance Counters} -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]}
-add wave -noupdate -group {Performance Counters} -group DCACHE -label {D Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]}
-add wave -noupdate -group {Performance Counters} -group Privileged -label {CSR Write} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[19]}
-add wave -noupdate -group {Performance Counters} -group Privileged -label Fence.I {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[20]}
-add wave -noupdate -group {Performance Counters} -group Privileged -label sfence.VMA {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[21]}
-add wave -noupdate -group {Performance Counters} -group Privileged -label Interrupt {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[22]}
-add wave -noupdate -group {Performance Counters} -group Privileged -label Exception {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[23]}
-add wave -noupdate -group {Performance Counters} -label {FDiv or IDiv Cycles} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[24]}
-add wave -noupdate -group {Performance Counters} /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW
+add wave -noupdate -expand -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
+add wave -noupdate -expand -group {Performance Counters} -label MINSTRET -radix hexadecimal {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label Branch -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BP Dir Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {Jump (Not Return)} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label Return -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BP Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BTA Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {RAS Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]}
+add wave -noupdate -expand -group {Performance Counters} -group ICACHE -label {I Cache Access} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[16]}
+add wave -noupdate -expand -group {Performance Counters} -group ICACHE -label {I Cache Miss} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[17]}
+add wave -noupdate -expand -group {Performance Counters} -group ICACHE -label {I Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[18]}
+add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {Load Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
+add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {Store Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
+add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
+add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]}
+add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {D Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]}
+add wave -noupdate -expand -group {Performance Counters} -group Privileged -label {CSR Write} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[19]}
+add wave -noupdate -expand -group {Performance Counters} -group Privileged -label Fence.I {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[20]}
+add wave -noupdate -expand -group {Performance Counters} -group Privileged -label sfence.VMA {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[21]}
+add wave -noupdate -expand -group {Performance Counters} -group Privileged -label Interrupt {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[22]}
+add wave -noupdate -expand -group {Performance Counters} -group Privileged -label Exception {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[23]}
+add wave -noupdate -expand -group {Performance Counters} -label {FDiv or IDiv Cycles} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[24]}
+add wave -noupdate -expand -group {Performance Counters} /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW
 add wave -noupdate -group {ifu } -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState
 add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/HREADY
 add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/FetchBuffer
@@ -675,7 +677,7 @@ add wave -noupdate /testbench/dut/core/fpu/fpu/fctrl/IllegalFPUInstrD
 add wave -noupdate /testbench/dut/core/fpu/fpu/fctrl/STATUS_FS
 add wave -noupdate /testbench/dut/core/priv/priv/csr/csrsr/STATUS_FS_INT
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {172636 ns} 1} {{Cursor 4} {578 ns} 0} {{Cursor 3} {152766 ns} 1}
+WaveRestoreCursors {{Cursor 4} {172636 ns} 1} {{Cursor 4} {5101 ns} 0} {{Cursor 3} {152766 ns} 1}
 quietly wave cursor active 2
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 194
@@ -691,4 +693,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {526 ns} {696 ns}
+WaveRestoreZoom {4326 ns} {6929 ns}

From 1fdfa024fc8fb57b8e4d0e9cb296bf693b910f9b Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Fri, 22 Sep 2023 16:00:32 -0500
Subject: [PATCH 11/32] Temporarily commit replacement parseTest.py for
 parseHPMC.py.

---
 bin/parseTest.py | 385 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 385 insertions(+)
 create mode 100755 bin/parseTest.py

diff --git a/bin/parseTest.py b/bin/parseTest.py
new file mode 100755
index 000000000..99bcd3fa1
--- /dev/null
+++ b/bin/parseTest.py
@@ -0,0 +1,385 @@
+#!/usr/bin/python3
+
+###########################################
+## Written: Rose Thompson ross1728@gmail.com
+## Created: 20 September 2023
+## Modified: 
+##
+## Purpose: Parses the performance counters from a modelsim trace.
+##
+## A component of the CORE-V-WALLY configurable RISC-V project.
+##
+## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+##
+## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+##
+## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+## may obtain a copy of the License at
+##
+## https:##solderpad.org/licenses/SHL-2.1/
+##
+## Unless required by applicable law or agreed to in writing, any work distributed under the 
+## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+## either express or implied. See the License for the specific language governing permissions 
+## and limitations under the License.
+################################################################################################
+
+import os
+import sys
+import matplotlib.pyplot as plt
+import math
+
+import argparse
+
+
+def ParseBranchListFile(path):
+    '''Take the path to the list of Questa Sim log files containing the performance counters outputs.  File
+    is formated in row columns.  Each row is a trace with the file, branch predictor type, and the parameters.
+    parameters can be any number and depend on the predictor type. Returns a list of lists.'''
+    lst = []
+    BranchList = open(path, 'r')
+    for line in BranchList:
+        tokens = line.split()
+        predictorLog = os.path.dirname(path) + '/' + tokens[0]
+        predictorType = tokens[1]
+        predictorParams = tokens[2::]
+        lst.append([predictorLog, predictorType, predictorParams])
+        #print(predictorLog, predictorType, predictorParams)
+    return lst
+    
+def ProcessFile(fileName):
+    '''Extract preformance counters from a modelsim log.  Outputs a list of tuples for each test/benchmark.
+    The tuple contains the test name, optimization characteristics, and dictionary of performance counters.'''
+    # 1 find lines with Read memfile and extract test name
+    # 2 parse counters into a list of (name, value) tuples (dictionary maybe?)
+    benchmarks = []
+    transcript = open(fileName, 'r')
+    HPMClist = { }
+    testName = ''
+    for line in transcript.readlines():
+        lineToken = line.split()
+        if(len(lineToken) > 3 and lineToken[1] == 'Read' and lineToken[2] == 'memfile'):
+            opt = lineToken[3].split('/')[-4]
+            testName = lineToken[3].split('/')[-1].split('.')[0]
+            HPMClist = { }
+        elif(len(lineToken) > 4 and lineToken[1][0:3] == 'Cnt'):
+            countToken = line.split('=')[1].split()
+            value = int(countToken[0])
+            name = ' '.join(countToken[1:])
+            HPMClist[name] = value
+        elif ('is done' in line):
+            benchmarks.append((testName, opt, HPMClist))
+    return benchmarks
+
+
+def ComputeStats(benchmarks):
+    for benchmark in benchmarks:
+        (nameString, opt, dataDict) = benchmark
+        dataDict['CPI'] = 1.0 * int(dataDict['Mcycle']) / int(dataDict['InstRet'])
+        dataDict['BDMR'] = 100.0 * int(dataDict['BP Dir Wrong']) / int(dataDict['Br Count'])
+        dataDict['BTMR'] = 100.0 * int(dataDict['BP Target Wrong']) / (int(dataDict['Br Count']) + int(dataDict['Jump Not Return']))
+        dataDict['RASMPR'] = 100.0 * int(dataDict['RAS Wrong']) / int(dataDict['Return'])
+        dataDict['ClassMPR'] = 100.0 * int(dataDict['Instr Class Wrong']) / int(dataDict['InstRet'])
+        dataDict['ICacheMR'] = 100.0 * int(dataDict['I Cache Miss']) / int(dataDict['I Cache Access'])
+
+        cycles = int(dataDict['I Cache Miss'])
+        if(cycles == 0): ICacheMR = 0
+        else: ICacheMR = 100.0 * int(dataDict['I Cache Cycles']) / cycles
+        dataDict['ICacheMT'] = ICacheMR
+
+        dataDict['DCacheMR'] = 100.0 * int(dataDict['D Cache Miss']) / int(dataDict['D Cache Access'])
+
+        (nameString, opt, dataDict) = benchmark
+        cycles = int(dataDict['D Cache Miss'])
+        if(cycles == 0): DCacheMR = 0
+        else: DCacheMR = 100.0 * int(dataDict['D Cache Cycles']) / cycles
+        dataDict['DCacheMT'] = DCacheMR
+
+
+def ComputeGeometricAverage(benchmarks):
+    fields = ['BDMR', 'BTMR', 'RASMPR', 'ClassMPR', 'ICacheMR', 'DCacheMR', 'CPI', 'ICacheMT', 'DCacheMT']
+    AllAve = {}
+    for field in fields:
+        Product = 1
+        index = 0
+        for (testName, opt, HPMCList) in benchmarks:
+            #print(HPMCList)
+            Product *= HPMCList[field]
+            index += 1
+        AllAve[field] = Product ** (1.0/index)
+    benchmarks.append(('Mean', '', AllAve))
+
+def GenerateName(predictorType, predictorParams):
+    if(predictorType == 'gshare' or  predictorType == 'twobit'):
+        return predictorType + predictorParams[0]
+    elif(predictorParams == 'local'):
+        return predictorType + predictorParams[0] + '_' + predictorParams[1]
+    else:
+        print(f'Error unsupported predictor type {predictorType}')
+        sys.exit(-1)
+
+def ComputePredNumEntries(predictorType, predictorParams):
+    if(predictorType == 'gshare' or  predictorType == 'twobit'):
+        return 2**int(predictorParams[0])
+    elif(predictorParams == 'local'):
+        return 2**int(predictorParams[0]) * int(predictorParams[1]) + 2**int(predictorParams[1])
+    else:
+        print(f'Error unsupported predictor type {predictorType}')
+        sys.exit(-1)
+
+def BuildDataBase(predictorLogs):
+    # Once done with the following loop, performanceCounterList will contain the predictor type and size along with the
+    # raw performance counter data and the processed data on a per benchmark basis.  It also includes the geometric mean.
+    # list
+    #   branch predictor configuration 0 (tuple)
+    #     benchmark name
+    #     compiler optimization
+    #     data (dictionary)
+    #       dictionary of performance counters
+    #   branch predictor configuration 1 (tuple)
+    #     benchmark name (dictionary)
+    #     compiler optimization
+    #     data
+    #       dictionary of performance counters
+    # ...
+    performanceCounterList = []
+    for trace in predictorLogs:
+        predictorLog = trace[0]
+        predictorType = trace[1]
+        predictorParams = trace[2]
+        # Extract the performance counter data
+        performanceCounters = ProcessFile(predictorLog)
+        ComputeStats(performanceCounters)
+        ComputeGeometricAverage(performanceCounters)
+        #print(performanceCounters)
+        performanceCounterList.append([GenerateName(predictorType, predictorParams), predictorType, performanceCounters, ComputePredNumEntries(predictorType, predictorParams)])
+    return performanceCounterList
+
+def ReorderDataBase(performanceCounterList):
+    # Reorder the data so the benchmark name comes first, then the branch predictor configuration
+    benchmarkFirstList = []
+    for (predictorName, predictorPrefixName, benchmarks, entries) in performanceCounterList:
+        for benchmark in benchmarks:
+            (nameString, opt, dataDict) = benchmark
+            benchmarkFirstList.append((nameString, opt, predictorName, predictorPrefixName, entries, dataDict))
+    return benchmarkFirstList
+
+def ExtractSelectedData(benchmarkFirstList):
+    # now extract all branch prediction direction miss rates for each
+    # namestring + opt, config
+    benchmarkDict = { }
+    for benchmark in benchmarkFirstList:
+        (name, opt, config, prefixName, entries, dataDict) = benchmark
+        if opt == 'bd_speedopt_speed': NewName = name+'Sp'
+        elif opt == 'bd_sizeopt_speed': NewName = name+'Sz'
+        else: NewName = name
+        #print(NewName)
+        #NewName = name+'_'+opt
+        if NewName in benchmarkDict:
+            benchmarkDict[NewName].append((config, prefixName, entries, dataDict[ReportPredictorType]))
+        else:
+            benchmarkDict[NewName] = [(config, prefixName, entries, dataDict[ReportPredictorType])]
+    return benchmarkDict
+
+def ReportAsTable(benchmarkDict):
+    refLine = benchmarkDict['Mean']
+    FirstLine = []
+    SecondLine = []
+    for (name, typ, size, val) in refLine:
+        FirstLine.append(name)
+        SecondLine.append(size)
+
+    sys.stdout.write('benchmark\t\t')
+    for name in FirstLine:
+        if(len(name) < 8): sys.stdout.write('%s\t\t' % name)
+        else: sys.stdout.write('%s\t' % name)        
+    sys.stdout.write('\n')
+    sys.stdout.write('size\t\t\t')
+    for size in SecondLine:
+        if(len(str(size)) < 8): sys.stdout.write('%d\t\t' % size)
+        else: sys.stdout.write('%d\t' % size)        
+    sys.stdout.write('\n')
+
+    if(args.summary):
+        sys.stdout.write('Mean\t\t\t')
+        for (name, typ, size, val) in refLine:
+            sys.stdout.write('%0.2f\t\t' % (val if not args.invert else 100 - val))
+        sys.stdout.write('\n')
+
+    if(not args.summary):
+        for benchmark in benchmarkDict:
+            length = len(benchmark)
+            if(length < 8): sys.stdout.write('%s\t\t\t' % benchmark)
+            elif(length < 16): sys.stdout.write('%s\t\t' % benchmark)
+            else: sys.stdout.write('%s\t' % benchmark)
+            for (name, typ, size, val) in benchmarkDict[benchmark]:
+                sys.stdout.write('%0.2f\t\t' % (val if not args.invert else 100 -val))
+            sys.stdout.write('\n')
+
+def ReportAsText(benchmarkDict):
+    if(args.summary):
+        mean = benchmarkDict['Mean']
+        print('Mean')
+        for (name, typ, size, val) in mean:
+            sys.stdout.write('%s %s %0.2f\n' % (name, size, val if not args.invert else 100 - val))
+        
+    if(not args.summary):
+        for benchmark in benchmarkDict:
+            print(benchmark)
+            for (name, type, size, val) in benchmarkDict[benchmark]:
+                sys.stdout.write('%s %s %0.2f\n' % (name, size, val if not args.invert else 100 - val))
+
+def ReportAsGraph(benchmarkDict, bar):
+    def FormatToPlot(currBenchmark):
+        names = []
+        sizes = []
+        values = []
+        typs = []
+        for config in currBenchmark:
+            names.append(config[0])
+            sizes.append(config[1])
+            values.append(config[2])
+            typs.append(config[3])
+        return (names, sizes, values, typs)
+    titlesInvert = {'BDMR' : 'Branch Direction Accuracy',
+              'BTMR' : 'Branch Target Accuracy',
+              'RASMPR': 'RAS Accuracy',
+              'ClassMPR': 'Class Prediction Accuracy'}
+    titles = {'BDMR' : 'Branch Direction Misprediction',
+              'BTMR' : 'Branch Target Misprediction',
+              'RASMPR': 'RAS Misprediction',
+              'ClassMPR': 'Class Misprediction'}
+    if(args.summary):
+        markers = ['x', '.', '+', '*', '^', 'o', ',', 's']
+        colors = ['black', 'blue', 'dodgerblue', 'turquoise', 'lightsteelblue', 'gray', 'black', 'blue']
+        temp = benchmarkDict['Mean']
+
+        # the benchmarkDict['Mean'] contains sequencies of results for multiple
+        # branch predictors with various parameterizations
+        # group the parameterizations by the common typ.
+        sequencies = {}
+        for (name, typ, size, value) in benchmarkDict['Mean']:
+            if not typ in sequencies:
+                sequencies[typ] = [(size, value)]
+            else:
+                sequencies[typ].append((size,value))
+        # then graph the common typ as a single line+scatter plot
+        # finally repeat for all typs of branch predictors and overlay
+        fig, axes = plt.subplots()
+        index = 0
+        if(args.invert): plt.title(titlesInvert[ReportPredictorType])
+        else: plt.title(titles[ReportPredictorType])
+        for branchPredName in sequencies:
+            data = sequencies[branchPredName]
+            (xdata, ydata) = zip(*data) 
+            if args.invert: ydata = [100 - x for x in ydata]
+            axes.plot(xdata, ydata, color=colors[index])
+            axes.scatter(xdata, ydata, label=branchPredName, color=colors[index], marker=markers[index])
+            index = (index + 1) % len(markers)
+        axes.legend(loc='upper left')
+        axes.set_xscale("log")
+        axes.set_ylabel('Prediction Accuracy')
+        axes.set_xlabel('Entries')
+        axes.set_xticks(xdata)
+        axes.set_xticklabels(xdata)
+        axes.grid(color='b', alpha=0.5, linestyle='dashed', linewidth=0.5)
+
+    if(not args.summary):
+        size = len(benchmarkDict)
+        sizeSqrt = math.sqrt(size)
+        isSquare = math.isclose(sizeSqrt, round(sizeSqrt))
+        numCol = math.floor(sizeSqrt)
+        numRow = numCol + (0 if isSquare else 1)
+        index = 1
+        fig = plt.figure()
+        for benchmarkName in benchmarkDict:
+            currBenchmark = benchmarkDict[benchmarkName]
+            (names, typs, sizes, values) = FormatToPlot(currBenchmark)
+            #axes.plot(numRow, numCol, index)
+            ax = fig.add_subplot(numRow, numCol, index)
+            ax.bar(names, values)
+            ax.title.set_text(benchmarkName)
+            #plt.ylabel('BR Dir Miss Rate (%)')
+            #plt.xlabel('Predictor')
+            index += 1
+    plt.show()
+
+
+# main
+parser = argparse.ArgumentParser(description='Parses performance counters from a Questa Sim trace to produce a graph or graphs.')
+
+# parse program arguments
+metric = parser.add_mutually_exclusive_group()
+metric.add_argument('-r', '--ras', action='store_const', help='Plot return address stack (RAS) performance.', default=False, const=True)
+metric.add_argument('-d', '--direction', action='store_const', help='Plot direction prediction (2-bit, Gshare, local, etc) performance.', default=False, const=True)
+metric.add_argument('-t', '--target', action='store_const', help='Plot branch target buffer (BTB) performance.', default=False, const=True)
+metric.add_argument('-c', '--iclass', action='store_const', help='Plot instruction classification performance.', default=False, const=True)
+
+parser.add_argument('-s', '--summary', action='store_const', help='Show only the geometric average for all benchmarks.', default=False, const=True)
+parser.add_argument('-b', '--bar', action='store_const', help='Plot graphs.', default=False, const=True)
+parser.add_argument('-g', '--reference', action='store_const', help='Include the golden reference model from branch-predictor-simulator. Data stored statically at the top of %(prog)s.  If you need to regenreate use CModelBranchAcurracy.sh', default=False, const=True)
+parser.add_argument('-i', '--invert', action='store_const', help='Invert metric. Example Branch miss prediction becomes prediction accuracy. 100 - miss rate', default=False, const=True)
+
+displayMode = parser.add_mutually_exclusive_group()
+displayMode.add_argument('--text', action='store_const', help='Display in text format only.', default=False, const=True)
+displayMode.add_argument('--table', action='store_const', help='Display in text format only.', default=False, const=True)
+displayMode.add_argument('--gui', action='store_const', help='Display in text format only.', default=False, const=True)
+displayMode.add_argument('--debug', action='store_const', help='Display in text format only.', default=False, const=True)
+parser.add_argument('sources', nargs=1)
+
+args = parser.parse_args()
+
+# Figure what we are reporting
+ReportPredictorType = 'BDMR'  # default
+if(args.ras): ReportPredictorType = 'RASMPR'
+if(args.target): ReportPredictorType = 'BTMR'
+if(args.iclass): ReportPredictorType = 'ClassMPR'
+
+# Figure how we are displaying the data
+ReportMode = 'gui' # default
+if(args.text): ReportMode = 'text'
+if(args.table): ReportMode = 'table'
+if(args.debug): ReportMode = 'debug'
+
+# read the questa sim list file.
+# row, col format.  each row is a questa sim run with performance counters and a particular
+# branch predictor type and size. size can be multiple parameters for more complex predictors like
+# local history and tage.
+# <file> <type> <size>
+predictorLogs = ParseBranchListFile(args.sources[0])          # digests the traces
+performanceCounterList = BuildDataBase(predictorLogs)         # builds a database of performance counters by trace and then by benchmark
+benchmarkFirstList = ReorderDataBase(performanceCounterList)  # reorder first by benchmark then trace
+benchmarkDict = ExtractSelectedData(benchmarkFirstList)       # filters to just the desired performance counter metric
+
+#print(benchmarkDict['Mean'])
+#print(benchmarkDict['aha-mont64Speed'])
+#print(benchmarkDict)
+
+# table format
+if(ReportMode == 'table'):
+    ReportAsTable(benchmarkDict)
+
+if(ReportMode == 'text'):
+    ReportAsText(benchmarkDict)
+
+if(ReportMode == 'gui'):
+    ReportAsGraph(benchmarkDict, args.bar)
+            
+# *** this is only needed of -b (no -s)
+
+# debug
+#config0 = performanceCounterList[0][0]
+#data0 = performanceCounterList[0][1]
+#bench0 = data0[0]
+#bench0name = bench0[0]
+#bench0data = bench0[2]
+#bench0BrCount = bench0data['Br Count']
+#bench1 = data0[1]
+
+#print(data0)
+#print(bench0)
+#print(bench1)
+
+#print(bench0name)
+#print(bench0BrCount)

From 1cb278913ade66cf09e56b1811f845297deaba13 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 25 Sep 2023 09:55:38 -0500
Subject: [PATCH 12/32] Major improvement to the bar graph generation.

---
 bin/parseTest.py | 63 +++++++++++++++++++++++++++++++++++++++++-------
 1 file changed, 54 insertions(+), 9 deletions(-)

diff --git a/bin/parseTest.py b/bin/parseTest.py
index 99bcd3fa1..966572955 100755
--- a/bin/parseTest.py
+++ b/bin/parseTest.py
@@ -29,7 +29,7 @@ import os
 import sys
 import matplotlib.pyplot as plt
 import math
-
+import numpy as np
 import argparse
 
 
@@ -285,6 +285,25 @@ def ReportAsGraph(benchmarkDict, bar):
         axes.set_xticklabels(xdata)
         axes.grid(color='b', alpha=0.5, linestyle='dashed', linewidth=0.5)
 
+    # if(not args.summary):
+    #     size = len(benchmarkDict)
+    #     sizeSqrt = math.sqrt(size)
+    #     isSquare = math.isclose(sizeSqrt, round(sizeSqrt))
+    #     numCol = math.floor(sizeSqrt)
+    #     numRow = numCol + (0 if isSquare else 1)
+    #     index = 1
+    #     fig = plt.figure()
+    #     for benchmarkName in benchmarkDict:
+    #         currBenchmark = benchmarkDict[benchmarkName]
+    #         (names, typs, sizes, values) = FormatToPlot(currBenchmark)
+    #         #axes.plot(numRow, numCol, index)
+    #         ax = fig.add_subplot(numRow, numCol, index)
+    #         ax.bar(names, values)
+    #         ax.title.set_text(benchmarkName)
+    #         #plt.ylabel('BR Dir Miss Rate (%)')
+    #         #plt.xlabel('Predictor')
+    #         index += 1
+
     if(not args.summary):
         size = len(benchmarkDict)
         sizeSqrt = math.sqrt(size)
@@ -292,17 +311,43 @@ def ReportAsGraph(benchmarkDict, bar):
         numCol = math.floor(sizeSqrt)
         numRow = numCol + (0 if isSquare else 1)
         index = 1
-        fig = plt.figure()
+        fig = plt.subplots()
+        testLimit = 7
+
+        xlabelList = []
+        seriesDict = {}
+        NumberInGroup = len(benchmarkDict['Mean'])
+        # Figure out width of bars.  NumberInGroup bars + want 2 bar space
+        # the space between groups is 1
+        EffectiveNumInGroup = NumberInGroup + 2
+        barWidth = 1 / EffectiveNumInGroup
         for benchmarkName in benchmarkDict:
             currBenchmark = benchmarkDict[benchmarkName]
-            (names, typs, sizes, values) = FormatToPlot(currBenchmark)
-            #axes.plot(numRow, numCol, index)
-            ax = fig.add_subplot(numRow, numCol, index)
-            ax.bar(names, values)
-            ax.title.set_text(benchmarkName)
-            #plt.ylabel('BR Dir Miss Rate (%)')
-            #plt.xlabel('Predictor')
+            xlabelList.append(benchmarkName)
+            for (name, typ, size, value) in currBenchmark:
+                if(name not in seriesDict):
+                    seriesDict[name] = [value]
+                else:
+                    seriesDict[name].append(value)
+            #print(currBenchmark)
+            #(names, typs, sizes, values) = FormatToPlot(currBenchmark)
+            #xpos = np.arange(testLimit + index*barWidth)
+            #print(f'xpos = {xpos}, values={values}')
+            #plt.bar(xpos, values, wdith=barWidth, edgecolor='grey', label=names)
+            if(index >= testLimit): break
             index += 1
+        print(f'xlabelList = {xlabelList}')
+        print(f'seriesDict = {seriesDict}')
+        index = 0
+        for name in seriesDict:
+            xpos = np.arange(testLimit)
+            xpos = [x + index*barWidth for x in xpos]
+            values = seriesDict[name]
+            print(f'xpos = {xpos}, values={values}')
+            plt.bar(xpos, values, width=barWidth, edgecolor='grey', label=name)
+            index += 1
+        plt.xticks([r + barWidth*(NumberInGroup/2-0.5) for r in range(0, testLimit)], xlabelList)
+        plt.legend()
     plt.show()
 
 

From 81dd6517f104d95da0dea663af6b7852cfdb0aff Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 25 Sep 2023 10:09:33 -0500
Subject: [PATCH 13/32] Now produces beautiful graphs.

---
 bin/parseTest.py | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/bin/parseTest.py b/bin/parseTest.py
index 966572955..5cdcd81d4 100755
--- a/bin/parseTest.py
+++ b/bin/parseTest.py
@@ -321,6 +321,7 @@ def ReportAsGraph(benchmarkDict, bar):
         # the space between groups is 1
         EffectiveNumInGroup = NumberInGroup + 2
         barWidth = 1 / EffectiveNumInGroup
+        colors = ['blue', 'blue', 'blue', 'blue', 'blue', 'blue', 'black', 'black', 'black', 'black', 'black', 'black']
         for benchmarkName in benchmarkDict:
             currBenchmark = benchmarkDict[benchmarkName]
             xlabelList.append(benchmarkName)
@@ -344,10 +345,13 @@ def ReportAsGraph(benchmarkDict, bar):
             xpos = [x + index*barWidth for x in xpos]
             values = seriesDict[name]
             print(f'xpos = {xpos}, values={values}')
-            plt.bar(xpos, values, width=barWidth, edgecolor='grey', label=name)
+            plt.bar(xpos, values, width=barWidth, edgecolor='grey', label=name, color=colors[index%len(colors)])
             index += 1
         plt.xticks([r + barWidth*(NumberInGroup/2-0.5) for r in range(0, testLimit)], xlabelList)
-        plt.legend()
+        plt.xlabel('Benchmark')
+        if(not args.invert): plt.ylabel('Misprediction Rate Accuracy (%)')
+        else:  plt.ylabel('Prediction Accuracy (%)') 
+        plt.legend(loc='upper left', ncol=2)
     plt.show()
 
 

From 6b22138bf6aadd33fe82ed29ac85fcb7f6ff51c9 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 25 Sep 2023 12:45:09 -0500
Subject: [PATCH 14/32] Finally have this script generating beautiful bar plots
 of branch predictor misrates.

---
 bin/parseTest.py | 88 +++++++++++++++++++++++++++++++-----------------
 1 file changed, 58 insertions(+), 30 deletions(-)

diff --git a/bin/parseTest.py b/bin/parseTest.py
index 5cdcd81d4..ba3309aff 100755
--- a/bin/parseTest.py
+++ b/bin/parseTest.py
@@ -230,6 +230,40 @@ def ReportAsText(benchmarkDict):
             for (name, type, size, val) in benchmarkDict[benchmark]:
                 sys.stdout.write('%s %s %0.2f\n' % (name, size, val if not args.invert else 100 - val))
 
+def Inversion(lst):
+    return [x if not args.invert else 100 - x for x in lst]
+
+def BarGraph(seriesDict, xlabelList, BenchPerRow, FileName):
+    index = 0
+    NumberInGroup = len(seriesDict)
+    # Figure out width of bars.  NumberInGroup bars + want 2 bar space
+    # the space between groups is 1
+    EffectiveNumInGroup = NumberInGroup + 2
+    barWidth = 1 / EffectiveNumInGroup
+    fig = plt.subplots(figsize = (EffectiveNumInGroup*BenchPerRow/8, 4))
+    colors = ['blue', 'blue', 'blue', 'blue', 'blue', 'blue', 'black', 'black', 'black', 'black', 'black', 'black']
+    for name in seriesDict:
+        xpos = np.arange(BenchPerRow)
+        xpos = [x + index*barWidth for x in xpos]
+        values = seriesDict[name]
+        plt.bar(xpos, Inversion(values), width=barWidth, edgecolor='grey', label=name, color=colors[index%len(colors)])
+        index += 1
+    plt.xticks([r + barWidth*(NumberInGroup/2-0.5) for r in range(0, BenchPerRow)], xlabelList)
+    plt.xlabel('Benchmark')
+    if(not args.invert): plt.ylabel('Misprediction Rate (%)')
+    else:  plt.ylabel('Prediction Accuracy (%)') 
+    plt.legend(loc='upper left', ncol=2)
+    plt.savefig(FileName)
+
+def SelectPartition(xlabelListBig, seriesDictBig, group, BenchPerRow):
+    seriesDictTrunk = {}
+    for benchmarkName in seriesDictBig:
+        lst = seriesDictBig[benchmarkName]
+        seriesDictTrunk[benchmarkName] = lst[group*BenchPerRow:(group+1)*BenchPerRow]
+    xlabelListTrunk = xlabelListBig[group*BenchPerRow:(group+1)*BenchPerRow]
+    return(xlabelListTrunk, seriesDictTrunk)
+
+
 def ReportAsGraph(benchmarkDict, bar):
     def FormatToPlot(currBenchmark):
         names = []
@@ -284,6 +318,8 @@ def ReportAsGraph(benchmarkDict, bar):
         axes.set_xticks(xdata)
         axes.set_xticklabels(xdata)
         axes.grid(color='b', alpha=0.5, linestyle='dashed', linewidth=0.5)
+        plt.show()
+        
 
     # if(not args.summary):
     #     size = len(benchmarkDict)
@@ -311,17 +347,11 @@ def ReportAsGraph(benchmarkDict, bar):
         numCol = math.floor(sizeSqrt)
         numRow = numCol + (0 if isSquare else 1)
         index = 1
-        fig = plt.subplots()
-        testLimit = 7
+        BenchPerRow = 7
 
         xlabelList = []
         seriesDict = {}
-        NumberInGroup = len(benchmarkDict['Mean'])
-        # Figure out width of bars.  NumberInGroup bars + want 2 bar space
-        # the space between groups is 1
-        EffectiveNumInGroup = NumberInGroup + 2
-        barWidth = 1 / EffectiveNumInGroup
-        colors = ['blue', 'blue', 'blue', 'blue', 'blue', 'blue', 'black', 'black', 'black', 'black', 'black', 'black']
+
         for benchmarkName in benchmarkDict:
             currBenchmark = benchmarkDict[benchmarkName]
             xlabelList.append(benchmarkName)
@@ -330,29 +360,27 @@ def ReportAsGraph(benchmarkDict, bar):
                     seriesDict[name] = [value]
                 else:
                     seriesDict[name].append(value)
-            #print(currBenchmark)
-            #(names, typs, sizes, values) = FormatToPlot(currBenchmark)
-            #xpos = np.arange(testLimit + index*barWidth)
-            #print(f'xpos = {xpos}, values={values}')
-            #plt.bar(xpos, values, wdith=barWidth, edgecolor='grey', label=names)
-            if(index >= testLimit): break
+            if(index >= BenchPerRow): break
             index += 1
-        print(f'xlabelList = {xlabelList}')
-        print(f'seriesDict = {seriesDict}')
-        index = 0
-        for name in seriesDict:
-            xpos = np.arange(testLimit)
-            xpos = [x + index*barWidth for x in xpos]
-            values = seriesDict[name]
-            print(f'xpos = {xpos}, values={values}')
-            plt.bar(xpos, values, width=barWidth, edgecolor='grey', label=name, color=colors[index%len(colors)])
-            index += 1
-        plt.xticks([r + barWidth*(NumberInGroup/2-0.5) for r in range(0, testLimit)], xlabelList)
-        plt.xlabel('Benchmark')
-        if(not args.invert): plt.ylabel('Misprediction Rate Accuracy (%)')
-        else:  plt.ylabel('Prediction Accuracy (%)') 
-        plt.legend(loc='upper left', ncol=2)
-    plt.show()
+
+        xlabelListBig = []
+        seriesDictBig = {}
+        for benchmarkName in benchmarkDict:
+            currBenchmark = benchmarkDict[benchmarkName]
+            xlabelListBig.append(benchmarkName)
+            for (name, typ, size, value) in currBenchmark:
+                if(name not in seriesDictBig):
+                    seriesDictBig[name] = [value]
+                else:
+                    seriesDictBig[name].append(value)
+
+        #The next step will be to split the benchmarkDict into length BenchPerRow pieces then repeat the following code
+        # on each piece.
+        for row in range(0, math.ceil(39 / BenchPerRow)):
+            (xlabelListTrunk, seriesDictTrunk) = SelectPartition(xlabelListBig, seriesDictBig, row, BenchPerRow)
+            FileName = 'barSegment%d.png' % row
+            groupLen = len(xlabelListTrunk)
+            BarGraph(seriesDictTrunk, xlabelListTrunk, groupLen, FileName)
 
 
 # main

From 0215c375944d83f5ff0f543e805b9c6b16411ffe Mon Sep 17 00:00:00 2001
From: Jacob Pease <jacobpease@protonmail.com>
Date: Mon, 25 Sep 2023 18:04:51 -0500
Subject: [PATCH 15/32] Fixed error with finding vmlinux and busybox
 directories too early.

---
 linux/Makefile | 31 ++++++++++++++++++++-----------
 1 file changed, 20 insertions(+), 11 deletions(-)

diff --git a/linux/Makefile b/linux/Makefile
index 95a849fcf..433bf0e73 100644
--- a/linux/Makefile
+++ b/linux/Makefile
@@ -15,7 +15,7 @@ WALLYBOARD := $(BUILDROOT)/board/wally
 PACKAGE_SOURCE := ${WALLYLINUX}/buildroot-packages/package-source
 FPGA_AXI_SDC := ${WALLYLINUX}/buildroot-packages/fpga-axi-sdc
 DRIVER := ${PACKAGE_SOURCE}/fpga-axi-sdc.c
-PATCHFILE := $(BRPACKAGES)/package.patch
+PATCHFILE := $(BRPACKAGES)/package-2023.05.1.patch
 
 # Device tree files 
 DTS ?= $(shell find -type f -regex ".*\.dts" | sort)
@@ -32,8 +32,17 @@ OBJDUMPS := $(foreach name, $(OBJDUMPS), $(DIS)/$(name).objdump)
 # BUSYBOXDIR := $(shell ls $(BUILDROOT)/output/build | grep -e '^linux-[0-9]\+\.[0-9]\+\.[0-9]\+$$' )
 # BUSYBOXDIR := $(BUILDROOT)/output/build/$(BUSYBOXDIR)
 
-LINUXDIR := $(shell find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/linux-[0-9]+\.[0-9]+\.[0-9]+$$")
-BUSYBOXDIR := $(shell find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/busybox-[0-9]+\.[0-9]+\.[0-9]+$$")
+# Gets Linux and Busybox output folders for objedect dumps
+# LINUXDIR ?= $(shell find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/linux-[0-9]+\.[0-9]+\.[0-9]+$$")
+# BUSYBOXDIR ?= $(shell find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/busybox-[0-9]+\.[0-9]+\.[0-9]+$$")
+
+define linuxDir =
+$(shell find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/linux-[0-9]+\.[0-9]+\.[0-9]+$$")
+endef
+
+define busyboxDir =
+$(shell find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/busybox-[0-9]+\.[0-9]+\.[0-9]+$$")
+endef
 
 .PHONY: all generate disassemble install clean cleanDTB cleanDriver test
 
@@ -50,8 +59,8 @@ all:
 
 # Temp rule for debugging
 test:
-	@echo $(LINUXDIR)
-	@echo $(BUSYBOXDIR)
+	@echo $(linuxDir)
+	@echo $(busyboxDir)
 
 generate: $(DTB) $(IMAGES)
 
@@ -78,16 +87,16 @@ $(DIS)/%.objdump: $(IMAGES)/%.elf
 $(DIS)/%.objdump: $(IMAGES)/%
 	riscv64-unknown-elf-objdump -S $< >> $@
 
-$(IMAGES)/vmlinux: $(LINUXDIR)/vmlinux
+$(IMAGES)/vmlinux: $(call linuxDir)/vmlinux
 	cp $< $@
 
-$(IMAGES)/busybox: $(BUSYBOXDIR)/busybox
+$(IMAGES)/busybox: $(call busyboxDir)/busybox
 	cp $< $@
 
 # Generating new Buildroot directories --------------------------------
 
 # This directive should be run as: make install BUILDROOT=path/to/buildroot
-install: $(BUILDROOT)/package/fpga-axi-sdc $(WALLYBOARD) $(DRIVER)
+install: $(BUILDROOT)/package/fpga-axi-sdc $(WALLYBOARD)
 	cp $(WALLYBOARD)/main.config $(BUILDROOT)/.config
 
 # CONFIG DEPENDENCIES 2021.05 -----------------------------------------
@@ -122,9 +131,9 @@ $(BUILDROOT):
 	cd $@; git checkout 2023.05.x
 	#cd $@; git checkout 2021.05
 
-$(DRIVER):
-	@ if [ -d "$(WALLY)/addins/vivado-risc-v" ] ; then git submodule update --init $(WALLY)/addins/vivado-risc-v; fi
-	cp ../addins/vivado-risc-v/patches/fpga-axi-sdc.c $@
+#$(DRIVER):
+#	@ if [ -d "$(WALLY)/addins/vivado-risc-v" ] ; then git submodule update --init $(WALLY)/addins/vivado-risc-v; fi
+#	cp ../addins/vivado-risc-v/patches/fpga-axi-sdc.c $@
 	# For 2021.05
 	#sed -i "s|card_hw_reset|hw_reset|1" $@
 

From e6672c28189953a7a4949e25911f2c3f34b17945 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 25 Sep 2023 18:16:58 -0500
Subject: [PATCH 16/32] add c++ support to buildroot's config file. this is
 needed for running tensorflow's benchmark.

---
 .../buildroot-2023.05.1/main.config           | 1498 ++++-------------
 1 file changed, 298 insertions(+), 1200 deletions(-)

diff --git a/linux/buildroot-config-src/buildroot-2023.05.1/main.config b/linux/buildroot-config-src/buildroot-2023.05.1/main.config
index c7745f443..bb0547d71 100644
--- a/linux/buildroot-config-src/buildroot-2023.05.1/main.config
+++ b/linux/buildroot-config-src/buildroot-2023.05.1/main.config
@@ -1,6 +1,6 @@
 #
 # Automatically generated file; DO NOT EDIT.
-# Buildroot 2023.05.1-dirty Configuration
+# Buildroot 2023.05.2-166-gb362115b25 Configuration
 #
 BR2_HAVE_DOT_CONFIG=y
 BR2_HOST_GCC_AT_LEAST_4_9=y
@@ -99,7 +99,7 @@ BR2_KERNEL_HEADERS_6_3=y
 # BR2_KERNEL_HEADERS_CUSTOM_TARBALL is not set
 # BR2_KERNEL_HEADERS_CUSTOM_GIT is not set
 BR2_KERNEL_HEADERS_LATEST=y
-BR2_DEFAULT_KERNEL_HEADERS="6.3.12"
+BR2_DEFAULT_KERNEL_HEADERS="6.3.13"
 BR2_PACKAGE_LINUX_HEADERS=y
 BR2_PACKAGE_MUSL_ARCH_SUPPORTS=y
 BR2_PACKAGE_MUSL_SUPPORTS=y
@@ -133,7 +133,7 @@ BR2_BINUTILS_EXTRA_CONFIG_OPTIONS=""
 BR2_GCC_VERSION_12_X=y
 BR2_GCC_VERSION="12.3.0"
 BR2_EXTRA_GCC_CONFIG_OPTIONS=""
-# BR2_TOOLCHAIN_BUILDROOT_CXX is not set
+BR2_TOOLCHAIN_BUILDROOT_CXX=y
 # BR2_TOOLCHAIN_BUILDROOT_FORTRAN is not set
 # BR2_GCC_ENABLE_OPENMP is not set
 # BR2_GCC_ENABLE_GRAPHITE is not set
@@ -151,6 +151,7 @@ BR2_TOOLCHAIN_SUPPORTS_ALWAYS_LOCKFREE_ATOMIC_INTS=y
 BR2_TOOLCHAIN_SUPPORTS_VARIADIC_MI_THUNK=y
 BR2_USE_WCHAR=y
 BR2_ENABLE_LOCALE=y
+BR2_INSTALL_LIBSTDCPP=y
 BR2_TOOLCHAIN_HAS_THREADS=y
 BR2_TOOLCHAIN_HAS_THREADS_DEBUG=y
 BR2_TOOLCHAIN_HAS_THREADS_NPTL=y
@@ -406,7 +407,7 @@ BR2_LINUX_KERNEL_LATEST_VERSION=y
 # BR2_LINUX_KERNEL_CUSTOM_GIT is not set
 # BR2_LINUX_KERNEL_CUSTOM_HG is not set
 # BR2_LINUX_KERNEL_CUSTOM_SVN is not set
-BR2_LINUX_KERNEL_VERSION="6.3.12"
+BR2_LINUX_KERNEL_VERSION="6.3.13"
 BR2_LINUX_KERNEL_PATCH=""
 # BR2_LINUX_KERNEL_USE_DEFCONFIG is not set
 # BR2_LINUX_KERNEL_USE_ARCH_DEFAULT_CONFIG is not set
@@ -475,31 +476,19 @@ BR2_PACKAGE_SKELETON_INIT_SYSV=y
 # BR2_PACKAGE_BLUEZ_ALSA is not set
 # BR2_PACKAGE_DVBLAST is not set
 # BR2_PACKAGE_DVDAUTHOR is not set
-
-#
-# dvdrw-tools needs a toolchain w/ threads, C++, wchar
-#
-
-#
-# espeak needs a toolchain w/ C++, wchar, threads, dynamic library
-#
+# BR2_PACKAGE_DVDRW_TOOLS is not set
+# BR2_PACKAGE_ESPEAK is not set
 # BR2_PACKAGE_FAAD2 is not set
 BR2_PACKAGE_FFMPEG_ARCH_SUPPORTS=y
 # BR2_PACKAGE_FFMPEG is not set
 # BR2_PACKAGE_FLAC is not set
 # BR2_PACKAGE_FLITE is not set
 # BR2_PACKAGE_FLUID_SOUNDFONT is not set
-
-#
-# fluidsynth needs a toolchain w/ threads, wchar, dynamic library, C++
-#
+# BR2_PACKAGE_FLUIDSYNTH is not set
 # BR2_PACKAGE_GMRENDER_RESURRECT is not set
 # BR2_PACKAGE_GSTREAMER1 is not set
 # BR2_PACKAGE_JACK1 is not set
-
-#
-# jack2 needs a toolchain w/ threads, C++, dynamic library
-#
+# BR2_PACKAGE_JACK2 is not set
 BR2_PACKAGE_KODI_ARCH_SUPPORTS=y
 
 #
@@ -521,31 +510,16 @@ BR2_PACKAGE_KODI_ARCH_SUPPORTS=y
 #
 # miraclecast needs systemd and a glibc toolchain w/ threads and wchar
 #
-
-#
-# mjpegtools needs a toolchain w/ C++, threads
-#
-
-#
-# modplugtools needs a toolchain w/ C++
-#
+# BR2_PACKAGE_MJPEGTOOLS is not set
+# BR2_PACKAGE_MODPLUGTOOLS is not set
 # BR2_PACKAGE_MOTION is not set
-
-#
-# mpd needs a toolchain w/ C++, threads, wchar, gcc >= 8, host gcc >= 8
-#
+# BR2_PACKAGE_MPD is not set
 # BR2_PACKAGE_MPD_MPC is not set
 # BR2_PACKAGE_MPG123 is not set
-
-#
-# mpv needs a toolchain w/ C++, NPTL, gcc >= 4.9
-#
+# BR2_PACKAGE_MPV is not set
 # BR2_PACKAGE_MULTICAT is not set
 # BR2_PACKAGE_MUSEPACK is not set
-
-#
-# ncmpc needs a toolchain w/ C++, wchar, threads, gcc >= 10
-#
+# BR2_PACKAGE_NCMPC is not set
 # BR2_PACKAGE_OPUS_TOOLS is not set
 # BR2_PACKAGE_PIPEWIRE is not set
 BR2_PACKAGE_PULSEAUDIO_HAS_ATOMIC=y
@@ -554,59 +528,31 @@ BR2_PACKAGE_PULSEAUDIO_HAS_ATOMIC=y
 # BR2_PACKAGE_SPEECHD is not set
 # BR2_PACKAGE_SQUEEZELITE is not set
 # BR2_PACKAGE_TINYCOMPRESS is not set
-
-#
-# tovid needs a toolchain w/ NPTL, C++, wchar, gcc >= 4.9
-#
 # BR2_PACKAGE_TSTOOLS is not set
 # BR2_PACKAGE_TWOLAME is not set
 # BR2_PACKAGE_UDPXY is not set
-
-#
-# upmpdcli needs a toolchain w/ C++, NPTL, gcc >= 4.9
-#
-
-#
-# v4l2grab needs a toolchain w/ threads, dynamic library, C++ and headers >= 3.0
-#
+# BR2_PACKAGE_UPMPDCLI is not set
+# BR2_PACKAGE_V4L2GRAB is not set
 # BR2_PACKAGE_V4L2LOOPBACK is not set
-
-#
-# vlc needs a toolchain w/ C++, dynamic library, wchar, threads, gcc >= 4.9, headers >= 3.7
-#
+# BR2_PACKAGE_VLC is not set
 # BR2_PACKAGE_VORBIS_TOOLS is not set
 # BR2_PACKAGE_WAVPACK is not set
 # BR2_PACKAGE_YAVTA is not set
 # BR2_PACKAGE_YMPD is not set
-
-#
-# zynaddsubfx needs a toolchain w/ C++11 and threads
-#
+# BR2_PACKAGE_ZYNADDSUBFX is not set
 
 #
 # Compressors and decompressors
 #
 # BR2_PACKAGE_BROTLI is not set
 # BR2_PACKAGE_BZIP2 is not set
-
-#
-# lrzip needs a toolchain w/ wchar, threads, C++
-#
-
-#
-# lzip needs a toolchain w/ C++
-#
+# BR2_PACKAGE_LRZIP is not set
+# BR2_PACKAGE_LZIP is not set
 # BR2_PACKAGE_LZOP is not set
-
-#
-# p7zip needs a toolchain w/ threads, wchar, C++
-#
+# BR2_PACKAGE_P7ZIP is not set
 # BR2_PACKAGE_PIGZ is not set
 # BR2_PACKAGE_PIXZ is not set
-
-#
-# unrar needs a toolchain w/ C++, wchar, threads, gcc >= 4.8
-#
+# BR2_PACKAGE_UNRAR is not set
 # BR2_PACKAGE_XZ is not set
 # BR2_PACKAGE_ZIP is not set
 # BR2_PACKAGE_ZSTD is not set
@@ -616,10 +562,7 @@ BR2_PACKAGE_PULSEAUDIO_HAS_ATOMIC=y
 #
 # BR2_PACKAGE_BABELTRACE2 is not set
 # BR2_PACKAGE_BLKTRACE is not set
-
-#
-# bonnie++ needs a toolchain w/ C++
-#
+# BR2_PACKAGE_BONNIE is not set
 # BR2_PACKAGE_CACHE_CALIBRATOR is not set
 
 #
@@ -641,16 +584,10 @@ BR2_PACKAGE_DHRYSTONE=y
 # BR2_PACKAGE_DROPWATCH is not set
 # BR2_PACKAGE_DSTAT is not set
 # BR2_PACKAGE_DT is not set
-
-#
-# duma needs a toolchain w/ C++, threads, dynamic library
-#
+# BR2_PACKAGE_DUMA is not set
 # BR2_PACKAGE_FIO is not set
 BR2_PACKAGE_GDB_ARCH_SUPPORTS=y
-
-#
-# gdb/gdbserver >= 8.x needs a toolchain w/ C++, gcc >= 4.8
-#
+# BR2_PACKAGE_GDB is not set
 # BR2_PACKAGE_IOZONE is not set
 # BR2_PACKAGE_KMEMD is not set
 # BR2_PACKAGE_LATENCYTOP is not set
@@ -669,23 +606,13 @@ BR2_PACKAGE_LTP_TESTSUITE_ARCH_SUPPORTS=y
 # BR2_PACKAGE_PAX_UTILS is not set
 BR2_PACKAGE_PERFTEST_ARCH_SUPPORTS=y
 # BR2_PACKAGE_PERFTEST is not set
-
-#
-# piglit needs a glibc or musl toolchain w/ C++
-#
 # BR2_PACKAGE_POKE is not set
 # BR2_PACKAGE_PV is not set
 # BR2_PACKAGE_RAMSMP is not set
 BR2_PACKAGE_RAMSPEED=y
 # BR2_PACKAGE_RT_TESTS is not set
-
-#
-# rwmem needs a toolchain w/ C++, wchar, gcc >= 5
-#
-
-#
-# signal-estimator needs a toochain w/ C++, threads, gcc >= 7
-#
+# BR2_PACKAGE_RWMEM is not set
+# BR2_PACKAGE_SIGNAL_ESTIMATOR is not set
 # BR2_PACKAGE_SPIDEV_TEST is not set
 # BR2_PACKAGE_STRACE is not set
 # BR2_PACKAGE_STRESS is not set
@@ -709,33 +636,18 @@ BR2_PACKAGE_WHETSTONE=y
 # BR2_PACKAGE_BSDIFF is not set
 # BR2_PACKAGE_CHECK is not set
 BR2_PACKAGE_CMAKE_ARCH_SUPPORTS=y
-
-#
-# ctest needs a toolchain w/ C++, wchar, dynamic library, gcc >= 4.7, NPTL
-#
-
-#
-# cppunit needs a toolchain w/ C++, dynamic library
-#
+# BR2_PACKAGE_CMAKE_CTEST is not set
+# BR2_PACKAGE_CPPUNIT is not set
 # BR2_PACKAGE_CUKINIA is not set
 # BR2_PACKAGE_CUNIT is not set
 # BR2_PACKAGE_CVS is not set
-
-#
-# cxxtest needs a toolchain w/ C++ support
-#
+# BR2_PACKAGE_CXXTEST is not set
 # BR2_PACKAGE_FLEX is not set
 # BR2_PACKAGE_GETTEXT is not set
 BR2_PACKAGE_PROVIDES_HOST_GETTEXT="host-gettext-tiny"
 # BR2_PACKAGE_GIT is not set
-
-#
-# git-crypt needs a toolchain w/ C++, gcc >= 4.9
-#
-
-#
-# gperf needs a toolchain w/ C++
-#
+# BR2_PACKAGE_GIT_CRYPT is not set
+# BR2_PACKAGE_GPERF is not set
 # BR2_PACKAGE_JO is not set
 # BR2_PACKAGE_JQ is not set
 # BR2_PACKAGE_LIBTOOL is not set
@@ -837,17 +749,15 @@ BR2_PACKAGE_PROVIDES_HOST_GETTEXT="host-gettext-tiny"
 #
 # BR2_PACKAGE_ASCII_INVADERS is not set
 # BR2_PACKAGE_CHOCOLATE_DOOM is not set
-
-#
-# flare-engine needs a toolchain w/ C++, dynamic library
-#
+# BR2_PACKAGE_FLARE_ENGINE is not set
 # BR2_PACKAGE_FROTZ is not set
-
-#
-# gnuchess needs a toolchain w/ C++, threads
-#
+# BR2_PACKAGE_GNUCHESS is not set
 # BR2_PACKAGE_LBREAKOUT2 is not set
 # BR2_PACKAGE_LTRIS is not set
+
+#
+# minetest needs X11 and an OpenGL provider
+#
 # BR2_PACKAGE_OPENTYRIAN is not set
 # BR2_PACKAGE_PRBOOM is not set
 # BR2_PACKAGE_SL is not set
@@ -855,10 +765,7 @@ BR2_PACKAGE_PROVIDES_HOST_GETTEXT="host-gettext-tiny"
 #
 # solarus needs OpenGL and a toolchain w/ C++, gcc >= 4.9, NPTL, dynamic library, and luajit or lua 5.1
 #
-
-#
-# stella needs a toolchain w/ dynamic library, C++, threads, gcc >= 7
-#
+# BR2_PACKAGE_STELLA is not set
 # BR2_PACKAGE_XORCURSES is not set
 
 #
@@ -880,7 +787,7 @@ BR2_PACKAGE_PROVIDES_HOST_GETTEXT="host-gettext-tiny"
 # BR2_PACKAGE_GHOSTSCRIPT is not set
 
 #
-# glmark2 needs a toolchain w/ C++, gcc >= 4.9
+# glmark2 needs an OpenGL or an openGL ES and EGL backend
 #
 
 #
@@ -892,16 +799,9 @@ BR2_PACKAGE_PROVIDES_HOST_GETTEXT="host-gettext-tiny"
 #
 # kmscube needs EGL, GBM and OpenGL ES, and a toolchain w/ thread support
 #
-
-#
-# libva-utils needs a toolchain w/ C++, threads, dynamic library
-#
+# BR2_PACKAGE_LIBVA_UTILS is not set
 BR2_PACKAGE_MIDORI_ARCH_SUPPORTS=y
 
-#
-# midori needs a glibc toolchain w/ C++, wchar, threads, dynamic library, gcc >= 7, host gcc >= 8
-#
-
 #
 # midori needs libgtk3 w/ X11 or wayland backend
 #
@@ -917,58 +817,29 @@ BR2_PACKAGE_NETSURF_ARCH_SUPPORTS=y
 #
 # sway needs systemd, udev, EGL w/ Wayland backend and OpenGL ES support
 #
-
-#
-# sway needs a toolchain w/ wchar, threads, C++, dynamic library, gcc >= 4.9
-#
-
-#
-# tesseract-ocr needs a toolchain w/ threads, C++, gcc >= 7, dynamic library, wchar
-#
+# BR2_PACKAGE_TESSERACT_OCR is not set
 # BR2_PACKAGE_TINIFIER is not set
 
 #
 # Graphic libraries
 #
-
-#
-# cegui needs a toolchain w/ C++, threads, dynamic library, wchar, gcc >= 5
-#
-
-#
-# directfb needs a glibc or uClibc toolchain w/ C++, NPTL, gcc >= 4.5, dynamic library
-#
-
-#
-# efl needs a toolchain w/ C++, dynamic library, gcc >= 4.9, host gcc >= 4.9, threads, wchar
-#
+# BR2_PACKAGE_CEGUI is not set
+# BR2_PACKAGE_DIRECTFB is not set
 # BR2_PACKAGE_FB_TEST_APP is not set
 # BR2_PACKAGE_FBDUMP is not set
 # BR2_PACKAGE_FBGRAB is not set
-
-#
-# fbterm needs a toolchain w/ C++, wchar, locale
-#
+# BR2_PACKAGE_FBTERM is not set
 # BR2_PACKAGE_FBV is not set
-
-#
-# freerdp needs a toolchain w/ wchar, dynamic library, threads, C++
-#
+# BR2_PACKAGE_FREERDP is not set
 # BR2_PACKAGE_GRAPHICSMAGICK is not set
 # BR2_PACKAGE_IMAGEMAGICK is not set
 # BR2_PACKAGE_LIBGLVND is not set
 # BR2_PACKAGE_LINUX_FUSION is not set
+# BR2_PACKAGE_MESA3D is not set
+# BR2_PACKAGE_OCRAD is not set
 
 #
-# mesa3d needs a toolchain w/ gcc >=8, C++, NPTL, dynamic library
-#
-
-#
-# ocrad needs a toolchain w/ C++
-#
-
-#
-# ogre needs a toolchain w/ C++, dynamic library, gcc >= 4.8, threads, wchar
+# ogre needs X11 and an OpenGL provider
 #
 # BR2_PACKAGE_PSPLASH is not set
 # BR2_PACKAGE_SDL is not set
@@ -978,10 +849,7 @@ BR2_PACKAGE_NETSURF_ARCH_SUPPORTS=y
 #
 # Other GUIs
 #
-
-#
-# Qt5 needs host g++ >= 5.0, and a toolchain w/ gcc >= 5.0, wchar, NPTL, C++, dynamic library
-#
+# BR2_PACKAGE_QT5 is not set
 
 #
 # tekui needs a Lua interpreter and a toolchain w/ threads, dynamic library
@@ -991,18 +859,7 @@ BR2_PACKAGE_NETSURF_ARCH_SUPPORTS=y
 # weston needs udev and a toolchain w/ locale, threads, dynamic library, headers >= 3.0
 #
 # BR2_PACKAGE_XORG7 is not set
-
-#
-# apitrace needs a toolchain w/ C++, wchar, dynamic library, threads, gcc >= 7
-#
-
-#
-# mupdf needs a toolchain w/ C++, gcc >= 4.9
-#
-
-#
-# vte needs a uClibc or glibc toolchain w/ wchar, threads, C++, gcc >= 10
-#
+# BR2_PACKAGE_APITRACE is not set
 
 #
 # vte needs an OpenGL or an OpenGL-EGL/wayland backend
@@ -1032,16 +889,10 @@ BR2_PACKAGE_NETSURF_ARCH_SUPPORTS=y
 # BR2_PACKAGE_18XX_TI_UTILS is not set
 # BR2_PACKAGE_ACPICA is not set
 # BR2_PACKAGE_ACPID is not set
-
-#
-# acpitool needs a toolchain w/ threads, C++, dynamic library
-#
+# BR2_PACKAGE_ACPITOOL is not set
 # BR2_PACKAGE_AER_INJECT is not set
 # BR2_PACKAGE_ALTERA_STAPL is not set
-
-#
-# apcupsd needs a toolchain w/ C++, threads
-#
+# BR2_PACKAGE_APCUPSD is not set
 # BR2_PACKAGE_AVRDUDE is not set
 
 #
@@ -1052,10 +903,7 @@ BR2_PACKAGE_NETSURF_ARCH_SUPPORTS=y
 # brickd needs udev /dev management, a toolchain w/ threads, wchar
 #
 # BR2_PACKAGE_BRLTTY is not set
-
-#
-# cc-tool needs a toolchain w/ C++, threads, wchar, gcc >= 4.9 
-#
+# BR2_PACKAGE_CC_TOOL is not set
 # BR2_PACKAGE_CDRKIT is not set
 # BR2_PACKAGE_CRUCIBLE is not set
 # BR2_PACKAGE_CRYPTSETUP is not set
@@ -1067,10 +915,7 @@ BR2_PACKAGE_NETSURF_ARCH_SUPPORTS=y
 #
 # dbusbroker needs systemd and a toolchain w/ threads
 #
-
-#
-# dbus-cxx needs a toolchain w/ C++, threads, gcc >= 7 and dynamic library support
-#
+# BR2_PACKAGE_DBUS_CXX is not set
 # BR2_PACKAGE_DFU_UTIL is not set
 # BR2_PACKAGE_DMRAID is not set
 
@@ -1082,10 +927,7 @@ BR2_PACKAGE_NETSURF_ARCH_SUPPORTS=y
 # BR2_PACKAGE_DUMP1090 is not set
 # BR2_PACKAGE_DVB_APPS is not set
 # BR2_PACKAGE_DVBSNOOP is not set
-
-#
-# edid-decode needs a toolchain w/ C++, gcc >= 4.7
-#
+# BR2_PACKAGE_EDID_DECODE is not set
 
 #
 # eudev needs eudev /dev management
@@ -1097,15 +939,11 @@ BR2_PACKAGE_NETSURF_ARCH_SUPPORTS=y
 BR2_PACKAGE_FLASHROM_ARCH_SUPPORTS=y
 # BR2_PACKAGE_FLASHROM is not set
 # BR2_PACKAGE_FMTOOLS is not set
-BR2_PACKAGE_FPGA_AXI_SDC=y
 # BR2_PACKAGE_FREEIPMI is not set
 # BR2_PACKAGE_FXLOAD is not set
 # BR2_PACKAGE_GPM is not set
 # BR2_PACKAGE_GPSD is not set
-
-#
-# gptfdisk needs a toolchain w/ C++
-#
+# BR2_PACKAGE_GPTFDISK is not set
 # BR2_PACKAGE_GVFS is not set
 # BR2_PACKAGE_HDDTEMP is not set
 # BR2_PACKAGE_HWDATA is not set
@@ -1115,25 +953,16 @@ BR2_PACKAGE_FPGA_AXI_SDC=y
 # BR2_PACKAGE_IRDA_UTILS is not set
 # BR2_PACKAGE_KBD is not set
 # BR2_PACKAGE_LCDPROC is not set
-
-#
-# libiec61850 needs a toolchain w/ C++, threads, dynamic library
-#
+# BR2_PACKAGE_LIBIEC61850 is not set
 # BR2_PACKAGE_LIBMANETTE is not set
 # BR2_PACKAGE_LIBUBOOTENV is not set
 # BR2_PACKAGE_LIBUIO is not set
 # BR2_PACKAGE_LINUX_BACKPORTS is not set
 # BR2_PACKAGE_LINUX_SERIAL_TEST is not set
 # BR2_PACKAGE_LINUXCONSOLETOOLS is not set
-
-#
-# lirc-tools needs a toolchain w/ threads, dynamic library, C++
-#
+# BR2_PACKAGE_LIRC_TOOLS is not set
 # BR2_PACKAGE_LM_SENSORS is not set
-
-#
-# lshw needs a toolchain w/ C++, wchar
-#
+# BR2_PACKAGE_LSHW is not set
 # BR2_PACKAGE_LSSCSI is not set
 # BR2_PACKAGE_LSUIO is not set
 # BR2_PACKAGE_LUKSMETA is not set
@@ -1150,25 +979,16 @@ BR2_PACKAGE_FPGA_AXI_SDC=y
 # BR2_PACKAGE_NVIDIA_MODPROBE is not set
 # BR2_PACKAGE_NVME is not set
 # BR2_PACKAGE_OFONO is not set
-
-#
-# ola needs a toolchain w/ C++, threads, dynamic library, gcc >= 4.8
-#
+# BR2_PACKAGE_OLA is not set
 # BR2_PACKAGE_OPEN2300 is not set
-
-#
-# openfpgaloader needs a toolchain w/ threads, C++, gcc >= 4.9
-#
+# BR2_PACKAGE_OPENFPGALOADER is not set
 # BR2_PACKAGE_OPENIPMI is not set
 # BR2_PACKAGE_OPENOCD is not set
 # BR2_PACKAGE_PARTED is not set
 # BR2_PACKAGE_PCIUTILS is not set
 # BR2_PACKAGE_PDBG is not set
 # BR2_PACKAGE_PICOCOM is not set
-
-#
-# powertop needs a toolchain w/ C++, threads, wchar
-#
+# BR2_PACKAGE_POWERTOP is not set
 # BR2_PACKAGE_PPS_TOOLS is not set
 # BR2_PACKAGE_QORIQ_CADENCE_DP_FIRMWARE is not set
 # BR2_PACKAGE_RASPI_GPIO is not set
@@ -1193,10 +1013,7 @@ BR2_PACKAGE_FPGA_AXI_SDC=y
 # BR2_PACKAGE_SG3_UTILS is not set
 # BR2_PACKAGE_SIGROK_CLI is not set
 # BR2_PACKAGE_SISPMCTL is not set
-
-#
-# smartmontools needs a toolchain w/ C++
-#
+# BR2_PACKAGE_SMARTMONTOOLS is not set
 # BR2_PACKAGE_SMSTOOLS3 is not set
 # BR2_PACKAGE_SPI_TOOLS is not set
 # BR2_PACKAGE_SREDIRD is not set
@@ -1225,10 +1042,7 @@ BR2_PACKAGE_FPGA_AXI_SDC=y
 #
 # BR2_PACKAGE_USB_MODESWITCH is not set
 # BR2_PACKAGE_USB_MODESWITCH_DATA is not set
-
-#
-# usbguard needs a toolchain w/ C++, threads, dynamic library, gcc >= 8
-#
+# BR2_PACKAGE_USBGUARD is not set
 
 #
 # usbmount requires udev to be enabled
@@ -1283,21 +1097,12 @@ BR2_PACKAGE_PHP_ARCH_SUPPORTS=y
 # Audio/Sound
 #
 # BR2_PACKAGE_ALSA_LIB is not set
-
-#
-# alure needs a toolchain w/ C++, gcc >= 4.9, NPTL, wchar
-#
+# BR2_PACKAGE_ALURE is not set
 # BR2_PACKAGE_AUBIO is not set
 # BR2_PACKAGE_BCG729 is not set
-
-#
-# caps needs a toolchain w/ C++, dynamic library
-#
+# BR2_PACKAGE_CAPS is not set
 # BR2_PACKAGE_LIBAO is not set
-
-#
-# asplib needs a toolchain w/ C++
-#
+# BR2_PACKAGE_LIBASPLIB is not set
 # BR2_PACKAGE_LIBBROADVOICE is not set
 # BR2_PACKAGE_LIBCDAUDIO is not set
 # BR2_PACKAGE_LIBCDDB is not set
@@ -1313,41 +1118,23 @@ BR2_PACKAGE_PHP_ARCH_SUPPORTS=y
 # BR2_PACKAGE_LIBILBC is not set
 # BR2_PACKAGE_LIBLO is not set
 # BR2_PACKAGE_LIBMAD is not set
-
-#
-# libmodplug needs a toolchain w/ C++
-#
+# BR2_PACKAGE_LIBMODPLUG is not set
 # BR2_PACKAGE_LIBMPD is not set
 # BR2_PACKAGE_LIBMPDCLIENT is not set
 # BR2_PACKAGE_LIBREPLAYGAIN is not set
 # BR2_PACKAGE_LIBSAMPLERATE is not set
-
-#
-# libsidplay2 needs a toolchain w/ C++
-#
+# BR2_PACKAGE_LIBSIDPLAY2 is not set
 # BR2_PACKAGE_LIBSILK is not set
 # BR2_PACKAGE_LIBSNDFILE is not set
-
-#
-# libsoundtouch needs a toolchain w/ C++
-#
+# BR2_PACKAGE_LIBSOUNDTOUCH is not set
 # BR2_PACKAGE_LIBSOXR is not set
 # BR2_PACKAGE_LIBVORBIS is not set
 # BR2_PACKAGE_LILV is not set
 # BR2_PACKAGE_LV2 is not set
-
-#
-# mp4v2 needs a toolchain w/ C++
-#
+# BR2_PACKAGE_MP4V2 is not set
 BR2_PACKAGE_OPENAL_ARCH_SUPPORTS=y
-
-#
-# openal needs a toolchain w/ NPTL, C++, gcc >= 4.9
-#
-
-#
-# opencore-amr needs a toolchain w/ C++
-#
+# BR2_PACKAGE_OPENAL is not set
+# BR2_PACKAGE_OPENCORE_AMR is not set
 # BR2_PACKAGE_OPUS is not set
 # BR2_PACKAGE_OPUSFILE is not set
 # BR2_PACKAGE_PORTAUDIO is not set
@@ -1356,10 +1143,7 @@ BR2_PACKAGE_OPENAL_ARCH_SUPPORTS=y
 # BR2_PACKAGE_SPEEX is not set
 # BR2_PACKAGE_SPEEXDSP is not set
 # BR2_PACKAGE_SRATOM is not set
-
-#
-# taglib needs a toolchain w/ C++, wchar
-#
+# BR2_PACKAGE_TAGLIB is not set
 # BR2_PACKAGE_TINYALSA is not set
 # BR2_PACKAGE_TREMOR is not set
 # BR2_PACKAGE_VO_AACENC is not set
@@ -1370,19 +1154,13 @@ BR2_PACKAGE_OPENAL_ARCH_SUPPORTS=y
 # BR2_PACKAGE_LIBARCHIVE is not set
 # BR2_PACKAGE_LIBDEFLATE is not set
 # BR2_PACKAGE_LIBMSPACK is not set
-
-#
-# libsquish needs a toolchain w/ C++
-#
+# BR2_PACKAGE_LIBSQUISH is not set
 # BR2_PACKAGE_LIBZIP is not set
 # BR2_PACKAGE_LZ4 is not set
 # BR2_PACKAGE_LZO is not set
 # BR2_PACKAGE_MINIZIP is not set
 # BR2_PACKAGE_MINIZIP_ZLIB is not set
-
-#
-# snappy needs a toolchain w/ C++
-#
+# BR2_PACKAGE_SNAPPY is not set
 # BR2_PACKAGE_SZIP is not set
 # BR2_PACKAGE_ZCHUNK is not set
 BR2_PACKAGE_ZLIB_NG_ARCH_SUPPORTS=y
@@ -1396,16 +1174,10 @@ BR2_PACKAGE_PROVIDES_HOST_ZLIB="host-libzlib"
 # BR2_PACKAGE_BEARSSL is not set
 # BR2_PACKAGE_BEECRYPT is not set
 BR2_PACKAGE_BOTAN_ARCH_SUPPORTS=y
-
-#
-# botan needs a toolchain w/ C++, threads, gcc >= 4.8
-#
+# BR2_PACKAGE_BOTAN is not set
 # BR2_PACKAGE_CA_CERTIFICATES is not set
 # BR2_PACKAGE_CRYPTODEV is not set
-
-#
-# cryptopp needs a toolchain w/ C++, dynamic library, wchar
-#
+# BR2_PACKAGE_CRYPTOPP is not set
 # BR2_PACKAGE_GCR is not set
 # BR2_PACKAGE_GNUTLS is not set
 # BR2_PACKAGE_LIBARGON2 is not set
@@ -1421,10 +1193,7 @@ BR2_PACKAGE_LIBGPG_ERROR_SYSCFG="riscv64-unknown-linux-gnu"
 # BR2_PACKAGE_LIBMD is not set
 # BR2_PACKAGE_LIBMHASH is not set
 # BR2_PACKAGE_LIBNSS is not set
-
-#
-# libolm needs a toolchain w/ C++, gcc >= 4.8
-#
+# BR2_PACKAGE_LIBOLM is not set
 # BR2_PACKAGE_LIBP11 is not set
 # BR2_PACKAGE_LIBSCRYPT is not set
 # BR2_PACKAGE_LIBSECRET is not set
@@ -1456,26 +1225,14 @@ BR2_PACKAGE_WOLFSSL_ASM_SUPPORTS=y
 # BR2_PACKAGE_BERKELEYDB is not set
 # BR2_PACKAGE_GDBM is not set
 # BR2_PACKAGE_HIREDIS is not set
-
-#
-# kompexsqlite needs a toolchain w/ C++, wchar, threads, dynamic library
-#
-
-#
-# leveldb needs a toolchain w/ C++, threads, gcc >= 4.8
-#
+# BR2_PACKAGE_KOMPEXSQLITE is not set
+# BR2_PACKAGE_LEVELDB is not set
 # BR2_PACKAGE_LIBDBI is not set
 # BR2_PACKAGE_LIBDBI_DRIVERS is not set
 # BR2_PACKAGE_LIBGIT2 is not set
 # BR2_PACKAGE_LIBMDBX is not set
-
-#
-# libodb needs a toolchain w/ C++, threads
-#
-
-#
-# mysql needs a toolchain w/ C++, threads
-#
+# BR2_PACKAGE_LIBODB is not set
+# BR2_PACKAGE_MYSQL is not set
 # BR2_PACKAGE_POSTGRESQL is not set
 # BR2_PACKAGE_REDIS is not set
 # BR2_PACKAGE_SQLCIPHER is not set
@@ -1494,52 +1251,25 @@ BR2_PACKAGE_WOLFSSL_ASM_SUPPORTS=y
 # BR2_PACKAGE_LIBNFS is not set
 # BR2_PACKAGE_LIBSYSFS is not set
 # BR2_PACKAGE_LOCKDEV is not set
-
-#
-# physfs needs a toolchain w/ C++, threads
-#
+# BR2_PACKAGE_PHYSFS is not set
 
 #
 # Graphics
 #
-
-#
-# assimp needs a toolchain w/ C++, wchar, gcc >= 7
-#
+# BR2_PACKAGE_ASSIMP is not set
 # BR2_PACKAGE_AT_SPI2_CORE is not set
-
-#
-# atkmm needs a toolchain w/ C++, wchar, threads, gcc >= 7
-#
-
-#
-# atkmm (2.28.x) needs a toolchain w/ C++, wchar, threads, gcc >= 4.9
-#
-
-#
-# bullet needs a toolchain w/ C++, dynamic library, threads, wchar
-#
+# BR2_PACKAGE_ATKMM is not set
+# BR2_PACKAGE_ATKMM2_28 is not set
+# BR2_PACKAGE_BULLET is not set
 # BR2_PACKAGE_CAIRO is not set
-
-#
-# cairomm needs a toolchain w/ C++, wchar, threads, gcc >= 7
-#
-
-#
-# cairomm (1.14.x) needs a toolchain w/ C++, wchar, threads, gcc >= 4.9
-#
+# BR2_PACKAGE_CAIROMM is not set
+# BR2_PACKAGE_CAIROMM1_14 is not set
 
 #
 # chipmunk needs an OpenGL backend
 #
-
-#
-# exempi needs a toolchain w/ C++, dynamic library, threads, wchar
-#
-
-#
-# exiv2 needs a uClibc or glibc toolchain w/ C++, wchar, dynamic library, threads
-#
+# BR2_PACKAGE_EXEMPI is not set
+# BR2_PACKAGE_EXIV2 is not set
 # BR2_PACKAGE_FONTCONFIG is not set
 # BR2_PACKAGE_FREETYPE is not set
 # BR2_PACKAGE_GD is not set
@@ -1549,40 +1279,24 @@ BR2_PACKAGE_WOLFSSL_ASM_SUPPORTS=y
 #
 # granite needs libgtk3 and a toolchain w/ wchar, threads, gcc >= 4.9
 #
-
-#
-# graphite2 needs a toolchain w/ C++
-#
+# BR2_PACKAGE_GRAPHITE2 is not set
 
 #
 # gtkmm3 needs libgtk3 and a toolchain w/ C++, wchar, threads, gcc >= 4.9
 #
-
-#
-# harfbuzz needs a toolchain w/ C++, gcc >= 4.9
-#
+# BR2_PACKAGE_HARFBUZZ is not set
 # BR2_PACKAGE_IJS is not set
 # BR2_PACKAGE_IMLIB2 is not set
 
 #
-# intel-gmmlib needs a toolchain w/ dynamic library, C++, threads
-#
-
-#
-# irrlicht needs a toolchain w/ C++
+# irrlicht needs X11 and an OpenGL provider
 #
 # BR2_PACKAGE_JASPER is not set
 # BR2_PACKAGE_JBIG2DEC is not set
 # BR2_PACKAGE_JPEG is not set
-
-#
-# kms++ needs a toolchain w/ threads, C++, gcc >= 4.8, headers >= 4.11, wchar
-#
+# BR2_PACKAGE_KMSXX is not set
 # BR2_PACKAGE_LCMS2 is not set
-
-#
-# lensfun needs a toolchain w/ C++, threads, wchar
-#
+# BR2_PACKAGE_LENSFUN is not set
 # BR2_PACKAGE_LEPTONICA is not set
 # BR2_PACKAGE_LIBART is not set
 # BR2_PACKAGE_LIBDMTX is not set
@@ -1601,14 +1315,8 @@ BR2_PACKAGE_WOLFSSL_ASM_SUPPORTS=y
 #
 # libfreeglut depends on X.org and needs an OpenGL backend
 #
-
-#
-# libfreeimage needs a toolchain w/ C++, dynamic library, wchar
-#
-
-#
-# libgeotiff needs a toolchain w/ C++, gcc >= 4.7, threads, wchar
-#
+# BR2_PACKAGE_LIBFREEIMAGE is not set
+# BR2_PACKAGE_LIBGEOTIFF is not set
 
 #
 # libglew depends on X.org and needs an OpenGL backend
@@ -1623,64 +1331,33 @@ BR2_PACKAGE_WOLFSSL_ASM_SUPPORTS=y
 #
 # BR2_PACKAGE_LIBGTA is not set
 
-#
-# libgtk3 needs a toolchain w/ wchar, threads, C++, gcc >= 4.9
-#
-
 #
 # libgtk3 needs an OpenGL or an OpenGL-EGL/wayland backend
 #
-
-#
-# libjxl needs a toolchain with C++, threads, gcc >= 7, dynamic library
-#
+# BR2_PACKAGE_LIBJXL is not set
 # BR2_PACKAGE_LIBMEDIAART is not set
 # BR2_PACKAGE_LIBMNG is not set
 # BR2_PACKAGE_LIBPNG is not set
 # BR2_PACKAGE_LIBQRENCODE is not set
-
-#
-# libraw needs a toolchain w/ C++
-#
+# BR2_PACKAGE_LIBRAW is not set
 # BR2_PACKAGE_LIBSVG is not set
 # BR2_PACKAGE_LIBSVG_CAIRO is not set
 # BR2_PACKAGE_LIBSVGTINY is not set
 # BR2_PACKAGE_LIBVA is not set
-
-#
-# libvips needs a toolchain w/ wchar, threads, C++
-#
+# BR2_PACKAGE_LIBVIPS is not set
 
 #
 # libwpe needs a toolchain w/ C++, dynamic library and an OpenEGL-capable backend
 #
 # BR2_PACKAGE_MENU_CACHE is not set
-
-#
-# opencv3 needs a toolchain w/ C++, NPTL, wchar, dynamic library
-#
-
-#
-# opencv4 needs a toolchain w/ C++, NPTL, wchar, dynamic library, gcc >= 4.8
-#
+# BR2_PACKAGE_OPENCV3 is not set
+# BR2_PACKAGE_OPENCV4 is not set
 # BR2_PACKAGE_OPENJPEG is not set
-
-#
-# pango needs a toolchain w/ wchar, threads, C++, gcc >= 4.9
-#
-
-#
-# pangomm needs a toolchain w/ C++, wchar, threads, gcc >= 7
-#
-
-#
-# pangomm (2.46.x) needs a toolchain w/ C++, wchar, threads, gcc >= 4.9
-#
+# BR2_PACKAGE_PANGO is not set
+# BR2_PACKAGE_PANGOMM is not set
+# BR2_PACKAGE_PANGOMM2_46 is not set
 # BR2_PACKAGE_PIXMAN is not set
-
-#
-# poppler needs a toolchain w/ wchar, C++, threads, dynamic library, gcc >= 7
-#
+# BR2_PACKAGE_POPPLER is not set
 # BR2_PACKAGE_STB is not set
 # BR2_PACKAGE_TIFF is not set
 # BR2_PACKAGE_WAYLAND is not set
@@ -1694,31 +1371,18 @@ BR2_PACKAGE_WEBKITGTK_ARCH_SUPPORTS=y
 #
 # wlroots needs udev, EGL w/ Wayland backend and OpenGL ES support
 #
-
-#
-# woff2 needs a toolchain w/ C++
-#
+# BR2_PACKAGE_WOFF2 is not set
 
 #
 # wpebackend-fdo needs a toolchain w/ C++, wchar, threads, dynamic library and an OpenEGL-capable Wayland backend
 #
 BR2_PACKAGE_WPEWEBKIT_ARCH_SUPPORTS=y
 
-#
-# wpewebkit needs a toolchain w/ C++, wchar, threads, dynamic library, gcc >= 7, host gcc >= 4.9
-#
-
 #
 # wpewebkit needs an OpenGL ES w/ EGL-capable Wayland backend
 #
-
-#
-# zbar needs a toolchain w/ threads, C++ and headers >= 3.0
-#
-
-#
-# zxing-cpp needs a toolchain w/ C++, wchar, dynamic library
-#
+# BR2_PACKAGE_ZBAR is not set
+# BR2_PACKAGE_ZXING_CPP is not set
 
 #
 # Hardware handling
@@ -1733,14 +1397,8 @@ BR2_PACKAGE_WPEWEBKIT_ARCH_SUPPORTS=y
 # hidapi needs udev /dev management and a toolchain w/ NPTL, threads, gcc >= 4.9
 #
 # BR2_PACKAGE_JITTERENTROPY_LIBRARY is not set
-
-#
-# lcdapi needs a toolchain w/ C++, threads
-#
-
-#
-# let-me-create needs a toolchain w/ C++, threads, dynamic library
-#
+# BR2_PACKAGE_LCDAPI is not set
+# BR2_PACKAGE_LET_ME_CREATE is not set
 # BR2_PACKAGE_LIBAIO is not set
 
 #
@@ -1750,10 +1408,7 @@ BR2_PACKAGE_WPEWEBKIT_ARCH_SUPPORTS=y
 #
 # libblockdev needs udev /dev management and a toolchain w/ wchar, threads, dynamic library, locale
 #
-
-#
-# libcec needs a toolchain w/ C++, wchar, threads, dynamic library, gcc >= 4.7
-#
+# BR2_PACKAGE_LIBCEC is not set
 # BR2_PACKAGE_LIBFREEFARE is not set
 # BR2_PACKAGE_LIBFTDI is not set
 # BR2_PACKAGE_LIBFTDI1 is not set
@@ -1780,10 +1435,7 @@ BR2_PACKAGE_WPEWEBKIT_ARCH_SUPPORTS=y
 # BR2_PACKAGE_LIBQRTR_GLIB is not set
 # BR2_PACKAGE_LIBRAW1394 is not set
 # BR2_PACKAGE_LIBRTLSDR is not set
-
-#
-# libserial needs a toolchain w/ C++, gcc >= 5, threads, wchar
-#
+# BR2_PACKAGE_LIBSERIAL is not set
 # BR2_PACKAGE_LIBSERIALPORT is not set
 # BR2_PACKAGE_LIBSIGROK is not set
 # BR2_PACKAGE_LIBSIGROKDECODE is not set
@@ -1791,10 +1443,7 @@ BR2_PACKAGE_WPEWEBKIT_ARCH_SUPPORTS=y
 # BR2_PACKAGE_LIBSS7 is not set
 # BR2_PACKAGE_LIBUSB is not set
 # BR2_PACKAGE_LIBUSBGX is not set
-
-#
-# libv4l needs a toolchain w/ threads, C++ and headers >= 3.0
-#
+# BR2_PACKAGE_LIBV4L is not set
 # BR2_PACKAGE_LIBXKBCOMMON is not set
 # BR2_PACKAGE_MTDEV is not set
 # BR2_PACKAGE_NEARDAL is not set
@@ -1802,14 +1451,8 @@ BR2_PACKAGE_WPEWEBKIT_ARCH_SUPPORTS=y
 # BR2_PACKAGE_OWFS is not set
 # BR2_PACKAGE_PCSC_LITE is not set
 # BR2_PACKAGE_TSLIB is not set
-
-#
-# uhd needs a toolchain w/ C++, NPTL, wchar, dynamic library, gcc >= 5
-#
-
-#
-# urg needs a toolchain w/ C++
-#
+# BR2_PACKAGE_UHD is not set
+# BR2_PACKAGE_URG is not set
 
 #
 # Javascript
@@ -1834,170 +1477,83 @@ BR2_PACKAGE_WPEWEBKIT_ARCH_SUPPORTS=y
 #
 # JSON/XML
 #
-
-#
-# benejson needs a toolchain w/ C++
-#
+# BR2_PACKAGE_BENEJSON is not set
 # BR2_PACKAGE_CJSON is not set
 # BR2_PACKAGE_EXPAT is not set
 # BR2_PACKAGE_JANSSON is not set
 # BR2_PACKAGE_JOSE is not set
 # BR2_PACKAGE_JSMN is not set
 # BR2_PACKAGE_JSON_C is not set
-
-#
-# json-for-modern-cpp needs a toolchain w/ C++, gcc >= 4.9
-#
+# BR2_PACKAGE_JSON_FOR_MODERN_CPP is not set
 # BR2_PACKAGE_JSON_GLIB is not set
-
-#
-# jsoncpp needs a toolchain w/ C++, gcc >= 4.7
-#
+# BR2_PACKAGE_JSONCPP is not set
 # BR2_PACKAGE_LIBBSON is not set
 # BR2_PACKAGE_LIBFASTJSON is not set
-
-#
-# libjson needs a toolchain w/ C++
-#
+# BR2_PACKAGE_LIBJSON is not set
 # BR2_PACKAGE_LIBROXML is not set
 # BR2_PACKAGE_LIBUCL is not set
 # BR2_PACKAGE_LIBXML2 is not set
-
-#
-# libxml++ needs a toolchain w/ C++, wchar, threads, gcc >= 7
-#
+# BR2_PACKAGE_LIBXMLPP is not set
 # BR2_PACKAGE_LIBXMLRPC is not set
 # BR2_PACKAGE_LIBXSLT is not set
 # BR2_PACKAGE_LIBYAML is not set
 # BR2_PACKAGE_MXML is not set
-
-#
-# pugixml needs a toolchain w/ C++
-#
-
-#
-# rapidjson needs a toolchain w/ C++
-#
+# BR2_PACKAGE_PUGIXML is not set
+# BR2_PACKAGE_RAPIDJSON is not set
 # BR2_PACKAGE_RAPIDXML is not set
 # BR2_PACKAGE_RAPTOR is not set
 # BR2_PACKAGE_SERD is not set
 # BR2_PACKAGE_SORD is not set
-
-#
-# tinyxml needs a toolchain w/ C++
-#
-
-#
-# tinyxml2 needs a toolchain w/ C++
-#
-
-#
-# valijson needs a toolchain w/ C++
-#
-
-#
-# xerces-c++ needs a toolchain w/ C++, dynamic library, wchar
-#
-
-#
-# xml-security-c needs a toolchain w/ C++, wchar, dynamic library, threads, gcc >= 4.7
-#
+# BR2_PACKAGE_TINYXML is not set
+# BR2_PACKAGE_TINYXML2 is not set
+# BR2_PACKAGE_VALIJSON is not set
+# BR2_PACKAGE_XERCES is not set
+# BR2_PACKAGE_XML_SECURITY_C is not set
 # BR2_PACKAGE_YAJL is not set
-
-#
-# yaml-cpp needs a toolchain w/ C++, gcc >= 4.7
-#
+# BR2_PACKAGE_YAML_CPP is not set
 
 #
 # Logging
 #
-
-#
-# glog needs a toolchain w/ C++
-#
-
-#
-# hawktracer needs a toolchain w/ C++, gcc >= 4.8
-#
+# BR2_PACKAGE_GLOG is not set
+# BR2_PACKAGE_HAWKTRACER is not set
 # BR2_PACKAGE_LIBLOG4C_LOCALTIME is not set
 # BR2_PACKAGE_LIBLOGGING is not set
-
-#
-# log4cplus needs a toolchain w/ C++, wchar, threads, gcc >= 4.8
-#
-
-#
-# log4cpp needs a toolchain w/ C++, threads
-#
-
-#
-# log4cxx needs a toolchain w/ C++, threads, dynamic library
-#
+# BR2_PACKAGE_LOG4CPLUS is not set
+# BR2_PACKAGE_LOG4CPP is not set
+# BR2_PACKAGE_LOG4CXX is not set
 
 #
 # log4qt needs qt5
 #
-
-#
-# opentracing-cpp needs a toolchain w/ C++, threads, dynamic library, gcc >= 4.8
-#
-
-#
-# spdlog needs a toolchain w/ C++, threads, wchar
-#
-
-#
-# ulog needs a toolchain w/ C++, threads
-#
+# BR2_PACKAGE_OPENTRACING_CPP is not set
+# BR2_PACKAGE_SPDLOG is not set
+# BR2_PACKAGE_ULOG is not set
 # BR2_PACKAGE_ZLOG is not set
 
 #
 # Multimedia
 #
-
-#
-# bento4 support needs a toolchain with C++
-#
+# BR2_PACKAGE_BENTO4 is not set
 # BR2_PACKAGE_BITSTREAM is not set
 # BR2_PACKAGE_DAV1D is not set
-
-#
-# kvazaar needs a toolchain w/ C++, threads
-#
+# BR2_PACKAGE_KVAZAAR is not set
 # BR2_PACKAGE_LIBAACS is not set
-
-#
-# libass needs a toolchain w/ C++, gcc >= 4.9
-#
+# BR2_PACKAGE_LIBASS is not set
 # BR2_PACKAGE_LIBBDPLUS is not set
 # BR2_PACKAGE_LIBBLURAY is not set
 BR2_PACKAGE_LIBCAMERA_ARCH_SUPPORTS=y
-
-#
-# libcamera needs a toolchain w/ C++, threads, wchar, dynamic library, gcc >= 8
-#
-
-#
-# libcamera-apps needs a toolchain w/ C++, threads, wchar, dynamic library, gcc >= 8
-#
+# BR2_PACKAGE_LIBCAMERA is not set
+# BR2_PACKAGE_LIBCAMERA_APPS is not set
 # BR2_PACKAGE_LIBDVBCSA is not set
 # BR2_PACKAGE_LIBDVBPSI is not set
-
-#
-# libdvbsi++ needs a toolchain w/ C++, wchar, threads
-#
+# BR2_PACKAGE_LIBDVBSI is not set
 # BR2_PACKAGE_LIBDVDCSS is not set
 # BR2_PACKAGE_LIBDVDNAV is not set
 # BR2_PACKAGE_LIBDVDREAD is not set
-
-#
-# libebml needs a toolchain w/ C++, wchar
-#
+# BR2_PACKAGE_LIBEBML is not set
 # BR2_PACKAGE_LIBHDHOMERUN is not set
-
-#
-# libmatroska needs a toolchain w/ C++, wchar
-#
+# BR2_PACKAGE_LIBMATROSKA is not set
 # BR2_PACKAGE_LIBMMS is not set
 # BR2_PACKAGE_LIBMPEG2 is not set
 # BR2_PACKAGE_LIBOGG is not set
@@ -2006,99 +1562,48 @@ BR2_PACKAGE_LIBCAMERA_ARCH_SUPPORTS=y
 # BR2_PACKAGE_LIBTHEORA is not set
 # BR2_PACKAGE_LIBUDFREAD is not set
 # BR2_PACKAGE_LIBVPX is not set
-
-#
-# libyuv needs a toolchain w/ C++, dynamic library
-#
-
-#
-# live555 needs a toolchain w/ C++
-#
-
-#
-# mediastreamer needs a toolchain w/ threads, C++, dynamic library, gcc >= 5
-#
+# BR2_PACKAGE_LIBYUV is not set
+# BR2_PACKAGE_LIVE555 is not set
+# BR2_PACKAGE_MEDIASTREAMER is not set
 # BR2_PACKAGE_X264 is not set
-
-#
-# x265 needs a toolchain w/ C++, threads, dynamic library
-#
+# BR2_PACKAGE_X265 is not set
 
 #
 # Networking
 #
-
-#
-# agent++ needs a toolchain w/ threads, C++, dynamic library
-#
-
-#
-# azmq needs a toolchain w/ C++11, wchar and threads
-#
-
-#
-# azure-iot-sdk-c needs a toolchain w/ C++, NPTL and wchar
-#
+# BR2_PACKAGE_AGENTPP is not set
+# BR2_PACKAGE_AZMQ is not set
+# BR2_PACKAGE_AZURE_IOT_SDK_C is not set
 # BR2_PACKAGE_BATMAN_ADV is not set
-
-#
-# belle-sip needs a toolchain w/ threads, C++, dynamic library, wchar
-#
+# BR2_PACKAGE_BELLE_SIP is not set
 # BR2_PACKAGE_C_ARES is not set
 # BR2_PACKAGE_CGIC is not set
 # BR2_PACKAGE_CNI_PLUGINS is not set
-
-#
-# cppzmq needs a toolchain w/ C++, threads
-#
-
-#
-# curlpp needs a toolchain w/ C++, dynamic library
-#
-
-#
-# czmq needs a toolchain w/ C++, threads
-#
+# BR2_PACKAGE_CPPZMQ is not set
+# BR2_PACKAGE_CURLPP is not set
+# BR2_PACKAGE_CZMQ is not set
 # BR2_PACKAGE_DAQ is not set
 # BR2_PACKAGE_DAQ3 is not set
 # BR2_PACKAGE_DAVICI is not set
 # BR2_PACKAGE_DHT is not set
 # BR2_PACKAGE_ENET is not set
-
-#
-# filemq needs a toolchain w/ C++, threads
-#
+# BR2_PACKAGE_FILEMQ is not set
 # BR2_PACKAGE_FLICKCURL is not set
 # BR2_PACKAGE_FREERADIUS_CLIENT is not set
 # BR2_PACKAGE_GENSIO is not set
 # BR2_PACKAGE_GEOIP is not set
 # BR2_PACKAGE_GLIB_NETWORKING is not set
-
-#
-# grpc needs a toolchain w/ C++, threads, dynamic library, gcc >= 5
-#
+# BR2_PACKAGE_GRPC is not set
 # BR2_PACKAGE_GSSDP is not set
 # BR2_PACKAGE_GUPNP is not set
 # BR2_PACKAGE_GUPNP_AV is not set
 # BR2_PACKAGE_GUPNP_DLNA is not set
-
-#
-# ibrcommon needs a toolchain w/ C++, threads
-#
-
-#
-# ibrdtn needs a toolchain w/ C++, threads
-#
+# BR2_PACKAGE_IBRCOMMON is not set
+# BR2_PACKAGE_IBRDTN is not set
 # BR2_PACKAGE_LIBCGI is not set
-
-#
-# libcgicc needs a toolchain w/ C++
-#
+# BR2_PACKAGE_LIBCGICC is not set
 # BR2_PACKAGE_LIBCOAP is not set
-
-#
-# libcpprestsdk needs a toolchain w/ NPTL, C++, wchar, locale
-#
+# BR2_PACKAGE_LIBCPPRESTSDK is not set
 # BR2_PACKAGE_LIBCURL is not set
 # BR2_PACKAGE_LIBDNET is not set
 # BR2_PACKAGE_LIBEXOSIP2 is not set
@@ -2107,10 +1612,7 @@ BR2_PACKAGE_LIBCAMERA_ARCH_SUPPORTS=y
 # BR2_PACKAGE_LIBGSASL is not set
 # BR2_PACKAGE_LIBHTP is not set
 # BR2_PACKAGE_LIBHTTPPARSER is not set
-
-#
-# libhttpserver needs a toolchain w/ C++, threads, gcc >= 5
-#
+# BR2_PACKAGE_LIBHTTPSERVER is not set
 # BR2_PACKAGE_LIBIDN is not set
 # BR2_PACKAGE_LIBIDN2 is not set
 # BR2_PACKAGE_LIBISCSI is not set
@@ -2118,18 +1620,12 @@ BR2_PACKAGE_LIBCAMERA_ARCH_SUPPORTS=y
 # BR2_PACKAGE_LIBLDNS is not set
 # BR2_PACKAGE_LIBMAXMINDDB is not set
 # BR2_PACKAGE_LIBMBUS is not set
-
-#
-# libmemcached needs a toolchain w/ C++, threads
-#
+# BR2_PACKAGE_LIBMEMCACHED is not set
 # BR2_PACKAGE_LIBMICROHTTPD is not set
 # BR2_PACKAGE_LIBMINIUPNPC is not set
 # BR2_PACKAGE_LIBMNL is not set
 # BR2_PACKAGE_LIBMODBUS is not set
-
-#
-# libmodsecurity needs a toolchain w/ C++, threads, dynamic library
-#
+# BR2_PACKAGE_LIBMODSECURITY is not set
 # BR2_PACKAGE_LIBNATPMP is not set
 # BR2_PACKAGE_LIBNDP is not set
 # BR2_PACKAGE_LIBNET is not set
@@ -2145,19 +1641,13 @@ BR2_PACKAGE_LIBCAMERA_ARCH_SUPPORTS=y
 # BR2_PACKAGE_LIBNICE is not set
 # BR2_PACKAGE_LIBNIDS is not set
 # BR2_PACKAGE_LIBNL is not set
-
-#
-# libnpupnp needs a toolchain w/ C++, threads, gcc >= 4.9
-#
+# BR2_PACKAGE_LIBNPUPNP is not set
 # BR2_PACKAGE_LIBOAUTH is not set
 # BR2_PACKAGE_LIBOPING is not set
 # BR2_PACKAGE_LIBOSIP2 is not set
 # BR2_PACKAGE_LIBPAGEKITE is not set
 # BR2_PACKAGE_LIBPCAP is not set
-
-#
-# libpjsip needs a toolchain w/ C++, threads
-#
+# BR2_PACKAGE_LIBPJSIP is not set
 # BR2_PACKAGE_LIBPSL is not set
 # BR2_PACKAGE_LIBRELP is not set
 # BR2_PACKAGE_LIBRSYNC is not set
@@ -2170,30 +1660,14 @@ BR2_PACKAGE_LIBCAMERA_ARCH_SUPPORTS=y
 # BR2_PACKAGE_LIBTEAM is not set
 # BR2_PACKAGE_LIBTELNET is not set
 # BR2_PACKAGE_LIBTIRPC is not set
-
-#
-# libtorrent needs a toolchain w/ C++, threads
-#
-
-#
-# libtorrent-rasterbar needs a toolchain w/ C++, threads, wchar, gcc >= 4.9
-#
+# BR2_PACKAGE_LIBTORRENT is not set
+# BR2_PACKAGE_LIBTORRENT_RASTERBAR is not set
 # BR2_PACKAGE_LIBUEV is not set
 # BR2_PACKAGE_LIBUHTTPD is not set
-
-#
-# libuhttpd needs a toolchain w/ gcc >= 4.9
-#
 # BR2_PACKAGE_LIBUPNP is not set
-
-#
-# libupnpp needs a toolchain w/ C++, threads, gcc >= 4.9
-#
+# BR2_PACKAGE_LIBUPNPP is not set
 # BR2_PACKAGE_LIBURIPARSER is not set
-
-#
-# libutp support needs a toolchain with C++
-#
+# BR2_PACKAGE_LIBUTP is not set
 # BR2_PACKAGE_LIBUWSC is not set
 # BR2_PACKAGE_LIBVNCSERVER is not set
 # BR2_PACKAGE_LIBWEBSOCK is not set
@@ -2204,213 +1678,87 @@ BR2_PACKAGE_LIBCAMERA_ARCH_SUPPORTS=y
 # BR2_PACKAGE_MONGOOSE is not set
 # BR2_PACKAGE_NANOMSG is not set
 # BR2_PACKAGE_NEON is not set
-
-#
-# netopeer2 needs a toolchain w/ gcc >= 4.8, C++, threads, dynamic library
-#
+# BR2_PACKAGE_NETOPEER2 is not set
 # BR2_PACKAGE_NGHTTP2 is not set
-
-#
-# norm needs a toolchain w/ C++, threads, dynamic library
-#
+# BR2_PACKAGE_NORM is not set
 # BR2_PACKAGE_NSS_MYHOSTNAME is not set
 # BR2_PACKAGE_NSS_PAM_LDAPD is not set
-
-#
-# omniORB needs a toolchain w/ C++, threads
-#
+# BR2_PACKAGE_OMNIORB is not set
 # BR2_PACKAGE_OPEN_ISNS is not set
 # BR2_PACKAGE_OPEN62541 is not set
 # BR2_PACKAGE_OPENLDAP is not set
-
-#
-# openmpi needs a toolchain w/ dynamic library, NPTL, wchar, C++
-#
+# BR2_PACKAGE_OPENMPI is not set
 # BR2_PACKAGE_OPENPGM is not set
-
-#
-# openzwave needs a toolchain w/ C++, dynamic library, NPTL, wchar
-#
-
-#
-# ortp needs a toolchain w/ C++, threads
-#
+# BR2_PACKAGE_OPENZWAVE is not set
+# BR2_PACKAGE_ORTP is not set
 # BR2_PACKAGE_PAHO_MQTT_C is not set
-
-#
-# paho-mqtt-cpp needs a toolchain w/ threads, C++
-#
-
-#
-# pistache needs a toolchain w/ C++, gcc >= 7, threads, wchar, not binutils bug 27597
-#
+# BR2_PACKAGE_PAHO_MQTT_CPP is not set
+# BR2_PACKAGE_PISTACHE is not set
 # BR2_PACKAGE_QDECODER is not set
-
-#
-# qpid-proton needs a toolchain w/ C++, dynamic library, threads
-#
+# BR2_PACKAGE_QPID_PROTON is not set
 # BR2_PACKAGE_RABBITMQ_C is not set
-
-#
-# resiprocate needs a toolchain w/ C++, threads, wchar
-#
-
-#
-# restclient-cpp needs a toolchain w/ C++, gcc >= 4.8
-#
+# BR2_PACKAGE_RESIPROCATE is not set
+# BR2_PACKAGE_RESTCLIENT_CPP is not set
 # BR2_PACKAGE_RTMPDUMP is not set
 # BR2_PACKAGE_SIPROXD is not set
 # BR2_PACKAGE_SLIRP is not set
 # BR2_PACKAGE_SLIRP4NETNS is not set
-
-#
-# snmp++ needs a toolchain w/ threads, C++, dynamic library
-#
+# BR2_PACKAGE_SNMPPP is not set
 # BR2_PACKAGE_SOFIA_SIP is not set
 # BR2_PACKAGE_SSCEP is not set
-
-#
-# sysrepo needs a toolchain w/ C++, NPTL, dynamic library, gcc >= 4.8
-#
-
-#
-# thrift needs a toolchain w/ C++, wchar, threads
-#
+# BR2_PACKAGE_SYSREPO is not set
+# BR2_PACKAGE_THRIFT is not set
 # BR2_PACKAGE_USBREDIR is not set
-
-#
-# wampcc needs a toolchain w/ C++, NPTL, dynamic library
-#
-
-#
-# websocketpp needs a toolchain w/ C++ and gcc >= 4.8
-#
-
-#
-# zeromq needs a toolchain w/ C++, threads
-#
-
-#
-# zmqpp needs a toolchain w/ C++, threads, gcc >= 4.7
-#
-
-#
-# zyre needs a toolchain w/ C++, threads
-#
+# BR2_PACKAGE_WAMPCC is not set
+# BR2_PACKAGE_WEBSOCKETPP is not set
+# BR2_PACKAGE_ZEROMQ is not set
+# BR2_PACKAGE_ZMQPP is not set
+# BR2_PACKAGE_ZYRE is not set
 
 #
 # Other
 #
-
-#
-# ACE needs a glibc toolchain, dynamic library, C++, gcc >= 4.8
-#
+# BR2_PACKAGE_ACE is not set
 # BR2_PACKAGE_APR is not set
 # BR2_PACKAGE_APR_UTIL is not set
 
 #
 # armadillo needs a toolchain w/ fortran, C++
 #
-
-#
-# atf needs a toolchain w/ C++
-#
+# BR2_PACKAGE_ATF is not set
 # BR2_PACKAGE_AVRO_C is not set
-
-#
-# bctoolbox needs a toolchain w/ C++, threads
-#
+# BR2_PACKAGE_BCTOOLBOX is not set
 # BR2_PACKAGE_BDWGC is not set
-
-#
-# belr needs a toolchain w/ threads, C++
-#
-
-#
-# boost needs a toolchain w/ C++, threads, wchar
-#
-
-#
-# c-capnproto needs host and target gcc >= 5 w/ C++14, threads, atomic, ucontext and not gcc bug 64735
-#
-
-#
-# capnproto needs host and target gcc >= 5 w/ C++14, threads, atomic, ucontext and not gcc bug 64735
-#
-
-#
-# catch2 needs a toolchain w/ C++, wchar, threads, gcc >= 5
-#
-
-#
-# cctz needs a toolchain w/ C++, threads, gcc >= 4.8
-#
-
-#
-# cereal needs a toolchain w/ C++, gcc >= 4.7, threads, wchar
-#
-
-#
-# clang needs a toolchain w/ wchar, threads, C++, gcc >= 5, dynamic library, host gcc >= 5
-#
+# BR2_PACKAGE_BELR is not set
+# BR2_PACKAGE_BOOST is not set
+# BR2_PACKAGE_C_CAPNPROTO is not set
+# BR2_PACKAGE_CAPNPROTO is not set
+# BR2_PACKAGE_CATCH2 is not set
+# BR2_PACKAGE_CCTZ is not set
+# BR2_PACKAGE_CEREAL is not set
+# BR2_PACKAGE_CLANG is not set
 # BR2_PACKAGE_CMOCKA is not set
-
-#
-# cppcms needs a toolchain w/ C++, NPTL, wchar, dynamic library
-#
+# BR2_PACKAGE_CPPCMS is not set
 # BR2_PACKAGE_CRACKLIB is not set
-
-#
-# dawgdic needs a toolchain w/ C++, gcc >= 4.6
-#
+# BR2_PACKAGE_DAWGDIC is not set
 # BR2_PACKAGE_DING_LIBS is not set
 # BR2_PACKAGE_DOTCONF is not set
-
-#
-# double-conversion needs a toolchain w/ C++
-#
-
-#
-# eigen needs a toolchain w/ C++
-#
+# BR2_PACKAGE_DOUBLE_CONVERSION is not set
+# BR2_PACKAGE_EIGEN is not set
 # BR2_PACKAGE_ELFUTILS is not set
 # BR2_PACKAGE_ELL is not set
 # BR2_PACKAGE_FFTW is not set
-
-#
-# flann needs a toolchain w/ C++, dynamic library, gcc >= 4.7
-#
-
-#
-# flatbuffers needs a toolchain w/ C++, gcc >= 4.7
-#
+# BR2_PACKAGE_FLANN is not set
+# BR2_PACKAGE_FLATBUFFERS is not set
 # BR2_PACKAGE_FLATCC is not set
 # BR2_PACKAGE_FXDIV is not set
 # BR2_PACKAGE_GCONF is not set
-
-#
-# gdal needs a toolchain w/ C++, dynamic library, gcc >= 4.7, not binutils bug 27597, threads, wchar
-#
-
-#
-# gflags needs a toolchain w/ C++
-#
-
-#
-# gli needs a toolchain w/ C++
-#
-
-#
-# glibmm needs a toolchain w/ C++, wchar, threads, gcc >= 7
-#
-
-#
-# glibmm (2.66.x) needs a toolchain w/ C++, wchar, threads, gcc >= 4.9
-#
-
-#
-# glm needs a toolchain w/ C++
-#
+# BR2_PACKAGE_GDAL is not set
+# BR2_PACKAGE_GFLAGS is not set
+# BR2_PACKAGE_GLI is not set
+# BR2_PACKAGE_GLIBMM is not set
+# BR2_PACKAGE_GLIBMM2_66 is not set
+# BR2_PACKAGE_GLM is not set
 # BR2_PACKAGE_GMP is not set
 BR2_PACKAGE_GOBJECT_INTROSPECTION_ARCH_SUPPORTS=y
 
@@ -2418,15 +1766,9 @@ BR2_PACKAGE_GOBJECT_INTROSPECTION_ARCH_SUPPORTS=y
 # gobject-introspection needs python3
 #
 # BR2_PACKAGE_GSL is not set
-
-#
-# gtest needs a toolchain w/ C++, wchar, threads, gcc >= 5
-#
+# BR2_PACKAGE_GTEST is not set
 # BR2_PACKAGE_GUMBO_PARSER is not set
-
-#
-# highway needs a toolchain w/ C++, gcc >= 7
-#
+# BR2_PACKAGE_HIGHWAY is not set
 BR2_PACKAGE_JEMALLOC_ARCH_SUPPORTS=y
 # BR2_PACKAGE_JEMALLOC is not set
 BR2_PACKAGE_LAPACK_ARCH_SUPPORTS=y
@@ -2435,10 +1777,7 @@ BR2_PACKAGE_LAPACK_ARCH_SUPPORTS=y
 # lapack/blas needs a toolchain w/ fortran
 #
 BR2_PACKAGE_LIBABSEIL_CPP_ARCH_SUPPORTS=y
-
-#
-# libabseil-cpp needs a toolchain w/ gcc >= 4.9, C++, threads, dynamic library
-#
+# BR2_PACKAGE_LIBABSEIL_CPP is not set
 # BR2_PACKAGE_LIBARGTABLE2 is not set
 BR2_PACKAGE_LIBATOMIC_OPS_ARCH_SUPPORTS=y
 # BR2_PACKAGE_LIBATOMIC_OPS is not set
@@ -2450,16 +1789,10 @@ BR2_PACKAGE_LIBBSD_ARCH_SUPPORTS=y
 # BR2_PACKAGE_LIBBYTESIZE is not set
 # BR2_PACKAGE_LIBCAP is not set
 # BR2_PACKAGE_LIBCAP_NG is not set
-
-#
-# libcgroup needs a glibc toolchain w/ C++
-#
+# BR2_PACKAGE_LIBCGROUP is not set
 # BR2_PACKAGE_LIBCLC is not set
 # BR2_PACKAGE_LIBCORRECT is not set
-
-#
-# libcrossguid needs a toolchain w/ C++, gcc >= 4.7
-#
+# BR2_PACKAGE_LIBCROSSGUID is not set
 # BR2_PACKAGE_LIBCSV is not set
 # BR2_PACKAGE_LIBDAEMON is not set
 # BR2_PACKAGE_LIBDILL is not set
@@ -2472,75 +1805,39 @@ BR2_PACKAGE_LIBBSD_ARCH_SUPPORTS=y
 # libexecinfo needs a musl or uclibc toolchain w/ dynamic library
 #
 # BR2_PACKAGE_LIBFFI is not set
-
-#
-# libfutils needs a toolchain w/ C++, threads
-#
+# BR2_PACKAGE_LIBFUTILS is not set
 # BR2_PACKAGE_LIBGEE is not set
-
-#
-# libgeos needs a toolchain w/ C++, wchar, threads not binutils bug 27597
-#
+# BR2_PACKAGE_LIBGEOS is not set
 # BR2_PACKAGE_LIBGLIB2 is not set
 # BR2_PACKAGE_LIBGLOB is not set
-
-#
-# libical needs a toolchain w/ C++, dynamic library, wchar
-#
+# BR2_PACKAGE_LIBICAL is not set
 # BR2_PACKAGE_LIBITE is not set
-
-#
-# libks needs a toolchain w/ C++, NPTL, dynamic library
-#
-
-#
-# liblinear needs a toolchain w/ C++
-#
-
-#
-# libloki needs a toolchain w/ C++, threads
-#
+# BR2_PACKAGE_LIBKS is not set
+# BR2_PACKAGE_LIBLINEAR is not set
+# BR2_PACKAGE_LIBLOKI is not set
 # BR2_PACKAGE_LIBNPTH is not set
 BR2_PACKAGE_LIBNSPR_ARCH_SUPPORT=y
 # BR2_PACKAGE_LIBNSPR is not set
-
-#
-# libosmium needs a toolchain w/ C++, wchar, threads, gcc >= 4.7
-#
+# BR2_PACKAGE_LIBOSMIUM is not set
 
 #
 # libpeas needs python3
 #
 # BR2_PACKAGE_LIBPFM4 is not set
-
-#
-# libplist needs a toolchain w/ C++, threads
-#
+# BR2_PACKAGE_LIBPLIST is not set
 # BR2_PACKAGE_LIBPTHREAD_STUBS is not set
 # BR2_PACKAGE_LIBPTHSEM is not set
 # BR2_PACKAGE_LIBPWQUALITY is not set
 # BR2_PACKAGE_LIBQB is not set
 BR2_PACKAGE_LIBSECCOMP_ARCH_SUPPORTS=y
 # BR2_PACKAGE_LIBSECCOMP is not set
-
-#
-# libshdata needs a toolchain w/ C++, threads
-#
-
-#
-# libsigc++ needs a toolchain w/ C++, gcc >= 7
-#
-
-#
-# libsigc++ (2.x.x) needs a toolchain w/ C++, gcc >= 4.9
-#
+# BR2_PACKAGE_LIBSHDATA is not set
+# BR2_PACKAGE_LIBSIGC is not set
+# BR2_PACKAGE_LIBSIGC2 is not set
 BR2_PACKAGE_LIBSIGSEGV_ARCH_SUPPORTS=y
 # BR2_PACKAGE_LIBSIGSEGV is not set
 # BR2_PACKAGE_LIBSOLV is not set
-
-#
-# libspatialindex needs a toolchain w/ C++, gcc >= 4.7
-#
+# BR2_PACKAGE_LIBSPATIALINDEX is not set
 # BR2_PACKAGE_LIBTALLOC is not set
 # BR2_PACKAGE_LIBTASN1 is not set
 # BR2_PACKAGE_LIBTOMMATH is not set
@@ -2556,79 +1853,37 @@ BR2_PACKAGE_LIBURCU_ARCH_SUPPORTS=y
 # BR2_PACKAGE_LIQUID_DSP is not set
 BR2_PACKAGE_LLVM_ARCH_SUPPORTS=y
 BR2_PACKAGE_LLVM_TARGET_ARCH="riscv64"
-
-#
-# llvm needs a toolchain w/ wchar, threads, C++, gcc >= 5, dynamic library, host gcc >= 5
-#
+# BR2_PACKAGE_LLVM is not set
 # BR2_PACKAGE_LTTNG_LIBUST is not set
 # BR2_PACKAGE_MATIO is not set
 # BR2_PACKAGE_MPC is not set
 # BR2_PACKAGE_MPDECIMAL is not set
 # BR2_PACKAGE_MPFR is not set
 # BR2_PACKAGE_MPIR is not set
-
-#
-# msgpack needs a toolchain w/ C++
-#
+# BR2_PACKAGE_MSGPACK is not set
 # BR2_PACKAGE_NEON_2_SSE is not set
 # BR2_PACKAGE_ORC is not set
 # BR2_PACKAGE_P11_KIT is not set
 BR2_PACKAGE_POCO_ARCH_SUPPORTS=y
-
-#
-# poco needs a toolchain w/ wchar, NPTL, C++, dynamic library, gcc >= 5 w/ C++14
-#
+# BR2_PACKAGE_POCO is not set
 BR2_PACKAGE_HOST_PROTOBUF_ARCH_SUPPORTS=y
 BR2_PACKAGE_PROTOBUF_ARCH_SUPPORTS=y
-
-#
-# protobuf needs a toolchain w/ C++, threads, dynamic library, gcc >= 4.8
-#
-
-#
-# protobuf-c needs a toolchain w/ C++, threads
-#
-
-#
-# protozero needs a toolchain w/ C++, gcc >= 4.7
-#
-
-#
-# qhull needs a toolchain w/ C++, gcc >= 4.4
-#
+# BR2_PACKAGE_PROTOBUF is not set
+# BR2_PACKAGE_PROTOBUF_C is not set
+# BR2_PACKAGE_PROTOZERO is not set
+# BR2_PACKAGE_QHULL is not set
 # BR2_PACKAGE_QLIBC is not set
 # BR2_PACKAGE_REPROC is not set
-
-#
-# riemann-c-client needs a toolchain w/ C++, threads
-#
-
-#
-# shapelib needs a toolchain w/ C++, threads
-#
+# BR2_PACKAGE_RIEMANN_C_CLIENT is not set
+# BR2_PACKAGE_SHAPELIB is not set
 # BR2_PACKAGE_SKALIBS is not set
 # BR2_PACKAGE_SPHINXBASE is not set
-
-#
-# tbb needs a glibc or musl toolchain w/ dynamic library, threads, C++
-#
+# BR2_PACKAGE_TBB is not set
 # BR2_PACKAGE_TINYCBOR is not set
-
-#
-# tl-expected needs a toolchain w/ C++, gcc >= 4.8
-#
-
-#
-# uvw needs a toolchain w/ NPTL, dynamic library, C++, gcc >= 7
-#
-
-#
-# volk needs a toolchain w/ C++, NPTL, wchar, dynamic library
-#
-
-#
-# xapian needs a toolchain w/ C++
-#
+# BR2_PACKAGE_TL_EXPECTED is not set
+# BR2_PACKAGE_UVW is not set
+# BR2_PACKAGE_VOLK is not set
+# BR2_PACKAGE_XAPIAN is not set
 
 #
 # Security
@@ -2637,36 +1892,18 @@ BR2_PACKAGE_PROTOBUF_ARCH_SUPPORTS=y
 # BR2_PACKAGE_LIBSELINUX is not set
 # BR2_PACKAGE_LIBSEPOL is not set
 # BR2_PACKAGE_SAFECLIB is not set
-
-#
-# softhsm2 needs a toolchain w/ C++, threads, gcc >= 4.8 and dynamic library support
-#
+# BR2_PACKAGE_SOFTHSM2 is not set
 
 #
 # Text and terminal handling
 #
 # BR2_PACKAGE_AUGEAS is not set
-
-#
-# cli11 needs a toolchain w/ C++, gcc >= 4.8
-#
-
-#
-# docopt-cpp needs a toolchain w/ C++, gcc >= 4.7
-#
-
-#
-# enchant needs a toolchain w/ C++, threads, wchar
-#
-
-#
-# fmt needs a toolchain w/ C++, wchar
-#
+# BR2_PACKAGE_CLI11 is not set
+# BR2_PACKAGE_DOCOPT_CPP is not set
+# BR2_PACKAGE_ENCHANT is not set
+# BR2_PACKAGE_FMT is not set
 # BR2_PACKAGE_FSTRCMP is not set
-
-#
-# icu needs a toolchain w/ C++, wchar, threads, gcc >= 4.9, host gcc >= 4.9
-#
+# BR2_PACKAGE_ICU is not set
 # BR2_PACKAGE_INIH is not set
 # BR2_PACKAGE_LIBCLI is not set
 # BR2_PACKAGE_LIBEDIT is not set
@@ -2685,20 +1922,11 @@ BR2_PACKAGE_NCURSES_ADDITIONAL_TERMINFO=""
 # BR2_PACKAGE_PCRE is not set
 # BR2_PACKAGE_PCRE2 is not set
 # BR2_PACKAGE_POPT is not set
-
-#
-# re2 needs a toolchain w/ C++, threads, gcc >= 4.8
-#
+# BR2_PACKAGE_RE2 is not set
 # BR2_PACKAGE_READLINE is not set
 # BR2_PACKAGE_SLANG is not set
-
-#
-# tclap needs a toolchain w/ C++
-#
-
-#
-# termcolor needs a toolchain w/ C++, gcc >= 4.8
-#
+# BR2_PACKAGE_TCLAP is not set
+# BR2_PACKAGE_TERMCOLOR is not set
 # BR2_PACKAGE_UTF8PROC is not set
 
 #
@@ -2718,10 +1946,7 @@ BR2_PACKAGE_NCURSES_ADDITIONAL_TERMINFO=""
 # BR2_PACKAGE_AESPIPE is not set
 # BR2_PACKAGE_BC is not set
 BR2_PACKAGE_BITCOIN_ARCH_SUPPORTS=y
-
-#
-# bitcoin needs a toolchain w/ C++, threads, wchar
-#
+# BR2_PACKAGE_BITCOIN is not set
 # BR2_PACKAGE_COLLECTD is not set
 # BR2_PACKAGE_COLLECTL is not set
 
@@ -2730,16 +1955,9 @@ BR2_PACKAGE_BITCOIN_ARCH_SUPPORTS=y
 #
 # BR2_PACKAGE_EMPTY is not set
 # BR2_PACKAGE_GITLAB_RUNNER is not set
-
-#
-# gnuradio needs a toolchain w/ C++, NPTL, wchar, dynamic library, gcc >= 8
-#
+# BR2_PACKAGE_GNURADIO is not set
 # BR2_PACKAGE_GOOGLEFONTDIRECTORY is not set
 
-#
-# gqrx needs a toolchain w/ C++, threads, wchar, dynamic library, gcc >= 8
-#
-
 #
 # gqrx needs qt5
 #
@@ -2748,74 +1966,48 @@ BR2_PACKAGE_BITCOIN_ARCH_SUPPORTS=y
 # BR2_PACKAGE_LINUX_SYSCALL_SUPPORT is not set
 # BR2_PACKAGE_MOBILE_BROADBAND_PROVIDER_INFO is not set
 # BR2_PACKAGE_NETDATA is not set
-
-#
-# proj needs a toolchain w/ C++, gcc >= 4.7, threads, wchar
-#
+# BR2_PACKAGE_PROJ is not set
 BR2_PACKAGE_QEMU_ARCH_SUPPORTS_TARGET=y
 # BR2_PACKAGE_QEMU is not set
-
-#
-# qpdf needs a toolchain w/ C++, gcc >= 5
-#
+# BR2_PACKAGE_QPDF is not set
 # BR2_PACKAGE_RTL_433 is not set
 # BR2_PACKAGE_SHARED_MIME_INFO is not set
-
-#
-# sunwait needs a toolchain w/ C++
-#
-
-#
-# taskd needs a toolchain w/ C++, wchar, dynamic library
-#
+# BR2_PACKAGE_SUNWAIT is not set
+# BR2_PACKAGE_TASKD is not set
 # BR2_PACKAGE_XUTIL_UTIL_MACROS is not set
 BR2_PACKAGE_Z3_ARCH_SUPPORTS=y
+# BR2_PACKAGE_Z3 is not set
 
 #
 # Networking applications
 #
-
-#
-# aircrack-ng needs a toolchain w/ dynamic library, threads, C++
-#
+# BR2_PACKAGE_AIRCRACK_NG is not set
 # BR2_PACKAGE_ALFRED is not set
 # BR2_PACKAGE_AOETOOLS is not set
 # BR2_PACKAGE_APACHE is not set
 # BR2_PACKAGE_ARGUS is not set
 # BR2_PACKAGE_ARP_SCAN is not set
 # BR2_PACKAGE_ARPTABLES is not set
-
-#
-# asterisk needs a glibc or uClibc toolchain w/ C++, dynamic library, threads, wchar
-#
+# BR2_PACKAGE_ASTERISK is not set
 # BR2_PACKAGE_ATFTP is not set
 # BR2_PACKAGE_AVAHI is not set
 # BR2_PACKAGE_AXEL is not set
 # BR2_PACKAGE_BABELD is not set
 # BR2_PACKAGE_BANDWIDTHD is not set
 # BR2_PACKAGE_BATCTL is not set
-
-#
-# bcusdk needs a toolchain w/ C++
-#
+# BR2_PACKAGE_BCUSDK is not set
 # BR2_PACKAGE_BIND is not set
 # BR2_PACKAGE_BIRD is not set
 # BR2_PACKAGE_BLUEZ5_UTILS is not set
 # BR2_PACKAGE_BMON is not set
 # BR2_PACKAGE_BMX7 is not set
-
-#
-# boinc needs a toolchain w/ dynamic library, C++, threads, gcc >= 4.8
-#
+# BR2_PACKAGE_BOINC is not set
 # BR2_PACKAGE_BRCM_PATCHRAM_PLUS is not set
 # BR2_PACKAGE_BRIDGE_UTILS is not set
 # BR2_PACKAGE_BWM_NG is not set
 # BR2_PACKAGE_C_ICAP is not set
 # BR2_PACKAGE_CAN_UTILS is not set
-
-#
-# cannelloni needs a toolchain w/ C++, threads, dynamic library, gcc >= 4.8
-#
+# BR2_PACKAGE_CANNELLONI is not set
 # BR2_PACKAGE_CASYNC is not set
 # BR2_PACKAGE_CFM is not set
 # BR2_PACKAGE_CHRONY is not set
@@ -2828,18 +2020,8 @@ BR2_PACKAGE_Z3_ARCH_SUPPORTS=y
 # BR2_PACKAGE_CONNTRACK_TOOLS is not set
 # BR2_PACKAGE_CORKSCREW is not set
 # BR2_PACKAGE_CRDA is not set
-
-#
-# ctorrent needs a toolchain w/ C++
-#
-
-#
-# cups needs a toolchain w/ C++, threads
-#
-
-#
-# cups-filters needs a toolchain w/ wchar, C++, threads and dynamic library, gcc >= 5
-#
+# BR2_PACKAGE_CTORRENT is not set
+# BR2_PACKAGE_CUPS is not set
 # BR2_PACKAGE_DANTE is not set
 # BR2_PACKAGE_DARKHTTPD is not set
 # BR2_PACKAGE_DEHYDRATED is not set
@@ -2861,47 +2043,26 @@ BR2_PACKAGE_Z3_ARCH_SUPPORTS=y
 # BR2_PACKAGE_FLANNEL is not set
 # BR2_PACKAGE_FPING is not set
 # BR2_PACKAGE_FREERADIUS_SERVER is not set
-
-#
-# freeswitch needs a toolchain w/ C++, dynamic library, threads, wchar
-#
+# BR2_PACKAGE_FREESWITCH is not set
 # BR2_PACKAGE_FRR is not set
-
-#
-# gerbera needs a toolchain w/ C++, dynamic library, threads, wchar, gcc >= 8
-#
+# BR2_PACKAGE_GERBERA is not set
 # BR2_PACKAGE_GESFTPSERVER is not set
-
-#
-# gloox needs a toolchain w/ C++
-#
+# BR2_PACKAGE_GLOOX is not set
 # BR2_PACKAGE_GLORYTUN is not set
 
 #
 # gupnp-tools needs libgtk3
 #
-
-#
-# hans needs a toolchain w/ C++
-#
+# BR2_PACKAGE_HANS is not set
 BR2_PACKAGE_HAPROXY_ARCH_SUPPORTS=y
 # BR2_PACKAGE_HAPROXY is not set
 # BR2_PACKAGE_HIAWATHA is not set
 # BR2_PACKAGE_HOSTAPD is not set
 # BR2_PACKAGE_HTPDATE is not set
 # BR2_PACKAGE_HTTPING is not set
-
-#
-# i2pd needs a toolchain w/ C++, NPTL, wchar
-#
-
-#
-# ibrdtn-tools needs a toolchain w/ C++, threads
-#
-
-#
-# ibrdtnd needs a toolchain w/ C++, threads
-#
+# BR2_PACKAGE_I2PD is not set
+# BR2_PACKAGE_IBRDTN_TOOLS is not set
+# BR2_PACKAGE_IBRDTND is not set
 # BR2_PACKAGE_IFMETRIC is not set
 # BR2_PACKAGE_IFTOP is not set
 BR2_PACKAGE_IFUPDOWN_SCRIPTS=y
@@ -2910,10 +2071,7 @@ BR2_PACKAGE_IFUPDOWN_SCRIPTS=y
 # BR2_PACKAGE_IGMPPROXY is not set
 # BR2_PACKAGE_INADYN is not set
 # BR2_PACKAGE_IODINE is not set
-
-#
-# iperf needs a toolchain w/ C++
-#
+# BR2_PACKAGE_IPERF is not set
 # BR2_PACKAGE_IPERF3 is not set
 # BR2_PACKAGE_IPROUTE2 is not set
 # BR2_PACKAGE_IPSET is not set
@@ -2925,28 +2083,16 @@ BR2_PACKAGE_IFUPDOWN_SCRIPTS=y
 # BR2_PACKAGE_IWD is not set
 # BR2_PACKAGE_JANUS_GATEWAY is not set
 # BR2_PACKAGE_KEEPALIVED is not set
-
-#
-# kismet needs a toolchain w/ threads, C++, gcc >= 5
-#
+# BR2_PACKAGE_KISMET is not set
 # BR2_PACKAGE_KNOCK is not set
 # BR2_PACKAGE_KSMBD_TOOLS is not set
 # BR2_PACKAGE_LEAFNODE2 is not set
 # BR2_PACKAGE_LFT is not set
-
-#
-# lftp requires a toolchain w/ C++, wchar
-#
+# BR2_PACKAGE_LFTP is not set
 # BR2_PACKAGE_LIGHTTPD is not set
-
-#
-# linknx needs a toolchain w/ C++
-#
+# BR2_PACKAGE_LINKNX is not set
 # BR2_PACKAGE_LINKS is not set
-
-#
-# linphone needs a toolchain w/ threads, C++, dynamic library, wchar, gcc >= 5
-#
+# BR2_PACKAGE_LINPHONE is not set
 # BR2_PACKAGE_LINUX_ZIGBEE is not set
 # BR2_PACKAGE_LINUXPTP is not set
 # BR2_PACKAGE_LLDPD is not set
@@ -2961,14 +2107,8 @@ BR2_PACKAGE_IFUPDOWN_SCRIPTS=y
 # BR2_PACKAGE_MJPG_STREAMER is not set
 # BR2_PACKAGE_MODEM_MANAGER is not set
 BR2_PACKAGE_MONGREL2_LIBC_SUPPORTS=y
-
-#
-# mongrel2 needs a uClibc or glibc toolchain w/ C++, threads, dynamic library
-#
-
-#
-# mosh needs a toolchain w/ C++, threads, dynamic library, wchar, gcc >= 4.8
-#
+# BR2_PACKAGE_MONGREL2 is not set
+# BR2_PACKAGE_MOSH is not set
 # BR2_PACKAGE_MOSQUITTO is not set
 # BR2_PACKAGE_MROUTED is not set
 # BR2_PACKAGE_MRP is not set
@@ -2991,14 +2131,8 @@ BR2_PACKAGE_MONGREL2_LIBC_SUPPORTS=y
 # BR2_PACKAGE_NGINX is not set
 # BR2_PACKAGE_NGIRCD is not set
 # BR2_PACKAGE_NGREP is not set
-
-#
-# nload needs a toolchain w/ C++
-#
-
-#
-# nmap-nmap needs a toolchain w/ C++, threads
-#
+# BR2_PACKAGE_NLOAD is not set
+# BR2_PACKAGE_NMAP is not set
 # BR2_PACKAGE_NOIP is not set
 # BR2_PACKAGE_NTP is not set
 # BR2_PACKAGE_NTPSEC is not set
@@ -3043,10 +2177,7 @@ BR2_PACKAGE_MONGREL2_LIBC_SUPPORTS=y
 # BR2_PACKAGE_RPCBIND is not set
 # BR2_PACKAGE_RSH_REDONE is not set
 # BR2_PACKAGE_RSYNC is not set
-
-#
-# rtorrent needs a toolchain w/ C++, threads, wchar, gcc >= 4.9
-#
+# BR2_PACKAGE_RTORRENT is not set
 # BR2_PACKAGE_RTPTOOLS is not set
 
 #
@@ -3055,16 +2186,10 @@ BR2_PACKAGE_MONGREL2_LIBC_SUPPORTS=y
 # BR2_PACKAGE_S6_DNS is not set
 # BR2_PACKAGE_S6_NETWORKING is not set
 # BR2_PACKAGE_SAMBA4 is not set
-
-#
-# sconeserver needs a toolchain with dynamic library, C++, NPTL
-#
+# BR2_PACKAGE_SCONESERVER is not set
 # BR2_PACKAGE_SER2NET is not set
 # BR2_PACKAGE_SHADOWSOCKS_LIBEV is not set
-
-#
-# shairport-sync needs a toolchain w/ C++, NPTL
-#
+# BR2_PACKAGE_SHAIRPORT_SYNC is not set
 # BR2_PACKAGE_SHELLINABOX is not set
 # BR2_PACKAGE_SMCROUTE is not set
 # BR2_PACKAGE_SNGREP is not set
@@ -3074,10 +2199,7 @@ BR2_PACKAGE_MONGREL2_LIBC_SUPPORTS=y
 # BR2_PACKAGE_SOFTETHER is not set
 # BR2_PACKAGE_SPAWN_FCGI is not set
 # BR2_PACKAGE_SPICE_PROTOCOL is not set
-
-#
-# squid needs a toolchain w/ C++, threads, gcc >= 4.8 not affected by bug 64735
-#
+# BR2_PACKAGE_SQUID is not set
 # BR2_PACKAGE_SSDP_RESPONDER is not set
 # BR2_PACKAGE_SSHGUARD is not set
 # BR2_PACKAGE_SSHPASS is not set
@@ -3093,10 +2215,7 @@ BR2_PACKAGE_MONGREL2_LIBC_SUPPORTS=y
 # BR2_PACKAGE_TINYSSH is not set
 # BR2_PACKAGE_TOR is not set
 # BR2_PACKAGE_TRACEROUTE is not set
-
-#
-# transmission needs a toolchain w/ dynamic library, threads, C++, gcc >= 7
-#
+# BR2_PACKAGE_TRANSMISSION is not set
 # BR2_PACKAGE_TUNCTL is not set
 # BR2_PACKAGE_TVHEADEND is not set
 # BR2_PACKAGE_UACME is not set
@@ -3110,10 +2229,7 @@ BR2_PACKAGE_MONGREL2_LIBC_SUPPORTS=y
 # BR2_PACKAGE_USHARE is not set
 # BR2_PACKAGE_USSP_PUSH is not set
 # BR2_PACKAGE_VDE2 is not set
-
-#
-# vdr needs a toolchain w/ C++, dynamic library, NPTL, wchar, headers >= 3.9
-#
+# BR2_PACKAGE_VDR is not set
 # BR2_PACKAGE_VNSTAT is not set
 # BR2_PACKAGE_VPNC is not set
 # BR2_PACKAGE_VSFTPD is not set
@@ -3122,24 +2238,15 @@ BR2_PACKAGE_MONGREL2_LIBC_SUPPORTS=y
 # BR2_PACKAGE_WIREGUARD_TOOLS is not set
 # BR2_PACKAGE_WIRELESS_REGDB is not set
 # BR2_PACKAGE_WIRELESS_TOOLS is not set
-
-#
-# wireshark needs a toolchain w/ wchar, threads, dynamic library, C++
-#
+# BR2_PACKAGE_WIRESHARK is not set
 # BR2_PACKAGE_WPA_SUPPLICANT is not set
 # BR2_PACKAGE_WPAN_TOOLS is not set
 # BR2_PACKAGE_XINETD is not set
 # BR2_PACKAGE_XL2TP is not set
 # BR2_PACKAGE_XTABLES_ADDONS is not set
 # BR2_PACKAGE_ZABBIX is not set
-
-#
-# zeek needs a toolchain w/ C++, wchar, threads, dynamic library, gcc >= 7, host gcc >= 7
-#
-
-#
-# znc needs a toolchain w/ C++, dynamic library, gcc >= 4.8, threads
-#
+# BR2_PACKAGE_ZEEK is not set
+# BR2_PACKAGE_ZNC is not set
 
 #
 # Package managers
@@ -3199,10 +2306,7 @@ BR2_PACKAGE_MONGREL2_LIBC_SUPPORTS=y
 #
 # Security
 #
-
-#
-# apparmor needs a toolchain w/ headers >= 3.16, threads, C++
-#
+# BR2_PACKAGE_APPARMOR is not set
 # BR2_PACKAGE_CHECKPOLICY is not set
 # BR2_PACKAGE_IMA_EVM_UTILS is not set
 # BR2_PACKAGE_OPTEE_CLIENT is not set
@@ -3281,10 +2385,7 @@ BR2_PACKAGE_GNUPG2_DEPENDS=y
 # BR2_PACKAGE_CRUN is not set
 # BR2_PACKAGE_DAEMON is not set
 # BR2_PACKAGE_DC3DD is not set
-
-#
-# ddrescue needs a toolchain w/ C++
-#
+# BR2_PACKAGE_DDRESCUE is not set
 # BR2_PACKAGE_DOCKER_CLI is not set
 
 #
@@ -3327,10 +2428,7 @@ BR2_PACKAGE_INITSCRIPTS=y
 # netifrc needs openrc as init system
 #
 # BR2_PACKAGE_NUMACTL is not set
-
-#
-# nut needs a toolchain w/ C++
-#
+# BR2_PACKAGE_NUT is not set
 
 #
 # pamtester depends on linux-pam

From aeacb481aabb1669d465389b3250e86c797b4993 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 27 Sep 2023 12:00:47 -0500
Subject: [PATCH 17/32] Fixed sutble RAS bug when the stack size was not a
 power of 2.

---
 src/ifu/bpred/RASPredictor.sv | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/src/ifu/bpred/RASPredictor.sv b/src/ifu/bpred/RASPredictor.sv
index 5dd3cf7b2..445bac622 100644
--- a/src/ifu/bpred/RASPredictor.sv
+++ b/src/ifu/bpred/RASPredictor.sv
@@ -27,8 +27,7 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module RASPredictor import cvw::*;  #(parameter cvw_t P, 
-                                      parameter StackSize = 16 )(
+module RASPredictor import cvw::*;  #(parameter cvw_t P)(
   input  logic             clk,
   input  logic             reset, 
   input  logic             StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM,
@@ -41,10 +40,10 @@ module RASPredictor import cvw::*;  #(parameter cvw_t P,
    );
 
   logic                     CounterEn;
-  localparam Depth = $clog2(StackSize);
+  localparam Depth = $clog2(P.RAS_SIZE);
 
   logic [Depth-1:0]         NextPtr, Ptr, P1, M1, IncDecPtr;
-  logic [StackSize-1:0]     [P.XLEN-1:0] memory;
+  logic [P.RAS_SIZE-1:0]     [P.XLEN-1:0] memory;
   integer        index;
 
   logic      PopF;
@@ -76,14 +75,17 @@ module RASPredictor import cvw::*;  #(parameter cvw_t P,
   assign P1 = 1;
   assign M1 = '1; // -1
   mux2 #(Depth) PtrMux(P1, M1, DecrementPtr, IncDecPtr);
-  assign NextPtr = Ptr + IncDecPtr;
+  logic [Depth-1:0] Sum;
+  assign Sum = Ptr + IncDecPtr;
+  assign NextPtr = Sum == P.RAS_SIZE[Depth-1:0] ? 0 : Sum; // wrap back around if our stack is not a power of 2
+  //assign NextPtr = Ptr + IncDecPtr;
 
   flopenr #(Depth) PTR(clk, reset, CounterEn, NextPtr, Ptr);
 
   // RAS must be reset. 
   always_ff @ (posedge clk) begin
     if(reset) begin
-      for(index=0; index<StackSize; index++)
+      for(index=0; index<P.RAS_SIZE; index++)
     memory[index] <= {P.XLEN{1'b0}};
     end else if(PushE) begin
       memory[NextPtr] <= #1 PCLinkE;

From f863cbf3668f5fb12a3978eb7b4b41ea8ea19d78 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 27 Sep 2023 12:25:05 -0500
Subject: [PATCH 18/32] Actually fixed non-power of 2 issue with RAS. Added RAS
 swapping to branch predictor scripts and configurations.

---
 bin/parseTest.py                | 13 +++++++---
 config/buildroot/config.vh      |  1 +
 config/fpga/config.vh           |  1 +
 config/rv32e/config.vh          |  1 +
 config/rv32gc/config.vh         |  6 +++++
 config/rv32i/config.vh          |  1 +
 config/rv32imc/config.vh        |  1 +
 config/rv64fpquad/config.vh     |  1 +
 config/rv64gc/config.vh         |  3 ++-
 config/rv64i/config.vh          |  1 +
 config/shared/parameter-defs.vh |  1 +
 sim/bpred-sim.py                | 46 ++++++++++++++++++++++++---------
 src/cvw.sv                      |  1 +
 src/ifu/bpred/RASPredictor.sv   |  5 +++-
 14 files changed, 64 insertions(+), 18 deletions(-)

diff --git a/bin/parseTest.py b/bin/parseTest.py
index ba3309aff..c24fbe3fe 100755
--- a/bin/parseTest.py
+++ b/bin/parseTest.py
@@ -32,6 +32,10 @@ import math
 import numpy as np
 import argparse
 
+RefData = [('twobitCModel6', 'twobitCModel', 64, 9.65280765420711), ('twobitCModel8', 'twobitCModel', 256, 8.75120245829945), ('twobitCModel10', 'twobitCModel', 1024, 8.1318382397263),
+           ('twobitCModel12', 'twobitCModel', 4096, 7.53026646633342), ('twobitCModel14', 'twobitCModel', 16384, 6.07679338544009), ('twobitCModel16', 'twobitCModel', 65536, 6.07679338544009),
+           ('gshareCModel6', 'gshareCModel', 64, 10.6602835418646), ('gshareCModel8', 'gshareCModel', 256, 8.38384710559667), ('gshareCModel10', 'gshareCModel', 1024, 6.36847432155534),
+           ('gshareCModel12', 'gshareCModel', 4096, 3.91108491151983), ('gshareCModel14', 'gshareCModel', 16384, 2.83926519215395), ('gshareCModel16', 'gshareCModel', 65536, .60213659066941)]
 
 def ParseBranchListFile(path):
     '''Take the path to the list of Questa Sim log files containing the performance counters outputs.  File
@@ -65,7 +69,7 @@ def ProcessFile(fileName):
             HPMClist = { }
         elif(len(lineToken) > 4 and lineToken[1][0:3] == 'Cnt'):
             countToken = line.split('=')[1].split()
-            value = int(countToken[0])
+            value = int(countToken[0]) if countToken[0] != 'x' else 0
             name = ' '.join(countToken[1:])
             HPMClist[name] = value
         elif ('is done' in line):
@@ -111,7 +115,7 @@ def ComputeGeometricAverage(benchmarks):
     benchmarks.append(('Mean', '', AllAve))
 
 def GenerateName(predictorType, predictorParams):
-    if(predictorType == 'gshare' or  predictorType == 'twobit'):
+    if(predictorType == 'gshare' or  predictorType == 'twobit' or predictorType == 'btb' or predictorType == 'class'):
         return predictorType + predictorParams[0]
     elif(predictorParams == 'local'):
         return predictorType + predictorParams[0] + '_' + predictorParams[1]
@@ -120,7 +124,7 @@ def GenerateName(predictorType, predictorParams):
         sys.exit(-1)
 
 def ComputePredNumEntries(predictorType, predictorParams):
-    if(predictorType == 'gshare' or  predictorType == 'twobit'):
+    if(predictorType == 'gshare' or  predictorType == 'twobit' or predictorType == 'btb' or predictorType == 'class'):
         return 2**int(predictorParams[0])
     elif(predictorParams == 'local'):
         return 2**int(predictorParams[0]) * int(predictorParams[1]) + 2**int(predictorParams[1])
@@ -286,7 +290,7 @@ def ReportAsGraph(benchmarkDict, bar):
               'ClassMPR': 'Class Misprediction'}
     if(args.summary):
         markers = ['x', '.', '+', '*', '^', 'o', ',', 's']
-        colors = ['black', 'blue', 'dodgerblue', 'turquoise', 'lightsteelblue', 'gray', 'black', 'blue']
+        colors = ['blue', 'black', 'dodgerblue', 'gray', 'lightsteelblue', 'turquoise', 'black', 'blue']
         temp = benchmarkDict['Mean']
 
         # the benchmarkDict['Mean'] contains sequencies of results for multiple
@@ -429,6 +433,7 @@ performanceCounterList = BuildDataBase(predictorLogs)         # builds a databas
 benchmarkFirstList = ReorderDataBase(performanceCounterList)  # reorder first by benchmark then trace
 benchmarkDict = ExtractSelectedData(benchmarkFirstList)       # filters to just the desired performance counter metric
 
+if(args.reference): benchmarkDict['Mean'].extend(RefData)
 #print(benchmarkDict['Mean'])
 #print(benchmarkDict['aha-mont64Speed'])
 #print(benchmarkDict)
diff --git a/config/buildroot/config.vh b/config/buildroot/config.vh
index 38960c735..79ee99f3c 100644
--- a/config/buildroot/config.vh
+++ b/config/buildroot/config.vh
@@ -142,6 +142,7 @@ localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BAS
 localparam BPRED_SIZE = 32'd10;
 localparam BPRED_NUM_LHR = 32'd6;
 localparam BTB_SIZE = 32'd10;
+localparam RAS_SIZE = 32'd16;
 
 
 localparam SVADU_SUPPORTED = 1;
diff --git a/config/fpga/config.vh b/config/fpga/config.vh
index 7e582fabb..27903d0be 100644
--- a/config/fpga/config.vh
+++ b/config/fpga/config.vh
@@ -156,6 +156,7 @@ localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BAS
 localparam BPRED_NUM_LHR = 32'd6;
 localparam BPRED_SIZE = 32'd12;
 localparam BTB_SIZE = 32'd10;
+localparam RAS_SIZE = 32'd16;
 
 localparam SVADU_SUPPORTED = 1;
 localparam ZMMUL_SUPPORTED = 0;
diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh
index e1cbdab0f..c67e71c13 100644
--- a/config/rv32e/config.vh
+++ b/config/rv32e/config.vh
@@ -144,6 +144,7 @@ localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BAS
 localparam BPRED_SIZE = 32'd10;
 localparam BPRED_NUM_LHR = 32'd6;
 localparam BTB_SIZE = 32'd10;
+localparam RAS_SIZE = 32'd16;
 
 localparam SVADU_SUPPORTED = 0;
 localparam ZMMUL_SUPPORTED = 0;
diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh
index 46d3ed22a..de966b1f2 100644
--- a/config/rv32gc/config.vh
+++ b/config/rv32gc/config.vh
@@ -150,7 +150,13 @@ localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BAS
 localparam BPRED_SIZE = 32'd10;
 `endif
 localparam BPRED_NUM_LHR = 32'd6;
+`ifdef BTB_OVERRIDE
+localparam BTB_SIZE = `BTB_SIZE;
+localparam RAS_SIZE = `RAS_SIZE;
+`else
 localparam BTB_SIZE = 32'd10;
+localparam RAS_SIZE = 32'd16;
+`endif
 
 localparam SVADU_SUPPORTED = 1;
 localparam ZMMUL_SUPPORTED = 0;
diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh
index e1c5a6a5d..a31e034df 100644
--- a/config/rv32i/config.vh
+++ b/config/rv32i/config.vh
@@ -144,6 +144,7 @@ localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BAS
 localparam BPRED_SIZE = 32'd10;
 localparam BPRED_NUM_LHR = 32'd6;
 localparam BTB_SIZE = 32'd10;
+localparam RAS_SIZE = 32'd16;
 
 localparam SVADU_SUPPORTED = 0;
 localparam ZMMUL_SUPPORTED = 0;
diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh
index a9123cbb4..61eea7325 100644
--- a/config/rv32imc/config.vh
+++ b/config/rv32imc/config.vh
@@ -143,6 +143,7 @@ localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BAS
 localparam BPRED_SIZE = 32'd10;
 localparam BPRED_NUM_LHR = 32'd6;
 localparam BTB_SIZE = 32'd10;
+localparam RAS_SIZE = 32'd16;
 
 localparam SVADU_SUPPORTED = 0;
 localparam ZMMUL_SUPPORTED = 0;
diff --git a/config/rv64fpquad/config.vh b/config/rv64fpquad/config.vh
index 2533dbc21..d8bf3e6fc 100644
--- a/config/rv64fpquad/config.vh
+++ b/config/rv64fpquad/config.vh
@@ -146,6 +146,7 @@ localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BAS
 localparam BPRED_SIZE = 32'd10;
 localparam BPRED_NUM_LHR = 32'd6;
 localparam BTB_SIZE = 32'd10;
+localparam RAS_SIZE = 32'd16;
 
 localparam SVADU_SUPPORTED = 0;
 localparam ZMMUL_SUPPORTED = 0;
diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh
index 16e50b899..36d99020e 100644
--- a/config/rv64gc/config.vh
+++ b/config/rv64gc/config.vh
@@ -147,8 +147,9 @@ localparam PLIC_SDC_ID = 32'd9;
 localparam BPRED_SUPPORTED = 1;
 localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 localparam BPRED_NUM_LHR = 32'd6;
-localparam BPRED_SIZE = 32'd10;
+localparam BPRED_SIZE = 32'd6;
 localparam BTB_SIZE = 32'd10;
+localparam RAS_SIZE = 32'd16;
 
 localparam SVADU_SUPPORTED = 1;
 localparam ZMMUL_SUPPORTED = 0;
diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh
index c27f7faf0..6add96e78 100644
--- a/config/rv64i/config.vh
+++ b/config/rv64i/config.vh
@@ -146,6 +146,7 @@ localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BAS
 localparam BPRED_SIZE = 32'd10;
 localparam BPRED_NUM_LHR = 32'd6;
 localparam BTB_SIZE = 32'd10;
+localparam RAS_SIZE = 32'd16;
 
 localparam SVADU_SUPPORTED = 0;
 localparam ZMMUL_SUPPORTED = 0;
diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh
index 340668466..4921f6a3d 100644
--- a/config/shared/parameter-defs.vh
+++ b/config/shared/parameter-defs.vh
@@ -89,6 +89,7 @@ localparam cvw_t P = '{
   BPRED_SIZE :        BPRED_SIZE,
   BPRED_NUM_LHR : BPRED_NUM_LHR,                       
   BTB_SIZE :        BTB_SIZE,
+  RAS_SIZE :        RAS_SIZE,
   RADIX :        RADIX,
   DIVCOPIES :        DIVCOPIES,
   ZBA_SUPPORTED :        ZBA_SUPPORTED,
diff --git a/sim/bpred-sim.py b/sim/bpred-sim.py
index 4ec9324a3..9a59e8866 100755
--- a/sim/bpred-sim.py
+++ b/sim/bpred-sim.py
@@ -46,19 +46,41 @@ configs = [
     )
 ]
 
-bpdSize = [6, 8, 10, 12, 14, 16]
-bpdType = ['twobit', 'gshare', 'global', 'gshare_basic', 'global_basic', 'local_basic']
-for CurrBPType in bpdType:
-    for CurrBPSize in bpdSize:
-        name = CurrBPType+str(CurrBPSize)
-        configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_OVERRIDE +define+BPRED_TYPE=" + str(bpdType.index(CurrBPType)) + "+define+BPRED_SIZE=" + str(CurrBPSize)
-        tc = TestCase(
-            name=name,
-            variant="rv32gc",
-            cmd="vsim > {} -c <<!\ndo wally-batch.do  rv32gc configOptions " + name + " embench " + configOptions,
-            grepstr="")
-        configs.append(tc)
+# bpdSize = [6, 8, 10, 12, 14, 16]
+# bpdType = ['twobit', 'gshare', 'global', 'gshare_basic', 'global_basic', 'local_basic']
+# for CurrBPType in bpdType:
+#     for CurrBPSize in bpdSize:
+#         name = CurrBPType+str(CurrBPSize)
+#         configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_OVERRIDE +define+BPRED_TYPE=" + str(bpdType.index(CurrBPType)) + "+define+BPRED_SIZE=" + str(CurrBPSize)
+#         tc = TestCase(
+#             name=name,
+#             variant="rv32gc",
+#             cmd="vsim > {} -c <<!\ndo wally-batch.do  rv32gc configOptions " + name + " embench " + configOptions,
+#             grepstr="")
+#         configs.append(tc)
 
+# bpdSize = [6, 8, 10, 12, 14, 16]
+# for CurrBPSize in bpdSize:
+#     name = 'BTB'+str(CurrBPSize)
+#     configOptions = "+define+INSTR_CLASS_PRED=1 +define+BPRED_OVERRIDE +define+BPRED_TYPE=\`BP_GSHARE" + "+define+BPRED_SIZE=16" + "+define+BTB_SIZE=" + str(CurrBPSize) + "+define+BTB_OVERRIDE"
+#     tc = TestCase(
+#         name=name,
+#         variant="rv32gc",
+#         cmd="vsim > {} -c <<!\ndo wally-batch.do  rv32gc configOptions " + name + " embench " + configOptions,
+#         grepstr="")
+#     configs.append(tc)
+
+bpdSize = [2, 3, 4, 6, 10, 16]
+for CurrBPSize in bpdSize:
+    name = 'RAS'+str(CurrBPSize)
+    configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_OVERRIDE +define+BPRED_TYPE=\`BP_GSHARE" + "+define+BPRED_SIZE=16" + "+define+BTB_SIZE=16" + "+define+RAS_SIZE=" + str(CurrBPSize) + "+define+BTB_OVERRIDE+define+RAS_OVERRIDE"
+    tc = TestCase(
+        name=name,
+        variant="rv32gc",
+        cmd="vsim > {} -c <<!\ndo wally-batch.do  rv32gc configOptions " + name + " embench " + configOptions,
+        grepstr="")
+    configs.append(tc)
+    
 # bpdSize = [6, 8, 10, 12, 14, 16]
 # LHRSize = [4, 8, 10]
 # bpdType = ['local_repair']
diff --git a/src/cvw.sv b/src/cvw.sv
index 0c3e959fc..f64618574 100644
--- a/src/cvw.sv
+++ b/src/cvw.sv
@@ -149,6 +149,7 @@ typedef struct packed {
   int                  BPRED_NUM_LHR;
   int                  BPRED_SIZE;
   int                  BTB_SIZE;
+  int                  RAS_SIZE;
 
 // FPU division architecture
   int           RADIX;
diff --git a/src/ifu/bpred/RASPredictor.sv b/src/ifu/bpred/RASPredictor.sv
index 445bac622..bc245d984 100644
--- a/src/ifu/bpred/RASPredictor.sv
+++ b/src/ifu/bpred/RASPredictor.sv
@@ -77,7 +77,10 @@ module RASPredictor import cvw::*;  #(parameter cvw_t P)(
   mux2 #(Depth) PtrMux(P1, M1, DecrementPtr, IncDecPtr);
   logic [Depth-1:0] Sum;
   assign Sum = Ptr + IncDecPtr;
-  assign NextPtr = Sum == P.RAS_SIZE[Depth-1:0] ? 0 : Sum; // wrap back around if our stack is not a power of 2
+  if(|P.RAS_SIZE[Depth-1:0])
+    assign NextPtr = Sum >= P.RAS_SIZE[Depth-1:0] ? 0 : Sum; // wrap back around if our stack is not a power of 2
+  else
+    assign NextPtr = Sum;
   //assign NextPtr = Ptr + IncDecPtr;
 
   flopenr #(Depth) PTR(clk, reset, CounterEn, NextPtr, Ptr);

From 3bbcfade9357c600099e45d3ed71bc912d233c90 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 27 Sep 2023 13:56:51 -0500
Subject: [PATCH 19/32] Completed branch predictor benchmarking.

---
 bin/parseTest.py               |  9 +++--
 sim/bp-results/branch-list.txt | 12 +++++++
 sim/bp-results/btb-list.txt    |  6 ++++
 sim/bp-results/class-list.txt  |  6 ++++
 sim/bp-results/ras-list.txt    |  5 +++
 sim/wave.do                    | 64 +++++++++++++++++++---------------
 6 files changed, 71 insertions(+), 31 deletions(-)
 create mode 100644 sim/bp-results/branch-list.txt
 create mode 100644 sim/bp-results/btb-list.txt
 create mode 100644 sim/bp-results/class-list.txt
 create mode 100644 sim/bp-results/ras-list.txt

diff --git a/bin/parseTest.py b/bin/parseTest.py
index c24fbe3fe..bb6d2871e 100755
--- a/bin/parseTest.py
+++ b/bin/parseTest.py
@@ -109,13 +109,14 @@ def ComputeGeometricAverage(benchmarks):
         index = 0
         for (testName, opt, HPMCList) in benchmarks:
             #print(HPMCList)
-            Product *= HPMCList[field]
+            value = HPMCList[field]
+            if(value != 0): Product *= value # if that value is 0 exclude from mean because it destories the geo mean
             index += 1
         AllAve[field] = Product ** (1.0/index)
     benchmarks.append(('Mean', '', AllAve))
 
 def GenerateName(predictorType, predictorParams):
-    if(predictorType == 'gshare' or  predictorType == 'twobit' or predictorType == 'btb' or predictorType == 'class'):
+    if(predictorType == 'gshare' or  predictorType == 'twobit' or predictorType == 'btb' or predictorType == 'class' or predictorType == 'ras'):
         return predictorType + predictorParams[0]
     elif(predictorParams == 'local'):
         return predictorType + predictorParams[0] + '_' + predictorParams[1]
@@ -126,6 +127,8 @@ def GenerateName(predictorType, predictorParams):
 def ComputePredNumEntries(predictorType, predictorParams):
     if(predictorType == 'gshare' or  predictorType == 'twobit' or predictorType == 'btb' or predictorType == 'class'):
         return 2**int(predictorParams[0])
+    elif(predictorType == 'ras'):
+        return int(predictorParams[0])
     elif(predictorParams == 'local'):
         return 2**int(predictorParams[0]) * int(predictorParams[1]) + 2**int(predictorParams[1])
     else:
@@ -290,7 +293,7 @@ def ReportAsGraph(benchmarkDict, bar):
               'ClassMPR': 'Class Misprediction'}
     if(args.summary):
         markers = ['x', '.', '+', '*', '^', 'o', ',', 's']
-        colors = ['blue', 'black', 'dodgerblue', 'gray', 'lightsteelblue', 'turquoise', 'black', 'blue']
+        colors = ['blue', 'black', 'gray', 'dodgerblue', 'lightsteelblue', 'turquoise', 'black', 'blue']
         temp = benchmarkDict['Mean']
 
         # the benchmarkDict['Mean'] contains sequencies of results for multiple
diff --git a/sim/bp-results/branch-list.txt b/sim/bp-results/branch-list.txt
new file mode 100644
index 000000000..c241610d3
--- /dev/null
+++ b/sim/bp-results/branch-list.txt
@@ -0,0 +1,12 @@
+gshare6.log gshare 6
+gshare8.log gshare 8
+gshare10.log gshare 10
+gshare12.log gshare 12
+gshare14.log gshare 14
+gshare16.log gshare 16
+twobit6.log twobit 6
+twobit8.log twobit 8
+twobit10.log twobit 10
+twobit12.log twobit 12
+twobit14.log twobit 14
+twobit16.log twobit 16
diff --git a/sim/bp-results/btb-list.txt b/sim/bp-results/btb-list.txt
new file mode 100644
index 000000000..741efdf24
--- /dev/null
+++ b/sim/bp-results/btb-list.txt
@@ -0,0 +1,6 @@
+btb6.log btb 6
+btb8.log btb 8
+btb10.log btb 10
+btb12.log btb 12
+btb14.log btb 14
+btb16.log btb 16
diff --git a/sim/bp-results/class-list.txt b/sim/bp-results/class-list.txt
new file mode 100644
index 000000000..0d24aa6ee
--- /dev/null
+++ b/sim/bp-results/class-list.txt
@@ -0,0 +1,6 @@
+class6.log class 6
+class8.log class 8
+class10.log class 10
+class12.log class 12
+class14.log class 14
+class16.log class 16
diff --git a/sim/bp-results/ras-list.txt b/sim/bp-results/ras-list.txt
new file mode 100644
index 000000000..b3e273a3d
--- /dev/null
+++ b/sim/bp-results/ras-list.txt
@@ -0,0 +1,5 @@
+ras3.log ras 3
+ras4.log ras 4
+ras6.log ras 6
+ras10.log ras 10
+ras16.log ras 16
diff --git a/sim/wave.do b/sim/wave.do
index 62ba0108f..20d383bd9 100644
--- a/sim/wave.do
+++ b/sim/wave.do
@@ -299,7 +299,15 @@ add wave -noupdate -group {WriteBack stage} /testbench/InstrW
 add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
 add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM
 add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} -label PHT /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/mem
-add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} -divider {class check}
+add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[5]}
+add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[4]}
+add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[3]}
+add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[2]}
+add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[1]}
+add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[0]}
+add wave -noupdate -expand -group Bpred -expand -group RAS -expand /testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory
+add wave -noupdate -expand -group Bpred -expand -group RAS /testbench/dut/core/ifu/bpred/bpred/RASPredictor/Ptr
+add wave -noupdate -expand -group Bpred -divider {class check}
 add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
 add wave -noupdate -expand -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
 add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
@@ -578,31 +586,31 @@ add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/c
 add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1}
 add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0}
 add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1}
-add wave -noupdate -expand -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
-add wave -noupdate -expand -group {Performance Counters} -label MINSTRET -radix hexadecimal {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
-add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label Branch -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
-add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BP Dir Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
-add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {Jump (Not Return)} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]}
-add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label Return -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]}
-add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BP Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]}
-add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BTA Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]}
-add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {RAS Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]}
-add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]}
-add wave -noupdate -expand -group {Performance Counters} -group ICACHE -label {I Cache Access} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[16]}
-add wave -noupdate -expand -group {Performance Counters} -group ICACHE -label {I Cache Miss} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[17]}
-add wave -noupdate -expand -group {Performance Counters} -group ICACHE -label {I Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[18]}
-add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {Load Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
-add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {Store Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
-add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
-add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]}
-add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {D Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]}
-add wave -noupdate -expand -group {Performance Counters} -group Privileged -label {CSR Write} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[19]}
-add wave -noupdate -expand -group {Performance Counters} -group Privileged -label Fence.I {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[20]}
-add wave -noupdate -expand -group {Performance Counters} -group Privileged -label sfence.VMA {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[21]}
-add wave -noupdate -expand -group {Performance Counters} -group Privileged -label Interrupt {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[22]}
-add wave -noupdate -expand -group {Performance Counters} -group Privileged -label Exception {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[23]}
-add wave -noupdate -expand -group {Performance Counters} -label {FDiv or IDiv Cycles} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[24]}
-add wave -noupdate -expand -group {Performance Counters} /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW
+add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
+add wave -noupdate -group {Performance Counters} -label MINSTRET -radix hexadecimal {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
+add wave -noupdate -group {Performance Counters} -expand -group BP -label Branch -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
+add wave -noupdate -group {Performance Counters} -expand -group BP -label {BP Dir Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
+add wave -noupdate -group {Performance Counters} -expand -group BP -label {Jump (Not Return)} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]}
+add wave -noupdate -group {Performance Counters} -expand -group BP -label Return -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]}
+add wave -noupdate -group {Performance Counters} -expand -group BP -label {BP Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]}
+add wave -noupdate -group {Performance Counters} -expand -group BP -label {BTA Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]}
+add wave -noupdate -group {Performance Counters} -expand -group BP -label {RAS Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]}
+add wave -noupdate -group {Performance Counters} -expand -group BP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]}
+add wave -noupdate -group {Performance Counters} -group ICACHE -label {I Cache Access} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[16]}
+add wave -noupdate -group {Performance Counters} -group ICACHE -label {I Cache Miss} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[17]}
+add wave -noupdate -group {Performance Counters} -group ICACHE -label {I Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[18]}
+add wave -noupdate -group {Performance Counters} -group DCACHE -label {Load Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
+add wave -noupdate -group {Performance Counters} -group DCACHE -label {Store Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
+add wave -noupdate -group {Performance Counters} -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
+add wave -noupdate -group {Performance Counters} -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]}
+add wave -noupdate -group {Performance Counters} -group DCACHE -label {D Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]}
+add wave -noupdate -group {Performance Counters} -group Privileged -label {CSR Write} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[19]}
+add wave -noupdate -group {Performance Counters} -group Privileged -label Fence.I {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[20]}
+add wave -noupdate -group {Performance Counters} -group Privileged -label sfence.VMA {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[21]}
+add wave -noupdate -group {Performance Counters} -group Privileged -label Interrupt {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[22]}
+add wave -noupdate -group {Performance Counters} -group Privileged -label Exception {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[23]}
+add wave -noupdate -group {Performance Counters} -label {FDiv or IDiv Cycles} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[24]}
+add wave -noupdate -group {Performance Counters} /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW
 add wave -noupdate -group {ifu } -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState
 add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/HREADY
 add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/FetchBuffer
@@ -677,7 +685,7 @@ add wave -noupdate /testbench/dut/core/fpu/fpu/fctrl/IllegalFPUInstrD
 add wave -noupdate /testbench/dut/core/fpu/fpu/fctrl/STATUS_FS
 add wave -noupdate /testbench/dut/core/priv/priv/csr/csrsr/STATUS_FS_INT
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {172636 ns} 1} {{Cursor 4} {5101 ns} 0} {{Cursor 3} {152766 ns} 1}
+WaveRestoreCursors {{Cursor 4} {172636 ns} 1} {{Cursor 4} {111958 ns} 0} {{Cursor 3} {152766 ns} 1}
 quietly wave cursor active 2
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 194
@@ -693,4 +701,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {4326 ns} {6929 ns}
+WaveRestoreZoom {37879604 ns} {38203328 ns}

From 77c591621cd0228e120246f8ccf9fa48c224e4fa Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 27 Sep 2023 13:57:40 -0500
Subject: [PATCH 20/32] Renamed parseTest.py to parseHPMC.py

---
 bin/parseHPMC.py | 624 +++++++++++++++++++++++++++++------------------
 bin/parseTest.py | 470 -----------------------------------
 2 files changed, 385 insertions(+), 709 deletions(-)
 delete mode 100755 bin/parseTest.py

diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py
index 8bf98ef5a..bb6d2871e 100755
--- a/bin/parseHPMC.py
+++ b/bin/parseHPMC.py
@@ -1,8 +1,8 @@
 #!/usr/bin/python3
 
 ###########################################
-## Written: Ross Thompson ross1728@gmail.com
-## Created: 4 Jan 2022
+## Written: Rose Thompson ross1728@gmail.com
+## Created: 20 September 2023
 ## Modified: 
 ##
 ## Purpose: Parses the performance counters from a modelsim trace.
@@ -28,111 +28,30 @@
 import os
 import sys
 import matplotlib.pyplot as plt
-import re
+import math
+import numpy as np
+import argparse
 
-#RefData={'twobitCModel' :(['6', '8', '10', '12', '14', '16'],
-#                          [11.0680836450622, 8.53864970807778, 7.59565430177984, 6.38741598498948, 5.83662961500838, 5.83662961500838]),
-#         'gshareCModel' : (['6', '8', '10', '12', '14', '16'],
-#                           [14.5859173702079, 12.3634674403619, 10.5806018170154, 8.38831266973592, 6.37097544620762, 3.52638362703015])
-#}
+RefData = [('twobitCModel6', 'twobitCModel', 64, 9.65280765420711), ('twobitCModel8', 'twobitCModel', 256, 8.75120245829945), ('twobitCModel10', 'twobitCModel', 1024, 8.1318382397263),
+           ('twobitCModel12', 'twobitCModel', 4096, 7.53026646633342), ('twobitCModel14', 'twobitCModel', 16384, 6.07679338544009), ('twobitCModel16', 'twobitCModel', 65536, 6.07679338544009),
+           ('gshareCModel6', 'gshareCModel', 64, 10.6602835418646), ('gshareCModel8', 'gshareCModel', 256, 8.38384710559667), ('gshareCModel10', 'gshareCModel', 1024, 6.36847432155534),
+           ('gshareCModel12', 'gshareCModel', 4096, 3.91108491151983), ('gshareCModel14', 'gshareCModel', 16384, 2.83926519215395), ('gshareCModel16', 'gshareCModel', 65536, .60213659066941)]
 
-#RefData = [('twobitCModel6', 11.0501534891674), ('twobitCModel8', 8.51829052266352), ('twobitCModel10', 7.56775222626483),
-#           ('twobitCModel12', 6.31366834586515), ('twobitCModel14', 5.72699936834177), ('twobitCModel16', 5.72699936834177),
-#           ('gshareCModel6', 14.5731555979574), ('gshareCModel8', 12.3155658100497), ('gshareCModel10', 10.4589596630561),
-#           ('gshareCModel12', 8.25796055444401), ('gshareCModel14', 6.23093702707613), ('gshareCModel16', 3.34001125650374)]
-
-RefData = [('twobitCModel6', 9.65280765420711), ('twobitCModel8', 8.75120245829945), ('twobitCModel10', 8.1318382397263),
-           ('twobitCModel12', 7.53026646633342), ('twobitCModel14', 6.07679338544009), ('twobitCModel16', 6.07679338544009),
-           ('gshareCModel6', 10.6602835418646), ('gshareCModel8', 8.38384710559667), ('gshareCModel10', 6.36847432155534),
-           ('gshareCModel12', 3.91108491151983), ('gshareCModel14', 2.83926519215395), ('gshareCModel16', .60213659066941)]
-
-
-def ComputeCPI(benchmark):
-    'Computes and inserts CPI into benchmark stats.'
-    (nameString, opt, dataDict) = benchmark
-    CPI = 1.0 * int(dataDict['Mcycle']) / int(dataDict['InstRet'])
-    dataDict['CPI'] = CPI
-
-def ComputeBranchDirMissRate(benchmark):
-    'Computes and inserts branch direction miss prediction rate.'
-    (nameString, opt, dataDict) = benchmark
-    branchDirMissRate = 100.0 * int(dataDict['BP Dir Wrong']) / int(dataDict['Br Count'])
-    dataDict['BDMR'] = branchDirMissRate
-
-def ComputeBranchTargetMissRate(benchmark):
-    'Computes and inserts branch target miss prediction rate.'
-    # *** this is wrong in the verilog test bench
-    (nameString, opt, dataDict) = benchmark
-    branchTargetMissRate = 100.0 * int(dataDict['BP Target Wrong']) / (int(dataDict['Br Count']) + int(dataDict['Jump Not Return']))
-    dataDict['BTMR'] = branchTargetMissRate
-
-def ComputeRASMissRate(benchmark):
-    'Computes and inserts return address stack miss prediction rate.'
-    (nameString, opt, dataDict) = benchmark
-    RASMPR = 100.0 * int(dataDict['RAS Wrong']) / int(dataDict['Return'])
-    dataDict['RASMPR'] = RASMPR
-
-def ComputeInstrClassMissRate(benchmark):
-    'Computes and inserts instruction class miss prediction rate.'
-    (nameString, opt, dataDict) = benchmark
-    ClassMPR = 100.0 * int(dataDict['Instr Class Wrong']) / int(dataDict['InstRet'])
-    dataDict['ClassMPR'] = ClassMPR
+def ParseBranchListFile(path):
+    '''Take the path to the list of Questa Sim log files containing the performance counters outputs.  File
+    is formated in row columns.  Each row is a trace with the file, branch predictor type, and the parameters.
+    parameters can be any number and depend on the predictor type. Returns a list of lists.'''
+    lst = []
+    BranchList = open(path, 'r')
+    for line in BranchList:
+        tokens = line.split()
+        predictorLog = os.path.dirname(path) + '/' + tokens[0]
+        predictorType = tokens[1]
+        predictorParams = tokens[2::]
+        lst.append([predictorLog, predictorType, predictorParams])
+        #print(predictorLog, predictorType, predictorParams)
+    return lst
     
-def ComputeICacheMissRate(benchmark):
-    'Computes and inserts instruction class miss prediction rate.'
-    (nameString, opt, dataDict) = benchmark
-    ICacheMR = 100.0 * int(dataDict['I Cache Miss']) / int(dataDict['I Cache Access'])
-    dataDict['ICacheMR'] = ICacheMR
-
-def ComputeICacheMissTime(benchmark):
-    'Computes and inserts instruction class miss prediction rate.'
-    (nameString, opt, dataDict) = benchmark
-    cycles = int(dataDict['I Cache Miss'])
-    if(cycles == 0): ICacheMR = 0
-    else: ICacheMR = 100.0 * int(dataDict['I Cache Cycles']) / cycles
-    dataDict['ICacheMT'] = ICacheMR
-    
-def ComputeDCacheMissRate(benchmark):
-    'Computes and inserts instruction class miss prediction rate.'
-    (nameString, opt, dataDict) = benchmark
-    DCacheMR = 100.0 * int(dataDict['D Cache Miss']) / int(dataDict['D Cache Access'])
-    dataDict['DCacheMR'] = DCacheMR
-
-def ComputeDCacheMissTime(benchmark):
-    'Computes and inserts instruction class miss prediction rate.'
-    (nameString, opt, dataDict) = benchmark
-    cycles = int(dataDict['D Cache Miss'])
-    if(cycles == 0): DCacheMR = 0
-    else: DCacheMR = 100.0 * int(dataDict['D Cache Cycles']) / cycles
-    dataDict['DCacheMT'] = DCacheMR
-
-def ComputeAll(benchmarks):
-    for benchmark in benchmarks:
-        ComputeCPI(benchmark)
-        ComputeBranchDirMissRate(benchmark)
-        ComputeBranchTargetMissRate(benchmark)
-        ComputeRASMissRate(benchmark)
-        ComputeInstrClassMissRate(benchmark)
-        ComputeICacheMissRate(benchmark)
-        ComputeICacheMissTime(benchmark)
-        ComputeDCacheMissRate(benchmark)
-        ComputeDCacheMissTime(benchmark)
-    
-def printStats(benchmark):
-    (nameString, opt, dataDict) = benchmark
-    print('Test', nameString)
-    print('Compile configuration', opt)
-    print('CPI \t\t\t  %1.2f' % dataDict['CPI'])
-    print('Branch Dir Pred Miss Rate %2.2f' % dataDict['BDMR'])
-    print('Branch Target Pred Miss Rate %2.2f' % dataDict['BTMR'])
-    print('RAS Miss Rate \t\t  %1.2f' % dataDict['RASMPR'])
-    print('Instr Class Miss Rate  %1.2f' % dataDict['ClassMPR'])
-    print('I Cache Miss Rate  %1.4f' % dataDict['ICacheMR'])
-    print('I Cache Miss Ave Cycles  %1.4f' % dataDict['ICacheMT'])
-    print('D Cache Miss Rate  %1.4f' % dataDict['DCacheMR'])
-    print('D Cache Miss Ave Cycles  %1.4f' % dataDict['DCacheMT'])
-    print()
-
 def ProcessFile(fileName):
     '''Extract preformance counters from a modelsim log.  Outputs a list of tuples for each test/benchmark.
     The tuple contains the test name, optimization characteristics, and dictionary of performance counters.'''
@@ -150,43 +69,37 @@ def ProcessFile(fileName):
             HPMClist = { }
         elif(len(lineToken) > 4 and lineToken[1][0:3] == 'Cnt'):
             countToken = line.split('=')[1].split()
-            value = int(countToken[0])
+            value = int(countToken[0]) if countToken[0] != 'x' else 0
             name = ' '.join(countToken[1:])
             HPMClist[name] = value
         elif ('is done' in line):
             benchmarks.append((testName, opt, HPMClist))
     return benchmarks
 
-def ComputeArithmeticAverage(benchmarks):
-    average = {}
-    index = 0
-    for (testName, opt, HPMClist) in benchmarks:
-        for field in HPMClist:
-            value = HPMClist[field]
-            if field not in average:
-                average[field] = value
-            else:
-                average[field] += value
-        index += 1
-    benchmarks.append(('All', '', average))
 
-def FormatToPlot(currBenchmark):
-    names = []
-    values = []
-    for config in currBenchmark:
-        #print ('config' , config)
-        names.append(config[0])
-        values.append(config[1])
-    return (names, values)
+def ComputeStats(benchmarks):
+    for benchmark in benchmarks:
+        (nameString, opt, dataDict) = benchmark
+        dataDict['CPI'] = 1.0 * int(dataDict['Mcycle']) / int(dataDict['InstRet'])
+        dataDict['BDMR'] = 100.0 * int(dataDict['BP Dir Wrong']) / int(dataDict['Br Count'])
+        dataDict['BTMR'] = 100.0 * int(dataDict['BP Target Wrong']) / (int(dataDict['Br Count']) + int(dataDict['Jump Not Return']))
+        dataDict['RASMPR'] = 100.0 * int(dataDict['RAS Wrong']) / int(dataDict['Return'])
+        dataDict['ClassMPR'] = 100.0 * int(dataDict['Instr Class Wrong']) / int(dataDict['InstRet'])
+        dataDict['ICacheMR'] = 100.0 * int(dataDict['I Cache Miss']) / int(dataDict['I Cache Access'])
+
+        cycles = int(dataDict['I Cache Miss'])
+        if(cycles == 0): ICacheMR = 0
+        else: ICacheMR = 100.0 * int(dataDict['I Cache Cycles']) / cycles
+        dataDict['ICacheMT'] = ICacheMR
+
+        dataDict['DCacheMR'] = 100.0 * int(dataDict['D Cache Miss']) / int(dataDict['D Cache Access'])
+
+        (nameString, opt, dataDict) = benchmark
+        cycles = int(dataDict['D Cache Miss'])
+        if(cycles == 0): DCacheMR = 0
+        else: DCacheMR = 100.0 * int(dataDict['D Cache Cycles']) / cycles
+        dataDict['DCacheMT'] = DCacheMR
 
-def GeometricAverage(benchmarks, field):
-    Product = 1
-    index = 0
-    for (testName, opt, HPMCList) in benchmarks:
-        #print(HPMCList)
-        Product *= HPMCList[field]
-        index += 1
-    return Product ** (1.0/index)
 
 def ComputeGeometricAverage(benchmarks):
     fields = ['BDMR', 'BTMR', 'RASMPR', 'ClassMPR', 'ICacheMR', 'DCacheMR', 'CPI', 'ICacheMT', 'DCacheMT']
@@ -196,129 +109,362 @@ def ComputeGeometricAverage(benchmarks):
         index = 0
         for (testName, opt, HPMCList) in benchmarks:
             #print(HPMCList)
-            Product *= HPMCList[field]
+            value = HPMCList[field]
+            if(value != 0): Product *= value # if that value is 0 exclude from mean because it destories the geo mean
             index += 1
         AllAve[field] = Product ** (1.0/index)
-    benchmarks.append(('All', '', AllAve))
+    benchmarks.append(('Mean', '', AllAve))
 
-if(sys.argv[1] == '-b'):
-    configList = []
-    summery = 0
-    if(sys.argv[2] == '-s'):
-        summery = 1
-        sys.argv = sys.argv[1::]
-    for config in sys.argv[2::]:
-        benchmarks = ProcessFile(config)
-        #ComputeArithmeticAverage(benchmarks)
-        ComputeAll(benchmarks)
-        ComputeGeometricAverage(benchmarks)
-        #print('CONFIG: %s GEO MEAN: %f' % (config, GeometricAverage(benchmarks, 'BDMR')))
-        configList.append((config.split('.')[0], benchmarks))
+def GenerateName(predictorType, predictorParams):
+    if(predictorType == 'gshare' or  predictorType == 'twobit' or predictorType == 'btb' or predictorType == 'class' or predictorType == 'ras'):
+        return predictorType + predictorParams[0]
+    elif(predictorParams == 'local'):
+        return predictorType + predictorParams[0] + '_' + predictorParams[1]
+    else:
+        print(f'Error unsupported predictor type {predictorType}')
+        sys.exit(-1)
 
-    # Merge all configruations into a single list
-    benchmarkAll = []
-    for (config, benchmarks) in configList:
-        #print(config)
+def ComputePredNumEntries(predictorType, predictorParams):
+    if(predictorType == 'gshare' or  predictorType == 'twobit' or predictorType == 'btb' or predictorType == 'class'):
+        return 2**int(predictorParams[0])
+    elif(predictorType == 'ras'):
+        return int(predictorParams[0])
+    elif(predictorParams == 'local'):
+        return 2**int(predictorParams[0]) * int(predictorParams[1]) + 2**int(predictorParams[1])
+    else:
+        print(f'Error unsupported predictor type {predictorType}')
+        sys.exit(-1)
+
+def BuildDataBase(predictorLogs):
+    # Once done with the following loop, performanceCounterList will contain the predictor type and size along with the
+    # raw performance counter data and the processed data on a per benchmark basis.  It also includes the geometric mean.
+    # list
+    #   branch predictor configuration 0 (tuple)
+    #     benchmark name
+    #     compiler optimization
+    #     data (dictionary)
+    #       dictionary of performance counters
+    #   branch predictor configuration 1 (tuple)
+    #     benchmark name (dictionary)
+    #     compiler optimization
+    #     data
+    #       dictionary of performance counters
+    # ...
+    performanceCounterList = []
+    for trace in predictorLogs:
+        predictorLog = trace[0]
+        predictorType = trace[1]
+        predictorParams = trace[2]
+        # Extract the performance counter data
+        performanceCounters = ProcessFile(predictorLog)
+        ComputeStats(performanceCounters)
+        ComputeGeometricAverage(performanceCounters)
+        #print(performanceCounters)
+        performanceCounterList.append([GenerateName(predictorType, predictorParams), predictorType, performanceCounters, ComputePredNumEntries(predictorType, predictorParams)])
+    return performanceCounterList
+
+def ReorderDataBase(performanceCounterList):
+    # Reorder the data so the benchmark name comes first, then the branch predictor configuration
+    benchmarkFirstList = []
+    for (predictorName, predictorPrefixName, benchmarks, entries) in performanceCounterList:
         for benchmark in benchmarks:
             (nameString, opt, dataDict) = benchmark
-            #print("BENCHMARK")
-            #print(nameString)
-            #print(opt)
-            #print(dataDict)
-            benchmarkAll.append((nameString, opt, config, dataDict))
-    #print('ALL!!!!!!!!!!')
-    #for bench in benchmarkAll:
-    #    print('BENCHMARK')
-    #    print(bench)
-    #print('ALL!!!!!!!!!!')
+            benchmarkFirstList.append((nameString, opt, predictorName, predictorPrefixName, entries, dataDict))
+    return benchmarkFirstList
 
+def ExtractSelectedData(benchmarkFirstList):
     # now extract all branch prediction direction miss rates for each
     # namestring + opt, config
     benchmarkDict = { }
-    for benchmark in benchmarkAll:
-        (name, opt, config, dataDict) = benchmark
-        if name+'_'+opt in benchmarkDict:
-            benchmarkDict[name+'_'+opt].append((config, dataDict['BDMR']))
+    for benchmark in benchmarkFirstList:
+        (name, opt, config, prefixName, entries, dataDict) = benchmark
+        if opt == 'bd_speedopt_speed': NewName = name+'Sp'
+        elif opt == 'bd_sizeopt_speed': NewName = name+'Sz'
+        else: NewName = name
+        #print(NewName)
+        #NewName = name+'_'+opt
+        if NewName in benchmarkDict:
+            benchmarkDict[NewName].append((config, prefixName, entries, dataDict[ReportPredictorType]))
         else:
-            benchmarkDict[name+'_'+opt] = [(config, dataDict['BDMR'])]
+            benchmarkDict[NewName] = [(config, prefixName, entries, dataDict[ReportPredictorType])]
+    return benchmarkDict
 
-    size = len(benchmarkDict)
-    index = 1
-    if(summery == 0):
-        #print('Number of plots', size)
+def ReportAsTable(benchmarkDict):
+    refLine = benchmarkDict['Mean']
+    FirstLine = []
+    SecondLine = []
+    for (name, typ, size, val) in refLine:
+        FirstLine.append(name)
+        SecondLine.append(size)
 
-        for benchmarkName in benchmarkDict:
-            currBenchmark = benchmarkDict[benchmarkName]
-            (names, values) = FormatToPlot(currBenchmark)
-            print(names, values)
-            plt.subplot(6, 7, index)
-            plt.bar(names, values)
-            plt.title(benchmarkName)
-            plt.ylabel('BR Dir Miss Rate (%)')
-            #plt.xlabel('Predictor')
-            index += 1
-    else:
-        combined = benchmarkDict['All_']
-        # merge the reference data into rtl data
-        # combined.extend(RefData)
-        (name, value) = FormatToPlot(combined)
-        lst = []
-        dct = {}
-        category = []
-        length = []
-        accuracy = []
-        for index in range(0, len(name)):
-            match = re.match(r"([a-z]+)([0-9]+)", name[index], re.I)
-            percent = 100 -value[index]
-            if match:
-                (PredType, size) = match.groups()
-                category.append(PredType)
-                length.append(size)
-                accuracy.append(percent)
-                if(PredType not in dct):
-                    dct[PredType] = ([size], [percent])
-                else:
-                    (currSize, currPercent) = dct[PredType]
-                    currSize.append(size)
-                    currPercent.append(percent)
-                    dct[PredType] = (currSize, currPercent)
-        print(dct)
+    sys.stdout.write('benchmark\t\t')
+    for name in FirstLine:
+        if(len(name) < 8): sys.stdout.write('%s\t\t' % name)
+        else: sys.stdout.write('%s\t' % name)        
+    sys.stdout.write('\n')
+    sys.stdout.write('size\t\t\t')
+    for size in SecondLine:
+        if(len(str(size)) < 8): sys.stdout.write('%d\t\t' % size)
+        else: sys.stdout.write('%d\t' % size)        
+    sys.stdout.write('\n')
+
+    if(args.summary):
+        sys.stdout.write('Mean\t\t\t')
+        for (name, typ, size, val) in refLine:
+            sys.stdout.write('%0.2f\t\t' % (val if not args.invert else 100 - val))
+        sys.stdout.write('\n')
+
+    if(not args.summary):
+        for benchmark in benchmarkDict:
+            length = len(benchmark)
+            if(length < 8): sys.stdout.write('%s\t\t\t' % benchmark)
+            elif(length < 16): sys.stdout.write('%s\t\t' % benchmark)
+            else: sys.stdout.write('%s\t' % benchmark)
+            for (name, typ, size, val) in benchmarkDict[benchmark]:
+                sys.stdout.write('%0.2f\t\t' % (val if not args.invert else 100 -val))
+            sys.stdout.write('\n')
+
+def ReportAsText(benchmarkDict):
+    if(args.summary):
+        mean = benchmarkDict['Mean']
+        print('Mean')
+        for (name, typ, size, val) in mean:
+            sys.stdout.write('%s %s %0.2f\n' % (name, size, val if not args.invert else 100 - val))
+        
+    if(not args.summary):
+        for benchmark in benchmarkDict:
+            print(benchmark)
+            for (name, type, size, val) in benchmarkDict[benchmark]:
+                sys.stdout.write('%s %s %0.2f\n' % (name, size, val if not args.invert else 100 - val))
+
+def Inversion(lst):
+    return [x if not args.invert else 100 - x for x in lst]
+
+def BarGraph(seriesDict, xlabelList, BenchPerRow, FileName):
+    index = 0
+    NumberInGroup = len(seriesDict)
+    # Figure out width of bars.  NumberInGroup bars + want 2 bar space
+    # the space between groups is 1
+    EffectiveNumInGroup = NumberInGroup + 2
+    barWidth = 1 / EffectiveNumInGroup
+    fig = plt.subplots(figsize = (EffectiveNumInGroup*BenchPerRow/8, 4))
+    colors = ['blue', 'blue', 'blue', 'blue', 'blue', 'blue', 'black', 'black', 'black', 'black', 'black', 'black']
+    for name in seriesDict:
+        xpos = np.arange(BenchPerRow)
+        xpos = [x + index*barWidth for x in xpos]
+        values = seriesDict[name]
+        plt.bar(xpos, Inversion(values), width=barWidth, edgecolor='grey', label=name, color=colors[index%len(colors)])
+        index += 1
+    plt.xticks([r + barWidth*(NumberInGroup/2-0.5) for r in range(0, BenchPerRow)], xlabelList)
+    plt.xlabel('Benchmark')
+    if(not args.invert): plt.ylabel('Misprediction Rate (%)')
+    else:  plt.ylabel('Prediction Accuracy (%)') 
+    plt.legend(loc='upper left', ncol=2)
+    plt.savefig(FileName)
+
+def SelectPartition(xlabelListBig, seriesDictBig, group, BenchPerRow):
+    seriesDictTrunk = {}
+    for benchmarkName in seriesDictBig:
+        lst = seriesDictBig[benchmarkName]
+        seriesDictTrunk[benchmarkName] = lst[group*BenchPerRow:(group+1)*BenchPerRow]
+    xlabelListTrunk = xlabelListBig[group*BenchPerRow:(group+1)*BenchPerRow]
+    return(xlabelListTrunk, seriesDictTrunk)
+
+
+def ReportAsGraph(benchmarkDict, bar):
+    def FormatToPlot(currBenchmark):
+        names = []
+        sizes = []
+        values = []
+        typs = []
+        for config in currBenchmark:
+            names.append(config[0])
+            sizes.append(config[1])
+            values.append(config[2])
+            typs.append(config[3])
+        return (names, sizes, values, typs)
+    titlesInvert = {'BDMR' : 'Branch Direction Accuracy',
+              'BTMR' : 'Branch Target Accuracy',
+              'RASMPR': 'RAS Accuracy',
+              'ClassMPR': 'Class Prediction Accuracy'}
+    titles = {'BDMR' : 'Branch Direction Misprediction',
+              'BTMR' : 'Branch Target Misprediction',
+              'RASMPR': 'RAS Misprediction',
+              'ClassMPR': 'Class Misprediction'}
+    if(args.summary):
+        markers = ['x', '.', '+', '*', '^', 'o', ',', 's']
+        colors = ['blue', 'black', 'gray', 'dodgerblue', 'lightsteelblue', 'turquoise', 'black', 'blue']
+        temp = benchmarkDict['Mean']
+
+        # the benchmarkDict['Mean'] contains sequencies of results for multiple
+        # branch predictors with various parameterizations
+        # group the parameterizations by the common typ.
+        sequencies = {}
+        for (name, typ, size, value) in benchmarkDict['Mean']:
+            if not typ in sequencies:
+                sequencies[typ] = [(size, value)]
+            else:
+                sequencies[typ].append((size,value))
+        # then graph the common typ as a single line+scatter plot
+        # finally repeat for all typs of branch predictors and overlay
         fig, axes = plt.subplots()
-        marker={'twobit' : '^', 'gshare' : 'o', 'global' : 's', 'gshareBasic' : '*', 'globalBasic' : 'x', 'btb': 'x', 'twobitCModel' : 'x', 'gshareCModel' : '*', 'tenlocal' : '.', 'eightlocal' : ',', 'fourlocal' : 'x', 'tenlocalahead' : '.', 'eightlocalahead' : ',', 'fourlocalahead' : 'x', 'tenlocalrepair' : 'x'}
-        colors={'twobit' : 'black', 'gshare' : 'blue', 'global' : 'dodgerblue', 'gshareBasic' : 'turquoise', 'globalBasic' : 'lightsteelblue', 'btb' : 'blue', 'twobitCModel' : 'gray', 'gshareCModel' : 'dodgerblue', 'tenlocal' : 'lightblue', 'eightlocal' : 'lightblue', 'fourlocal' : 'lightblue', 'tenlocalahead' : 'lightblue', 'eightlocalahead' : 'lightblue', 'fourlocalahead' : 'lightblue', 'tenlocalrepair' : 'lightblue'}
-        for cat in dct:
-            (x, y) = dct[cat]
-            x=[int(2**int(v)) for v in x]
-            #print(x, y)
-            print(cat)
-            axes.plot(x,y, color=colors[cat])
-            axes.scatter(x,y, label=cat, marker=marker[cat], color=colors[cat])
-            #plt.scatter(x, y, label=cat)
-            #plt.plot(x, y)
-            #axes.set_xticks([4, 6, 8, 10, 12, 14])
+        index = 0
+        if(args.invert): plt.title(titlesInvert[ReportPredictorType])
+        else: plt.title(titles[ReportPredictorType])
+        for branchPredName in sequencies:
+            data = sequencies[branchPredName]
+            (xdata, ydata) = zip(*data) 
+            if args.invert: ydata = [100 - x for x in ydata]
+            axes.plot(xdata, ydata, color=colors[index])
+            axes.scatter(xdata, ydata, label=branchPredName, color=colors[index], marker=markers[index])
+            index = (index + 1) % len(markers)
         axes.legend(loc='upper left')
         axes.set_xscale("log")
         axes.set_ylabel('Prediction Accuracy')
         axes.set_xlabel('Entries')
-        axes.set_xticks([64, 256, 1024, 4096, 16384, 65536])        
-        axes.set_xticklabels([64, 256, 1024, 4096, 16384, 65536])
+        axes.set_xticks(xdata)
+        axes.set_xticklabels(xdata)
         axes.grid(color='b', alpha=0.5, linestyle='dashed', linewidth=0.5)
-    plt.show()
-    
-            
-else:
-    # steps 1 and 2
-    benchmarks = ProcessFile(sys.argv[1])
-    print(benchmarks[0])
-    ComputeAll(benchmarks)
-    ComputeGeometricAverage(benchmarks)
-    # 3 process into useful data
-    # cache hit rates
-    # cache fill time
-    # branch predictor status
-    # hazard counts
-    # CPI
-    # instruction distribution
-    for benchmark in benchmarks:
-        printStats(benchmark)
+        plt.show()
+        
 
+    # if(not args.summary):
+    #     size = len(benchmarkDict)
+    #     sizeSqrt = math.sqrt(size)
+    #     isSquare = math.isclose(sizeSqrt, round(sizeSqrt))
+    #     numCol = math.floor(sizeSqrt)
+    #     numRow = numCol + (0 if isSquare else 1)
+    #     index = 1
+    #     fig = plt.figure()
+    #     for benchmarkName in benchmarkDict:
+    #         currBenchmark = benchmarkDict[benchmarkName]
+    #         (names, typs, sizes, values) = FormatToPlot(currBenchmark)
+    #         #axes.plot(numRow, numCol, index)
+    #         ax = fig.add_subplot(numRow, numCol, index)
+    #         ax.bar(names, values)
+    #         ax.title.set_text(benchmarkName)
+    #         #plt.ylabel('BR Dir Miss Rate (%)')
+    #         #plt.xlabel('Predictor')
+    #         index += 1
+
+    if(not args.summary):
+        size = len(benchmarkDict)
+        sizeSqrt = math.sqrt(size)
+        isSquare = math.isclose(sizeSqrt, round(sizeSqrt))
+        numCol = math.floor(sizeSqrt)
+        numRow = numCol + (0 if isSquare else 1)
+        index = 1
+        BenchPerRow = 7
+
+        xlabelList = []
+        seriesDict = {}
+
+        for benchmarkName in benchmarkDict:
+            currBenchmark = benchmarkDict[benchmarkName]
+            xlabelList.append(benchmarkName)
+            for (name, typ, size, value) in currBenchmark:
+                if(name not in seriesDict):
+                    seriesDict[name] = [value]
+                else:
+                    seriesDict[name].append(value)
+            if(index >= BenchPerRow): break
+            index += 1
+
+        xlabelListBig = []
+        seriesDictBig = {}
+        for benchmarkName in benchmarkDict:
+            currBenchmark = benchmarkDict[benchmarkName]
+            xlabelListBig.append(benchmarkName)
+            for (name, typ, size, value) in currBenchmark:
+                if(name not in seriesDictBig):
+                    seriesDictBig[name] = [value]
+                else:
+                    seriesDictBig[name].append(value)
+
+        #The next step will be to split the benchmarkDict into length BenchPerRow pieces then repeat the following code
+        # on each piece.
+        for row in range(0, math.ceil(39 / BenchPerRow)):
+            (xlabelListTrunk, seriesDictTrunk) = SelectPartition(xlabelListBig, seriesDictBig, row, BenchPerRow)
+            FileName = 'barSegment%d.png' % row
+            groupLen = len(xlabelListTrunk)
+            BarGraph(seriesDictTrunk, xlabelListTrunk, groupLen, FileName)
+
+
+# main
+parser = argparse.ArgumentParser(description='Parses performance counters from a Questa Sim trace to produce a graph or graphs.')
+
+# parse program arguments
+metric = parser.add_mutually_exclusive_group()
+metric.add_argument('-r', '--ras', action='store_const', help='Plot return address stack (RAS) performance.', default=False, const=True)
+metric.add_argument('-d', '--direction', action='store_const', help='Plot direction prediction (2-bit, Gshare, local, etc) performance.', default=False, const=True)
+metric.add_argument('-t', '--target', action='store_const', help='Plot branch target buffer (BTB) performance.', default=False, const=True)
+metric.add_argument('-c', '--iclass', action='store_const', help='Plot instruction classification performance.', default=False, const=True)
+
+parser.add_argument('-s', '--summary', action='store_const', help='Show only the geometric average for all benchmarks.', default=False, const=True)
+parser.add_argument('-b', '--bar', action='store_const', help='Plot graphs.', default=False, const=True)
+parser.add_argument('-g', '--reference', action='store_const', help='Include the golden reference model from branch-predictor-simulator. Data stored statically at the top of %(prog)s.  If you need to regenreate use CModelBranchAcurracy.sh', default=False, const=True)
+parser.add_argument('-i', '--invert', action='store_const', help='Invert metric. Example Branch miss prediction becomes prediction accuracy. 100 - miss rate', default=False, const=True)
+
+displayMode = parser.add_mutually_exclusive_group()
+displayMode.add_argument('--text', action='store_const', help='Display in text format only.', default=False, const=True)
+displayMode.add_argument('--table', action='store_const', help='Display in text format only.', default=False, const=True)
+displayMode.add_argument('--gui', action='store_const', help='Display in text format only.', default=False, const=True)
+displayMode.add_argument('--debug', action='store_const', help='Display in text format only.', default=False, const=True)
+parser.add_argument('sources', nargs=1)
+
+args = parser.parse_args()
+
+# Figure what we are reporting
+ReportPredictorType = 'BDMR'  # default
+if(args.ras): ReportPredictorType = 'RASMPR'
+if(args.target): ReportPredictorType = 'BTMR'
+if(args.iclass): ReportPredictorType = 'ClassMPR'
+
+# Figure how we are displaying the data
+ReportMode = 'gui' # default
+if(args.text): ReportMode = 'text'
+if(args.table): ReportMode = 'table'
+if(args.debug): ReportMode = 'debug'
+
+# read the questa sim list file.
+# row, col format.  each row is a questa sim run with performance counters and a particular
+# branch predictor type and size. size can be multiple parameters for more complex predictors like
+# local history and tage.
+# <file> <type> <size>
+predictorLogs = ParseBranchListFile(args.sources[0])          # digests the traces
+performanceCounterList = BuildDataBase(predictorLogs)         # builds a database of performance counters by trace and then by benchmark
+benchmarkFirstList = ReorderDataBase(performanceCounterList)  # reorder first by benchmark then trace
+benchmarkDict = ExtractSelectedData(benchmarkFirstList)       # filters to just the desired performance counter metric
+
+if(args.reference): benchmarkDict['Mean'].extend(RefData)
+#print(benchmarkDict['Mean'])
+#print(benchmarkDict['aha-mont64Speed'])
+#print(benchmarkDict)
+
+# table format
+if(ReportMode == 'table'):
+    ReportAsTable(benchmarkDict)
+
+if(ReportMode == 'text'):
+    ReportAsText(benchmarkDict)
+
+if(ReportMode == 'gui'):
+    ReportAsGraph(benchmarkDict, args.bar)
+            
+# *** this is only needed of -b (no -s)
+
+# debug
+#config0 = performanceCounterList[0][0]
+#data0 = performanceCounterList[0][1]
+#bench0 = data0[0]
+#bench0name = bench0[0]
+#bench0data = bench0[2]
+#bench0BrCount = bench0data['Br Count']
+#bench1 = data0[1]
+
+#print(data0)
+#print(bench0)
+#print(bench1)
+
+#print(bench0name)
+#print(bench0BrCount)
diff --git a/bin/parseTest.py b/bin/parseTest.py
deleted file mode 100755
index bb6d2871e..000000000
--- a/bin/parseTest.py
+++ /dev/null
@@ -1,470 +0,0 @@
-#!/usr/bin/python3
-
-###########################################
-## Written: Rose Thompson ross1728@gmail.com
-## Created: 20 September 2023
-## Modified: 
-##
-## Purpose: Parses the performance counters from a modelsim trace.
-##
-## A component of the CORE-V-WALLY configurable RISC-V project.
-##
-## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-## may obtain a copy of the License at
-##
-## https:##solderpad.org/licenses/SHL-2.1/
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the 
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-## either express or implied. See the License for the specific language governing permissions 
-## and limitations under the License.
-################################################################################################
-
-import os
-import sys
-import matplotlib.pyplot as plt
-import math
-import numpy as np
-import argparse
-
-RefData = [('twobitCModel6', 'twobitCModel', 64, 9.65280765420711), ('twobitCModel8', 'twobitCModel', 256, 8.75120245829945), ('twobitCModel10', 'twobitCModel', 1024, 8.1318382397263),
-           ('twobitCModel12', 'twobitCModel', 4096, 7.53026646633342), ('twobitCModel14', 'twobitCModel', 16384, 6.07679338544009), ('twobitCModel16', 'twobitCModel', 65536, 6.07679338544009),
-           ('gshareCModel6', 'gshareCModel', 64, 10.6602835418646), ('gshareCModel8', 'gshareCModel', 256, 8.38384710559667), ('gshareCModel10', 'gshareCModel', 1024, 6.36847432155534),
-           ('gshareCModel12', 'gshareCModel', 4096, 3.91108491151983), ('gshareCModel14', 'gshareCModel', 16384, 2.83926519215395), ('gshareCModel16', 'gshareCModel', 65536, .60213659066941)]
-
-def ParseBranchListFile(path):
-    '''Take the path to the list of Questa Sim log files containing the performance counters outputs.  File
-    is formated in row columns.  Each row is a trace with the file, branch predictor type, and the parameters.
-    parameters can be any number and depend on the predictor type. Returns a list of lists.'''
-    lst = []
-    BranchList = open(path, 'r')
-    for line in BranchList:
-        tokens = line.split()
-        predictorLog = os.path.dirname(path) + '/' + tokens[0]
-        predictorType = tokens[1]
-        predictorParams = tokens[2::]
-        lst.append([predictorLog, predictorType, predictorParams])
-        #print(predictorLog, predictorType, predictorParams)
-    return lst
-    
-def ProcessFile(fileName):
-    '''Extract preformance counters from a modelsim log.  Outputs a list of tuples for each test/benchmark.
-    The tuple contains the test name, optimization characteristics, and dictionary of performance counters.'''
-    # 1 find lines with Read memfile and extract test name
-    # 2 parse counters into a list of (name, value) tuples (dictionary maybe?)
-    benchmarks = []
-    transcript = open(fileName, 'r')
-    HPMClist = { }
-    testName = ''
-    for line in transcript.readlines():
-        lineToken = line.split()
-        if(len(lineToken) > 3 and lineToken[1] == 'Read' and lineToken[2] == 'memfile'):
-            opt = lineToken[3].split('/')[-4]
-            testName = lineToken[3].split('/')[-1].split('.')[0]
-            HPMClist = { }
-        elif(len(lineToken) > 4 and lineToken[1][0:3] == 'Cnt'):
-            countToken = line.split('=')[1].split()
-            value = int(countToken[0]) if countToken[0] != 'x' else 0
-            name = ' '.join(countToken[1:])
-            HPMClist[name] = value
-        elif ('is done' in line):
-            benchmarks.append((testName, opt, HPMClist))
-    return benchmarks
-
-
-def ComputeStats(benchmarks):
-    for benchmark in benchmarks:
-        (nameString, opt, dataDict) = benchmark
-        dataDict['CPI'] = 1.0 * int(dataDict['Mcycle']) / int(dataDict['InstRet'])
-        dataDict['BDMR'] = 100.0 * int(dataDict['BP Dir Wrong']) / int(dataDict['Br Count'])
-        dataDict['BTMR'] = 100.0 * int(dataDict['BP Target Wrong']) / (int(dataDict['Br Count']) + int(dataDict['Jump Not Return']))
-        dataDict['RASMPR'] = 100.0 * int(dataDict['RAS Wrong']) / int(dataDict['Return'])
-        dataDict['ClassMPR'] = 100.0 * int(dataDict['Instr Class Wrong']) / int(dataDict['InstRet'])
-        dataDict['ICacheMR'] = 100.0 * int(dataDict['I Cache Miss']) / int(dataDict['I Cache Access'])
-
-        cycles = int(dataDict['I Cache Miss'])
-        if(cycles == 0): ICacheMR = 0
-        else: ICacheMR = 100.0 * int(dataDict['I Cache Cycles']) / cycles
-        dataDict['ICacheMT'] = ICacheMR
-
-        dataDict['DCacheMR'] = 100.0 * int(dataDict['D Cache Miss']) / int(dataDict['D Cache Access'])
-
-        (nameString, opt, dataDict) = benchmark
-        cycles = int(dataDict['D Cache Miss'])
-        if(cycles == 0): DCacheMR = 0
-        else: DCacheMR = 100.0 * int(dataDict['D Cache Cycles']) / cycles
-        dataDict['DCacheMT'] = DCacheMR
-
-
-def ComputeGeometricAverage(benchmarks):
-    fields = ['BDMR', 'BTMR', 'RASMPR', 'ClassMPR', 'ICacheMR', 'DCacheMR', 'CPI', 'ICacheMT', 'DCacheMT']
-    AllAve = {}
-    for field in fields:
-        Product = 1
-        index = 0
-        for (testName, opt, HPMCList) in benchmarks:
-            #print(HPMCList)
-            value = HPMCList[field]
-            if(value != 0): Product *= value # if that value is 0 exclude from mean because it destories the geo mean
-            index += 1
-        AllAve[field] = Product ** (1.0/index)
-    benchmarks.append(('Mean', '', AllAve))
-
-def GenerateName(predictorType, predictorParams):
-    if(predictorType == 'gshare' or  predictorType == 'twobit' or predictorType == 'btb' or predictorType == 'class' or predictorType == 'ras'):
-        return predictorType + predictorParams[0]
-    elif(predictorParams == 'local'):
-        return predictorType + predictorParams[0] + '_' + predictorParams[1]
-    else:
-        print(f'Error unsupported predictor type {predictorType}')
-        sys.exit(-1)
-
-def ComputePredNumEntries(predictorType, predictorParams):
-    if(predictorType == 'gshare' or  predictorType == 'twobit' or predictorType == 'btb' or predictorType == 'class'):
-        return 2**int(predictorParams[0])
-    elif(predictorType == 'ras'):
-        return int(predictorParams[0])
-    elif(predictorParams == 'local'):
-        return 2**int(predictorParams[0]) * int(predictorParams[1]) + 2**int(predictorParams[1])
-    else:
-        print(f'Error unsupported predictor type {predictorType}')
-        sys.exit(-1)
-
-def BuildDataBase(predictorLogs):
-    # Once done with the following loop, performanceCounterList will contain the predictor type and size along with the
-    # raw performance counter data and the processed data on a per benchmark basis.  It also includes the geometric mean.
-    # list
-    #   branch predictor configuration 0 (tuple)
-    #     benchmark name
-    #     compiler optimization
-    #     data (dictionary)
-    #       dictionary of performance counters
-    #   branch predictor configuration 1 (tuple)
-    #     benchmark name (dictionary)
-    #     compiler optimization
-    #     data
-    #       dictionary of performance counters
-    # ...
-    performanceCounterList = []
-    for trace in predictorLogs:
-        predictorLog = trace[0]
-        predictorType = trace[1]
-        predictorParams = trace[2]
-        # Extract the performance counter data
-        performanceCounters = ProcessFile(predictorLog)
-        ComputeStats(performanceCounters)
-        ComputeGeometricAverage(performanceCounters)
-        #print(performanceCounters)
-        performanceCounterList.append([GenerateName(predictorType, predictorParams), predictorType, performanceCounters, ComputePredNumEntries(predictorType, predictorParams)])
-    return performanceCounterList
-
-def ReorderDataBase(performanceCounterList):
-    # Reorder the data so the benchmark name comes first, then the branch predictor configuration
-    benchmarkFirstList = []
-    for (predictorName, predictorPrefixName, benchmarks, entries) in performanceCounterList:
-        for benchmark in benchmarks:
-            (nameString, opt, dataDict) = benchmark
-            benchmarkFirstList.append((nameString, opt, predictorName, predictorPrefixName, entries, dataDict))
-    return benchmarkFirstList
-
-def ExtractSelectedData(benchmarkFirstList):
-    # now extract all branch prediction direction miss rates for each
-    # namestring + opt, config
-    benchmarkDict = { }
-    for benchmark in benchmarkFirstList:
-        (name, opt, config, prefixName, entries, dataDict) = benchmark
-        if opt == 'bd_speedopt_speed': NewName = name+'Sp'
-        elif opt == 'bd_sizeopt_speed': NewName = name+'Sz'
-        else: NewName = name
-        #print(NewName)
-        #NewName = name+'_'+opt
-        if NewName in benchmarkDict:
-            benchmarkDict[NewName].append((config, prefixName, entries, dataDict[ReportPredictorType]))
-        else:
-            benchmarkDict[NewName] = [(config, prefixName, entries, dataDict[ReportPredictorType])]
-    return benchmarkDict
-
-def ReportAsTable(benchmarkDict):
-    refLine = benchmarkDict['Mean']
-    FirstLine = []
-    SecondLine = []
-    for (name, typ, size, val) in refLine:
-        FirstLine.append(name)
-        SecondLine.append(size)
-
-    sys.stdout.write('benchmark\t\t')
-    for name in FirstLine:
-        if(len(name) < 8): sys.stdout.write('%s\t\t' % name)
-        else: sys.stdout.write('%s\t' % name)        
-    sys.stdout.write('\n')
-    sys.stdout.write('size\t\t\t')
-    for size in SecondLine:
-        if(len(str(size)) < 8): sys.stdout.write('%d\t\t' % size)
-        else: sys.stdout.write('%d\t' % size)        
-    sys.stdout.write('\n')
-
-    if(args.summary):
-        sys.stdout.write('Mean\t\t\t')
-        for (name, typ, size, val) in refLine:
-            sys.stdout.write('%0.2f\t\t' % (val if not args.invert else 100 - val))
-        sys.stdout.write('\n')
-
-    if(not args.summary):
-        for benchmark in benchmarkDict:
-            length = len(benchmark)
-            if(length < 8): sys.stdout.write('%s\t\t\t' % benchmark)
-            elif(length < 16): sys.stdout.write('%s\t\t' % benchmark)
-            else: sys.stdout.write('%s\t' % benchmark)
-            for (name, typ, size, val) in benchmarkDict[benchmark]:
-                sys.stdout.write('%0.2f\t\t' % (val if not args.invert else 100 -val))
-            sys.stdout.write('\n')
-
-def ReportAsText(benchmarkDict):
-    if(args.summary):
-        mean = benchmarkDict['Mean']
-        print('Mean')
-        for (name, typ, size, val) in mean:
-            sys.stdout.write('%s %s %0.2f\n' % (name, size, val if not args.invert else 100 - val))
-        
-    if(not args.summary):
-        for benchmark in benchmarkDict:
-            print(benchmark)
-            for (name, type, size, val) in benchmarkDict[benchmark]:
-                sys.stdout.write('%s %s %0.2f\n' % (name, size, val if not args.invert else 100 - val))
-
-def Inversion(lst):
-    return [x if not args.invert else 100 - x for x in lst]
-
-def BarGraph(seriesDict, xlabelList, BenchPerRow, FileName):
-    index = 0
-    NumberInGroup = len(seriesDict)
-    # Figure out width of bars.  NumberInGroup bars + want 2 bar space
-    # the space between groups is 1
-    EffectiveNumInGroup = NumberInGroup + 2
-    barWidth = 1 / EffectiveNumInGroup
-    fig = plt.subplots(figsize = (EffectiveNumInGroup*BenchPerRow/8, 4))
-    colors = ['blue', 'blue', 'blue', 'blue', 'blue', 'blue', 'black', 'black', 'black', 'black', 'black', 'black']
-    for name in seriesDict:
-        xpos = np.arange(BenchPerRow)
-        xpos = [x + index*barWidth for x in xpos]
-        values = seriesDict[name]
-        plt.bar(xpos, Inversion(values), width=barWidth, edgecolor='grey', label=name, color=colors[index%len(colors)])
-        index += 1
-    plt.xticks([r + barWidth*(NumberInGroup/2-0.5) for r in range(0, BenchPerRow)], xlabelList)
-    plt.xlabel('Benchmark')
-    if(not args.invert): plt.ylabel('Misprediction Rate (%)')
-    else:  plt.ylabel('Prediction Accuracy (%)') 
-    plt.legend(loc='upper left', ncol=2)
-    plt.savefig(FileName)
-
-def SelectPartition(xlabelListBig, seriesDictBig, group, BenchPerRow):
-    seriesDictTrunk = {}
-    for benchmarkName in seriesDictBig:
-        lst = seriesDictBig[benchmarkName]
-        seriesDictTrunk[benchmarkName] = lst[group*BenchPerRow:(group+1)*BenchPerRow]
-    xlabelListTrunk = xlabelListBig[group*BenchPerRow:(group+1)*BenchPerRow]
-    return(xlabelListTrunk, seriesDictTrunk)
-
-
-def ReportAsGraph(benchmarkDict, bar):
-    def FormatToPlot(currBenchmark):
-        names = []
-        sizes = []
-        values = []
-        typs = []
-        for config in currBenchmark:
-            names.append(config[0])
-            sizes.append(config[1])
-            values.append(config[2])
-            typs.append(config[3])
-        return (names, sizes, values, typs)
-    titlesInvert = {'BDMR' : 'Branch Direction Accuracy',
-              'BTMR' : 'Branch Target Accuracy',
-              'RASMPR': 'RAS Accuracy',
-              'ClassMPR': 'Class Prediction Accuracy'}
-    titles = {'BDMR' : 'Branch Direction Misprediction',
-              'BTMR' : 'Branch Target Misprediction',
-              'RASMPR': 'RAS Misprediction',
-              'ClassMPR': 'Class Misprediction'}
-    if(args.summary):
-        markers = ['x', '.', '+', '*', '^', 'o', ',', 's']
-        colors = ['blue', 'black', 'gray', 'dodgerblue', 'lightsteelblue', 'turquoise', 'black', 'blue']
-        temp = benchmarkDict['Mean']
-
-        # the benchmarkDict['Mean'] contains sequencies of results for multiple
-        # branch predictors with various parameterizations
-        # group the parameterizations by the common typ.
-        sequencies = {}
-        for (name, typ, size, value) in benchmarkDict['Mean']:
-            if not typ in sequencies:
-                sequencies[typ] = [(size, value)]
-            else:
-                sequencies[typ].append((size,value))
-        # then graph the common typ as a single line+scatter plot
-        # finally repeat for all typs of branch predictors and overlay
-        fig, axes = plt.subplots()
-        index = 0
-        if(args.invert): plt.title(titlesInvert[ReportPredictorType])
-        else: plt.title(titles[ReportPredictorType])
-        for branchPredName in sequencies:
-            data = sequencies[branchPredName]
-            (xdata, ydata) = zip(*data) 
-            if args.invert: ydata = [100 - x for x in ydata]
-            axes.plot(xdata, ydata, color=colors[index])
-            axes.scatter(xdata, ydata, label=branchPredName, color=colors[index], marker=markers[index])
-            index = (index + 1) % len(markers)
-        axes.legend(loc='upper left')
-        axes.set_xscale("log")
-        axes.set_ylabel('Prediction Accuracy')
-        axes.set_xlabel('Entries')
-        axes.set_xticks(xdata)
-        axes.set_xticklabels(xdata)
-        axes.grid(color='b', alpha=0.5, linestyle='dashed', linewidth=0.5)
-        plt.show()
-        
-
-    # if(not args.summary):
-    #     size = len(benchmarkDict)
-    #     sizeSqrt = math.sqrt(size)
-    #     isSquare = math.isclose(sizeSqrt, round(sizeSqrt))
-    #     numCol = math.floor(sizeSqrt)
-    #     numRow = numCol + (0 if isSquare else 1)
-    #     index = 1
-    #     fig = plt.figure()
-    #     for benchmarkName in benchmarkDict:
-    #         currBenchmark = benchmarkDict[benchmarkName]
-    #         (names, typs, sizes, values) = FormatToPlot(currBenchmark)
-    #         #axes.plot(numRow, numCol, index)
-    #         ax = fig.add_subplot(numRow, numCol, index)
-    #         ax.bar(names, values)
-    #         ax.title.set_text(benchmarkName)
-    #         #plt.ylabel('BR Dir Miss Rate (%)')
-    #         #plt.xlabel('Predictor')
-    #         index += 1
-
-    if(not args.summary):
-        size = len(benchmarkDict)
-        sizeSqrt = math.sqrt(size)
-        isSquare = math.isclose(sizeSqrt, round(sizeSqrt))
-        numCol = math.floor(sizeSqrt)
-        numRow = numCol + (0 if isSquare else 1)
-        index = 1
-        BenchPerRow = 7
-
-        xlabelList = []
-        seriesDict = {}
-
-        for benchmarkName in benchmarkDict:
-            currBenchmark = benchmarkDict[benchmarkName]
-            xlabelList.append(benchmarkName)
-            for (name, typ, size, value) in currBenchmark:
-                if(name not in seriesDict):
-                    seriesDict[name] = [value]
-                else:
-                    seriesDict[name].append(value)
-            if(index >= BenchPerRow): break
-            index += 1
-
-        xlabelListBig = []
-        seriesDictBig = {}
-        for benchmarkName in benchmarkDict:
-            currBenchmark = benchmarkDict[benchmarkName]
-            xlabelListBig.append(benchmarkName)
-            for (name, typ, size, value) in currBenchmark:
-                if(name not in seriesDictBig):
-                    seriesDictBig[name] = [value]
-                else:
-                    seriesDictBig[name].append(value)
-
-        #The next step will be to split the benchmarkDict into length BenchPerRow pieces then repeat the following code
-        # on each piece.
-        for row in range(0, math.ceil(39 / BenchPerRow)):
-            (xlabelListTrunk, seriesDictTrunk) = SelectPartition(xlabelListBig, seriesDictBig, row, BenchPerRow)
-            FileName = 'barSegment%d.png' % row
-            groupLen = len(xlabelListTrunk)
-            BarGraph(seriesDictTrunk, xlabelListTrunk, groupLen, FileName)
-
-
-# main
-parser = argparse.ArgumentParser(description='Parses performance counters from a Questa Sim trace to produce a graph or graphs.')
-
-# parse program arguments
-metric = parser.add_mutually_exclusive_group()
-metric.add_argument('-r', '--ras', action='store_const', help='Plot return address stack (RAS) performance.', default=False, const=True)
-metric.add_argument('-d', '--direction', action='store_const', help='Plot direction prediction (2-bit, Gshare, local, etc) performance.', default=False, const=True)
-metric.add_argument('-t', '--target', action='store_const', help='Plot branch target buffer (BTB) performance.', default=False, const=True)
-metric.add_argument('-c', '--iclass', action='store_const', help='Plot instruction classification performance.', default=False, const=True)
-
-parser.add_argument('-s', '--summary', action='store_const', help='Show only the geometric average for all benchmarks.', default=False, const=True)
-parser.add_argument('-b', '--bar', action='store_const', help='Plot graphs.', default=False, const=True)
-parser.add_argument('-g', '--reference', action='store_const', help='Include the golden reference model from branch-predictor-simulator. Data stored statically at the top of %(prog)s.  If you need to regenreate use CModelBranchAcurracy.sh', default=False, const=True)
-parser.add_argument('-i', '--invert', action='store_const', help='Invert metric. Example Branch miss prediction becomes prediction accuracy. 100 - miss rate', default=False, const=True)
-
-displayMode = parser.add_mutually_exclusive_group()
-displayMode.add_argument('--text', action='store_const', help='Display in text format only.', default=False, const=True)
-displayMode.add_argument('--table', action='store_const', help='Display in text format only.', default=False, const=True)
-displayMode.add_argument('--gui', action='store_const', help='Display in text format only.', default=False, const=True)
-displayMode.add_argument('--debug', action='store_const', help='Display in text format only.', default=False, const=True)
-parser.add_argument('sources', nargs=1)
-
-args = parser.parse_args()
-
-# Figure what we are reporting
-ReportPredictorType = 'BDMR'  # default
-if(args.ras): ReportPredictorType = 'RASMPR'
-if(args.target): ReportPredictorType = 'BTMR'
-if(args.iclass): ReportPredictorType = 'ClassMPR'
-
-# Figure how we are displaying the data
-ReportMode = 'gui' # default
-if(args.text): ReportMode = 'text'
-if(args.table): ReportMode = 'table'
-if(args.debug): ReportMode = 'debug'
-
-# read the questa sim list file.
-# row, col format.  each row is a questa sim run with performance counters and a particular
-# branch predictor type and size. size can be multiple parameters for more complex predictors like
-# local history and tage.
-# <file> <type> <size>
-predictorLogs = ParseBranchListFile(args.sources[0])          # digests the traces
-performanceCounterList = BuildDataBase(predictorLogs)         # builds a database of performance counters by trace and then by benchmark
-benchmarkFirstList = ReorderDataBase(performanceCounterList)  # reorder first by benchmark then trace
-benchmarkDict = ExtractSelectedData(benchmarkFirstList)       # filters to just the desired performance counter metric
-
-if(args.reference): benchmarkDict['Mean'].extend(RefData)
-#print(benchmarkDict['Mean'])
-#print(benchmarkDict['aha-mont64Speed'])
-#print(benchmarkDict)
-
-# table format
-if(ReportMode == 'table'):
-    ReportAsTable(benchmarkDict)
-
-if(ReportMode == 'text'):
-    ReportAsText(benchmarkDict)
-
-if(ReportMode == 'gui'):
-    ReportAsGraph(benchmarkDict, args.bar)
-            
-# *** this is only needed of -b (no -s)
-
-# debug
-#config0 = performanceCounterList[0][0]
-#data0 = performanceCounterList[0][1]
-#bench0 = data0[0]
-#bench0name = bench0[0]
-#bench0data = bench0[2]
-#bench0BrCount = bench0data['Br Count']
-#bench1 = data0[1]
-
-#print(data0)
-#print(bench0)
-#print(bench1)
-
-#print(bench0name)
-#print(bench0BrCount)

From 1852304a2a2f79ef55028f47f6d8ae06c817b455 Mon Sep 17 00:00:00 2001
From: "James E. Stine" <james.stine@okstate.edu>
Date: Tue, 3 Oct 2023 08:00:00 -0500
Subject: [PATCH 21/32] Update install script for working SAIL checkout
 (current version)

---
 bin/wally-tool-chain-install.sh | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh
index cc6254079..7ff470f17 100755
--- a/bin/wally-tool-chain-install.sh
+++ b/bin/wally-tool-chain-install.sh
@@ -120,8 +120,8 @@ sudo apt-get install -y perl g++ ccache help2man libgoogle-perftools-dev numactl
 sudo apt-get install -y libfl2  libfl-dev  # Ubuntu only (ignore if gives error)
 cd $RISCV
 git clone https://github.com/verilator/verilator   # Only first time
-unsetenv VERILATOR_ROOT  # For csh; ignore error if on bash
-unset VERILATOR_ROOT  # For bash
+# unsetenv VERILATOR_ROOT  # For csh; ignore error if on bash
+unset VERILATOR_ROOT     # For bash
 cd verilator
 git pull         # Make sure git repository is up-to-date
 git checkout master      # Use development branch (e.g. recent bug fixes)
@@ -157,6 +157,8 @@ opam install sail -y
 eval $(opam config env)
 git clone https://github.com/riscv/sail-riscv.git
 cd sail-riscv
+# For now, use checkout that is stable for Wally
+git checkout 72b2516d10d472ac77482fd959a9401ce3487f60
 make -j ${NUM_THREADS}
 ARCH=RV32 make -j ${NUM_THREADS}
 sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64

From 2d6b5d30004bdaa235fc6ce2e4e3434a84402534 Mon Sep 17 00:00:00 2001
From: "James E. Stine" <james.stine@okstate.edu>
Date: Tue, 3 Oct 2023 08:02:39 -0500
Subject: [PATCH 22/32] Modify Makefile + software example for SP/DP/QP

---
 examples/fp/softfloat_demo/Makefile           | 11 +--
 examples/fp/softfloat_demo/softfloat_demo2.c  | 77 ----------------
 examples/fp/softfloat_demo/softfloat_demoDP.c | 88 ++++++++++++++++++
 examples/fp/softfloat_demo/softfloat_demoQP.c | 91 +++++++++++++++++++
 examples/fp/softfloat_demo/softfloat_demoSP.c | 88 ++++++++++++++++++
 5 files changed, 272 insertions(+), 83 deletions(-)
 delete mode 100644 examples/fp/softfloat_demo/softfloat_demo2.c
 create mode 100644 examples/fp/softfloat_demo/softfloat_demoDP.c
 create mode 100644 examples/fp/softfloat_demo/softfloat_demoQP.c
 create mode 100644 examples/fp/softfloat_demo/softfloat_demoSP.c

diff --git a/examples/fp/softfloat_demo/Makefile b/examples/fp/softfloat_demo/Makefile
index 4d0efe20e..cc98d0cfb 100644
--- a/examples/fp/softfloat_demo/Makefile
+++ b/examples/fp/softfloat_demo/Makefile
@@ -2,14 +2,13 @@
 
 CC     = gcc
 CFLAGS = -O3
-LIBS   = -lm
 LFLAGS = -L. 
 # Link against the riscv-isa-sim version of SoftFloat rather than 
 # the regular version to get RISC-V NaN behavior
-IFLAGS   = -I$(RISCV)/riscv-isa-sim/softfloat
-LIBS   = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a
-#IFLAGS = -I../../../addins/SoftFloat-3e/source/include/
-#LIBS   = ../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a
+#IFLAGS   = -I$(RISCV)/riscv-isa-sim/softfloat
+#LIBS   = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a
+IFLAGS = -I../../../addins/SoftFloat-3e/source/include/
+LIBS   = ../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a -lm -lquadmath
 SRCS   = $(wildcard *.c)
 
 PROGS = $(patsubst %.c,%,$(SRCS))
@@ -17,7 +16,7 @@ PROGS = $(patsubst %.c,%,$(SRCS))
 all:	$(PROGS)
 
 %: %.c
-	$(CC) $(CFLAGS) $(IFLAGS) $(LFLAGS) -o $@ $< $(LIBS)
+	$(CC) $(CFLAGS) -DSOFTFLOAT_FAST_INT64 $(IFLAGS) $(LFLAGS) -o $@ $< $(LIBS)
 
 clean: 
 	rm -f $(PROGS)
diff --git a/examples/fp/softfloat_demo/softfloat_demo2.c b/examples/fp/softfloat_demo/softfloat_demo2.c
deleted file mode 100644
index d0582724c..000000000
--- a/examples/fp/softfloat_demo/softfloat_demo2.c
+++ /dev/null
@@ -1,77 +0,0 @@
-//
-// softfloat_div.c
-// james.stine@okstate.edu 12 April 2023
-// 
-// Demonstrate using SoftFloat to compute 754 fp divide, then print results
-// (adapted from original C built by David Harris)
-//
-
-#include <stdio.h>
-#include <stdint.h>
-#include "softfloat.h"
-#include "softfloat_types.h"
-typedef union sp {
-  uint32_t v;
-  unsigned short x[2];
-  float f;
-} sp;
-
-void printF32 (char *msg, float32_t f) {
-  sp conv;
-  int i, j;
-  conv.v = f.v; // use union to convert between hexadecimal and floating-point views
-  printf("%s: ", msg);  // print out nicely
-  printf("0x%04x_%04x = %1.15g\n", (conv.v >> 16),(conv.v & 0xFFFF), conv.f);
-}
-
-void printFlags(void) {
-  int NX = softfloat_exceptionFlags % 2;
-  int UF = (softfloat_exceptionFlags >> 1) % 2;
-  int OF = (softfloat_exceptionFlags >> 2) % 2;
-  int DZ = (softfloat_exceptionFlags >> 3) % 2;
-  int NV = (softfloat_exceptionFlags >> 4) % 2;
-  printf ("Flags: Inexact %d Underflow %d Overflow %d DivideZero %d Invalid %d\n", 
-          NX, UF, OF, DZ, NV);
-}
-
-void softfloatInit(void) {
-    // RNE: softfloat_round_near_even
-    // RZ:  softfloat_round_minMag
-    // RU:  softfloat_round_max
-    // RD:  softfloat_round_min
-    // RM: softfloat_round_near_maxMag   
-    softfloat_roundingMode = softfloat_round_near_even; 
-    softfloat_exceptionFlags = 0; // clear exceptions
-    softfloat_detectTininess = softfloat_tininess_afterRounding; // RISC-V behavior for tininess
-}
-
-int main() {
-
-  // float32_t is typedef in SoftFloat
-  float32_t x, y, r1, r2;
-  sp convx, convy;
-
-  // Choose two random values
-  convx.f = 1.30308703073;
-  convy.f = 1.903038030370;
-  // Convert to SoftFloat format
-  x.v = (convx.x[1] << 16) + convx.x[0];
-  y.v = (convy.x[1] << 16) + convy.x[0];  
-
-  printf("Example using SoftFloat\n");
-  
-  softfloatInit();
-  r1 = f32_div(x, y);
-  printf("-------\n");
-  printF32("X", x);
-  printF32("Y", y); 
-  printF32("result = X/Y", r1);
-  printFlags();
-
-  r2 = f32_sqrt(x);
-  printf("-------\n");    
-  printF32("X", x);
-  printF32("result = sqrt(X)", r2);
-  printFlags();  
-
-}
diff --git a/examples/fp/softfloat_demo/softfloat_demoDP.c b/examples/fp/softfloat_demo/softfloat_demoDP.c
new file mode 100644
index 000000000..50b3d0b53
--- /dev/null
+++ b/examples/fp/softfloat_demo/softfloat_demoDP.c
@@ -0,0 +1,88 @@
+// softfloat_demo3.c
+// james.stine@okstate.edu 15 August 2023
+// 
+// Demonstrate using SoftFloat do compute a floating-point for quad, then print results
+
+#include <stdio.h>
+#include <stdint.h>
+#include <inttypes.h>
+#include <quadmath.h> // GCC Quad-Math Library
+#include "softfloat.h"
+#include "softfloat_types.h"
+typedef union sp {
+  uint32_t v;
+  float f;
+} sp;
+
+typedef union dp {
+  uint64_t v;
+  double d;
+} dp;
+
+typedef union qp {
+  uint64_t v[2];
+  __float128 q;
+} qp;
+
+
+void printF32 (char *msg, float32_t f) {
+  sp conv;
+  int i, j;
+  conv.v = f.v; // use union to convert between hexadecimal and floating-point views
+  printf("%s: ", msg);  // print out nicely
+  printf("0x%04x_%04x = %g\n", (conv.v >> 16),(conv.v & 0xFFFF), conv.f);
+}
+
+void printF64 (char *msg, float64_t d) {
+  dp conv;
+  int i, j;
+  conv.v = d.v; // use union to convert between hexadecimal and floating-point views
+  printf("%s: ", msg);  // print out nicely
+  printf("0x%08x_%08x = %g\n", (conv.v >> 32),(conv.v & 0xFFFFFFFF), conv.d);
+}
+
+void printF128 (char *msg, float128_t q) {
+  qp conv;
+  int i, j;
+  conv.v[0] = q.v[0]; // use union to convert between hexadecimal and floating-point views
+  conv.v[1] = q.v[1]; // use union to convert between hexadecimal and floating-point views  
+  printf("%s: ", msg);  // print out nicely
+  printf("0x%016" PRIx64 "_%016" PRIx64 " = %1.15Qe\n", q.v[1], q.v[0], conv.q);
+}
+
+void printFlags(void) {
+  int NX = softfloat_exceptionFlags % 2;
+  int UF = (softfloat_exceptionFlags >> 1) % 2;
+  int OF = (softfloat_exceptionFlags >> 2) % 2;
+  int DZ = (softfloat_exceptionFlags >> 3) % 2;
+  int NV = (softfloat_exceptionFlags >> 4) % 2;
+  printf ("Flags: Inexact %d Underflow %d Overflow %d DivideZero %d Invalid %d\n", 
+          NX, UF, OF, DZ, NV);
+}
+
+void softfloatInit(void) {
+    // rounding modes: RNE: softfloat_round_near_even
+    //                 RZ:  softfloat_round_minMag
+    //                 RP:  softfloat_round_max
+    //                 RM:  softfloat_round_min
+    softfloat_roundingMode = softfloat_round_near_even; 
+    softfloat_exceptionFlags = 0; // clear exceptions
+    softfloat_detectTininess = softfloat_tininess_afterRounding; // RISC-V behavior for tininess
+}
+
+int main() {
+  
+  float64_t x, y, z;
+  float64_t r;
+
+  x.v = 0xBFFF988ECE97DFEB;
+  y.v = 0x3F8EFFFFFFFFFFFF;
+  z.v = 0x4001000000000000;
+
+  softfloatInit();
+  printF64("X", x); printF64("Y", y); printF64("Z", z);
+  r = f64_mulAdd(x, y, z);
+  printf("\n");
+  printF64("r", r);
+  
+}
diff --git a/examples/fp/softfloat_demo/softfloat_demoQP.c b/examples/fp/softfloat_demo/softfloat_demoQP.c
new file mode 100644
index 000000000..03f0e5edb
--- /dev/null
+++ b/examples/fp/softfloat_demo/softfloat_demoQP.c
@@ -0,0 +1,91 @@
+// softfloat_demo3.c
+// james.stine@okstate.edu 15 August 2023
+// 
+// Demonstrate using SoftFloat do compute a floating-point for quad, then print results
+
+#include <stdio.h>
+#include <stdint.h>
+#include <inttypes.h>
+#include <quadmath.h> // GCC Quad-Math Library
+#include "softfloat.h"
+#include "softfloat_types.h"
+typedef union sp {
+  uint32_t v;
+  float f;
+} sp;
+
+typedef union dp {
+  uint64_t v;
+  double d;
+} dp;
+
+typedef union qp {
+  uint64_t v[2];
+  __float128 q;
+} qp;
+
+
+void printF32 (char *msg, float32_t f) {
+  sp conv;
+  int i, j;
+  conv.v = f.v; // use union to convert between hexadecimal and floating-point views
+  printf("%s: ", msg);  // print out nicely
+  printf("0x%04x_%04x = %g\n", (conv.v >> 16),(conv.v & 0xFFFF), conv.f);
+}
+
+void printF64 (char *msg, float64_t d) {
+  dp conv;
+  int i, j;
+  conv.v = d.v; // use union to convert between hexadecimal and floating-point views
+  printf("%s: ", msg);  // print out nicely
+  printf("0x%08x_%08x = %g\n", (conv.v >> 32),(conv.v & 0xFFFFFFFF), conv.d);
+}
+
+void printF128 (char *msg, float128_t q) {
+  qp conv;
+  int i, j;
+  conv.v[0] = q.v[0]; // use union to convert between hexadecimal and floating-point views
+  conv.v[1] = q.v[1]; // use union to convert between hexadecimal and floating-point views  
+  printf("%s: ", msg);  // print out nicely
+  printf("0x%016" PRIx64 "_%016" PRIx64 " = %1.15Qe\n", q.v[1], q.v[0], conv.q);
+}
+
+void printFlags(void) {
+  int NX = softfloat_exceptionFlags % 2;
+  int UF = (softfloat_exceptionFlags >> 1) % 2;
+  int OF = (softfloat_exceptionFlags >> 2) % 2;
+  int DZ = (softfloat_exceptionFlags >> 3) % 2;
+  int NV = (softfloat_exceptionFlags >> 4) % 2;
+  printf ("Flags: Inexact %d Underflow %d Overflow %d DivideZero %d Invalid %d\n", 
+          NX, UF, OF, DZ, NV);
+}
+
+void softfloatInit(void) {
+    // rounding modes: RNE: softfloat_round_near_even
+    //                 RZ:  softfloat_round_minMag
+    //                 RP:  softfloat_round_max
+    //                 RM:  softfloat_round_min
+    softfloat_roundingMode = softfloat_round_near_even; 
+    softfloat_exceptionFlags = 0; // clear exceptions
+    softfloat_detectTininess = softfloat_tininess_afterRounding; // RISC-V behavior for tininess
+}
+
+int main() {
+  
+  float128_t x, y, z;
+  float128_t r;
+
+  x.v[1] = 0xBFFF988ECE97DFEB;
+  x.v[0] = 0xC3BBA082445B4836;
+  y.v[1] = 0x3F8EFFFFFFFFFFFF;
+  y.v[0] = 0xFFFFFFFFFFFFFFFF;
+  z.v[1] = 0x4001000000000000;
+  z.v[0] = 0x0000000000000000;
+
+  softfloatInit();
+  printF128("X", x); printF128("Y", y); printF128("Z", z);
+  r = f128_mulAdd(x, y, z);
+  printf("\n");
+  printF128("r", r);
+  
+}
diff --git a/examples/fp/softfloat_demo/softfloat_demoSP.c b/examples/fp/softfloat_demo/softfloat_demoSP.c
new file mode 100644
index 000000000..55c5ef991
--- /dev/null
+++ b/examples/fp/softfloat_demo/softfloat_demoSP.c
@@ -0,0 +1,88 @@
+// softfloat_demo3.c
+// james.stine@okstate.edu 15 August 2023
+// 
+// Demonstrate using SoftFloat do compute a floating-point for quad, then print results
+
+#include <stdio.h>
+#include <stdint.h>
+#include <inttypes.h>
+#include <quadmath.h> // GCC Quad-Math Library
+#include "softfloat.h"
+#include "softfloat_types.h"
+typedef union sp {
+  uint32_t v;
+  float f;
+} sp;
+
+typedef union dp {
+  uint64_t v;
+  double d;
+} dp;
+
+typedef union qp {
+  uint64_t v[2];
+  __float128 q;
+} qp;
+
+
+void printF32 (char *msg, float32_t f) {
+  sp conv;
+  int i, j;
+  conv.v = f.v; // use union to convert between hexadecimal and floating-point views
+  printf("%s: ", msg);  // print out nicely
+  printf("0x%04x_%04x = %g\n", (conv.v >> 16),(conv.v & 0xFFFF), conv.f);
+}
+
+void printF64 (char *msg, float64_t d) {
+  dp conv;
+  int i, j;
+  conv.v = d.v; // use union to convert between hexadecimal and floating-point views
+  printf("%s: ", msg);  // print out nicely
+  printf("0x%08x_%08x = %g\n", (conv.v >> 32),(conv.v & 0xFFFFFFFF), conv.d);
+}
+
+void printF128 (char *msg, float128_t q) {
+  qp conv;
+  int i, j;
+  conv.v[0] = q.v[0]; // use union to convert between hexadecimal and floating-point views
+  conv.v[1] = q.v[1]; // use union to convert between hexadecimal and floating-point views  
+  printf("%s: ", msg);  // print out nicely
+  printf("0x%016" PRIx64 "_%016" PRIx64 " = %1.15Qe\n", q.v[1], q.v[0], conv.q);
+}
+
+void printFlags(void) {
+  int NX = softfloat_exceptionFlags % 2;
+  int UF = (softfloat_exceptionFlags >> 1) % 2;
+  int OF = (softfloat_exceptionFlags >> 2) % 2;
+  int DZ = (softfloat_exceptionFlags >> 3) % 2;
+  int NV = (softfloat_exceptionFlags >> 4) % 2;
+  printf ("Flags: Inexact %d Underflow %d Overflow %d DivideZero %d Invalid %d\n", 
+          NX, UF, OF, DZ, NV);
+}
+
+void softfloatInit(void) {
+    // rounding modes: RNE: softfloat_round_near_even
+    //                 RZ:  softfloat_round_minMag
+    //                 RP:  softfloat_round_max
+    //                 RM:  softfloat_round_min
+    softfloat_roundingMode = softfloat_round_near_even; 
+    softfloat_exceptionFlags = 0; // clear exceptions
+    softfloat_detectTininess = softfloat_tininess_afterRounding; // RISC-V behavior for tininess
+}
+
+int main() {
+  
+  float32_t x, y, z;
+  float32_t r;
+
+  x.v = 0xBFFF988E;
+  y.v = 0x3F8EFFFF;
+  z.v = 0x40010000;
+
+  softfloatInit();
+  printF32("X", x); printF32("Y", y); printF32("Z", z);
+  r = f32_mulAdd(x, y, z);
+  printf("\n");
+  printF32("r", r);
+  
+}

From b342e15c0733317440589190040a82b107ebe315 Mon Sep 17 00:00:00 2001
From: "James E. Stine" <james.stine@okstate.edu>
Date: Tue, 3 Oct 2023 08:03:54 -0500
Subject: [PATCH 23/32] Add TeX files used for examples in textbook on divsqrt

---
 docs/divsqrt_tex/div2.aux  |   2 +
 docs/divsqrt_tex/div2.log  | 531 +++++++++++++++++++++++++++++++++++
 docs/divsqrt_tex/div2.pdf  | Bin 0 -> 110314 bytes
 docs/divsqrt_tex/div2.tex  | 123 ++++++++
 docs/divsqrt_tex/div4.aux  |   2 +
 docs/divsqrt_tex/div4.log  | 527 +++++++++++++++++++++++++++++++++++
 docs/divsqrt_tex/div4.pdf  | Bin 0 -> 88257 bytes
 docs/divsqrt_tex/div4.tex  |  84 ++++++
 docs/divsqrt_tex/sqrt2.aux |   2 +
 docs/divsqrt_tex/sqrt2.log | 557 +++++++++++++++++++++++++++++++++++++
 docs/divsqrt_tex/sqrt2.pdf | Bin 0 -> 105524 bytes
 docs/divsqrt_tex/sqrt2.tex | 385 +++++++++++++++++++++++++
 docs/divsqrt_tex/sqrt4.aux |   2 +
 docs/divsqrt_tex/sqrt4.log | 534 +++++++++++++++++++++++++++++++++++
 docs/divsqrt_tex/sqrt4.pdf | Bin 0 -> 75105 bytes
 docs/divsqrt_tex/sqrt4.tex | 147 ++++++++++
 16 files changed, 2896 insertions(+)
 create mode 100644 docs/divsqrt_tex/div2.aux
 create mode 100644 docs/divsqrt_tex/div2.log
 create mode 100644 docs/divsqrt_tex/div2.pdf
 create mode 100644 docs/divsqrt_tex/div2.tex
 create mode 100644 docs/divsqrt_tex/div4.aux
 create mode 100644 docs/divsqrt_tex/div4.log
 create mode 100644 docs/divsqrt_tex/div4.pdf
 create mode 100644 docs/divsqrt_tex/div4.tex
 create mode 100644 docs/divsqrt_tex/sqrt2.aux
 create mode 100644 docs/divsqrt_tex/sqrt2.log
 create mode 100644 docs/divsqrt_tex/sqrt2.pdf
 create mode 100644 docs/divsqrt_tex/sqrt2.tex
 create mode 100644 docs/divsqrt_tex/sqrt4.aux
 create mode 100644 docs/divsqrt_tex/sqrt4.log
 create mode 100644 docs/divsqrt_tex/sqrt4.pdf
 create mode 100644 docs/divsqrt_tex/sqrt4.tex

diff --git a/docs/divsqrt_tex/div2.aux b/docs/divsqrt_tex/div2.aux
new file mode 100644
index 000000000..a79beafe4
--- /dev/null
+++ b/docs/divsqrt_tex/div2.aux
@@ -0,0 +1,2 @@
+\relax 
+\gdef \@abspage@last{3}
diff --git a/docs/divsqrt_tex/div2.log b/docs/divsqrt_tex/div2.log
new file mode 100644
index 000000000..56ed865dc
--- /dev/null
+++ b/docs/divsqrt_tex/div2.log
@@ -0,0 +1,531 @@
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diff --git a/docs/divsqrt_tex/div2.tex b/docs/divsqrt_tex/div2.tex
new file mode 100644
index 000000000..03daaf1a8
--- /dev/null
+++ b/docs/divsqrt_tex/div2.tex
@@ -0,0 +1,123 @@
+\documentclass[12pt]{article}
+
+\usepackage{amssymb, amsmath, amsfonts, amsthm, graphicx, tcolorbox}
+
+\usepackage{arydshln}
+
+\parindent  = 0in
+
+\pagestyle{empty}
+
+%==========
+%==========
+
+\begin{document}
+
+\begin{center}
+\begin{tabular}{cccc}
+    Initialization&$D$&$0001.1010\ 000$&\\
+    &$-D=\overline{D}+1$&$1110.0101\ 111$&(+ 1 ulp)\\
+    &&&\\
+    &$WS_{-1}=X$&$0001.0000\ 010$&\\
+    &$WC_{-1}$&$0000.0000\ 000$&\\
+    \hdashline\\
+    Step 0:&$WS_{-1}$&$0001.0000\ 010$&\\
+    &$WC_{-1}$&$0000.0000\ 00\mathbf{1}$&($W_{msbs}=0001\ \text{so}\ q_0=1$)\\
+    &$-q_0D$&$1110.0101\ 111$&\\
+    \cline{2-3}
+    &$sum$&$1111.0101\ 100$&$\ll1$\\
+    &$carry$&$0000.0000\ 110$&$\ll1$\\
+    \hdashline\\
+    Step 1:&$WS_0$&$1110.1011\ 000$&\\
+    &$WC_0$&$0000.0001\ 10\mathbf{0}$&($W_{msbs}=1110\ \text{so}\ q_1=-1$)\\
+    &$-q_1D$&$0001.1010\ 000$&\\
+    \cline{2-3}
+    &$sum$&$1111.0000\ 100$&$\ll1$\\
+    &$carry$&$0001.0110\ 000$&$\ll1$\\
+    \hdashline\\
+    Step 2:&$WS_1$&$1110.0001\ 000$&\\
+    &$WC_1$&$0010.1100\ 00\mathbf{1}$&($W_{msbs}=0000\ \text{so}\ q_2=1$)\\
+    &$-q_2D$&$1110.0101\ 111$&\\
+    \cline{2-3}
+    &$sum$&$0010.1000\ 110$&$\ll1$\\
+    &$carry$&$1100.1010\ 010$&$\ll1$\\
+    \hdashline\\
+    Step 3:&$WS_2$&$0101.0001\ 100$&\\
+    &$WC_2$&$1001.0100\ 10\mathbf{0}$&($W_{msbs}=1110\ \text{so}\ q_3=-1$)\\
+    &$-q_3D$&$0001.1010\ 000$&\\
+    \cline{2-3}
+    &$sum$&$1101.1111\ 000$&\\
+    &$carry$&$0010.0001\ 000$&$sum+carry=0$, terminate.\\
+    \hdashline\\
+    Terminate&Quotient&0.101
+\end{tabular}
+\end{center}
+
+\vfill
+\eject
+
+X = 1.0110\ 011 (179/128)
+
+D = 1.0011\ 000 (152/128)
+
+Q = 1.0010\ 1101\ 0
+
+D[1.3] = 1.001, so we use the ``"1.001" column of chart 13.X. This means we select a quotient bit of 2 if the partial remainder is greater than or equal to 3.5, a quotient bit of 1 if the partial is greater or equal to than 1.0, a zero if the partial is greater than or equal to -1.5, -1 if the partial is greater than or equal to -3.75, and a -2 otherwise.
+\begin{center}
+\begin{tabular}{cccc}
+    Initialization&$D$&$0001.0011\ 000$&\\
+    &$2D$&$0010.0110\ 000$&\\
+    &$-D=\overline{D}+1$&$1110.1100\ 111$&(+ 1 ulp)\\
+    &$-2D=\overline{2D}+1$&$1101.1001\ 111$&(+ 1 ulp)\\
+    &&&\\
+    &$X=WS$&$0001.0110\ 011$&\\
+    &$WC$&$0000.0000\ 000$&\\
+    \hdashline\\
+    Step 4:&$WS$&$0001.0110\ 011$&\\
+    &$WC$&$0000.0000\ 00\mathbf{1}$&($RW_{msbs}=0001.010\ \text{so}\ q_4=1$)\\
+    &$-q_7D$&$1110.1100\ 111$&\\
+    \cline{2-3}
+    &$WS$&$1111.1010\ 101$&$\ll2$\\
+    &$WC$&$0000.1000\ 110$&$\ll2$\\
+    \hdashline\\
+    Step 3:&$WS$&$1110.1010\ 100$&\\
+    &$WC$&$0010.0011\ 000$&($RW_{msbs}=0000.110\ \text{so}\ q_3=1$)\\
+    &$-q_6D$&$0000.0000\ 000$&\\
+    \cline{2-3}
+    &$WS$&$1100.1001\ 100$&$\ll2$\\
+    &$WC$&$0100.0100\ 000$&$\ll2$\\
+    \hdashline\\
+    Step 2:&$WS$&$0010.0110\ 000$&\\
+    &$WC$&$0001.0000\ 00\mathbf{1}$&($RW_{msbs}=0011.010\ \text{so}\ q_2=-1$)\\
+    &$-q_5D$&$1110.0101\ 111$&\\
+    \cline{2-3}
+\end{tabular}
+\end{center}
+
+page 269 306
+
+\vfill 
+\eject
+
+\large{\bf{
+Math for the recurrence relation}}
+
+**going to have to change notation for sure, change the subscripts for steps and might have to get rid of some exponents**
+\begin{align*}
+    w[j+1] &= r^{j+1}\big(x-S[j+1]^2\big)\\
+    &= r^{j+1}\big(x-(S[j]+s_{j+1}r^{-(j+1)})^2\big)\\
+    &= r^{j+1}x-r^{j+1}\big(S[j]^2+2S[j]s_{j+1}r^{-(j+1)}+s^2_{j+1}r^{-2(j+1)}\big)\\
+    &= r^{j+1}\big(x-S[j]^2\big)-\big(2S[j]s_{j+1}+s_{j+1}^2r^{-(j+1)}\big)\\
+    &= rw[j]-\big(2S[j]s_{j+1}+s_{j+1}^2r^{-(j+1)}\big)\\
+    &= rw[j]+F[j]
+\end{align*}
+where
+\begin{align*}
+    F[j]=-\big(2S[j]s_{j+1}+s_{j+1}^2r^{-(j+1)}\big)
+\end{align*}
+
+Since there is a term of $S$ in the expression of $F$, we must come up with a way to represent $S$ using only zeros and ones, rather than using the bit set $\{-a,\ldots,a\}$. This is done using on-the-fly conversion just as we did to compute the quotient for the divider. We keep a running copy of $S$, but we also keep the value $SM=S-1$. The logic is still the same for computing $S$ and $SM$ on the next step; see figure 13.15. 
+
+Now that $S$ is in a form such that we can use it in a CSA, we need to compute $F$. To do so, 
+
+\end{document}
diff --git a/docs/divsqrt_tex/div4.aux b/docs/divsqrt_tex/div4.aux
new file mode 100644
index 000000000..d490c35e0
--- /dev/null
+++ b/docs/divsqrt_tex/div4.aux
@@ -0,0 +1,2 @@
+\relax 
+\gdef \@abspage@last{2}
diff --git a/docs/divsqrt_tex/div4.log b/docs/divsqrt_tex/div4.log
new file mode 100644
index 000000000..f2d997a65
--- /dev/null
+++ b/docs/divsqrt_tex/div4.log
@@ -0,0 +1,527 @@
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diff --git a/docs/divsqrt_tex/div4.tex b/docs/divsqrt_tex/div4.tex
new file mode 100644
index 000000000..a5b95dda1
--- /dev/null
+++ b/docs/divsqrt_tex/div4.tex
@@ -0,0 +1,84 @@
+\documentclass[12pt]{article}
+
+\usepackage{amssymb, amsmath, amsfonts, amsthm, graphicx, tcolorbox}
+
+\usepackage{arydshln}
+
+\parskip = .2in
+\parindent  = 0in
+
+\pagestyle{empty}
+
+%==========
+%==========
+
+\begin{document}
+
+
+X = 1.0000\ 1101 (269/256)
+
+D = 1.0011\ 0110 (310/256)
+
+Q = 0.1101\ 1110 (222/256)
+
+D[1.3] = 1.001, so we use the ``1.001" column of chart 13.X. This means we select a quotient bit of 2 if the partial remainder is greater than or equal to 3.5, a quotient bit of 1 if the partial is greater or equal to than 1.0, a zero if the partial is greater than or equal to -1.5, -1 if the partial is greater than or equal to -3.75, and a -2 otherwise.
+
+{\small
+\begin{center}
+\begin{tabular}{cccc}
+    Initialization&$D$&$0001.0011\ 0110\ 00$&\\
+    &$2D$&$0010.0110\ 1100\ 00$&\\
+    &$-D=\overline{D}+1$&$1110.1100\ 1001\ 11$&(+ 1 ulp)\\
+    &$-2D=\overline{2D}+1$&$1101.1001\ 0011\ 11$&(+ 1 ulp)\\
+    &&&\\
+    &$WS_{-1}=X$&$0001.0000\ 1101\ 00$&\\
+    &$WC_{-1}$&$0000.0000\ 0000\ 00$&\\
+    \hdashline\\
+    Step 0: &$WS_{-1}   $&$0001.0000\ 1101\ 00$&\\
+            &$WC_{-1}   $&$0000.0000\ 0000\ 0\mathbf{1}$&($W_{msbs}=0001.000\ \text{so}\ q_0=1$)\\
+            &$-q_0D     $&$1110.1100\ 1001\ 11$&\\
+    \cline{2-3}
+            &$sum       $&$1111.1100\ 0100\ 10$&$\ll2$\\
+            &$carry     $&$0000.0001\ 0010\ 10$&$\ll2$\\
+    \hdashline\\
+    Step 1: &$WS_0      $&$1111.0001\ 0010\ 00$&\\
+            &$WC_0      $&$0000.0100\ 1010\ 0\mathbf{0}$&($W_{msbs}=1111.010\ \text{so}\ q_1=-1$)\\
+            &$-q_1D     $&$0001.0011\ 0110\ 00$&\\
+    \cline{2-3}
+            &$sum       $&$1110.0110\ 1110\ 00$&$\ll2$\\
+            &$carry     $&$0010.0010\ 0100\ 00$&$\ll2$\\
+    \hdashline\\
+    Step 2: &$WS_1      $&$1001.1011\ 1000\ 00$&\\
+            &$WC_1      $&$1000.1001\ 0000\ 0\mathbf{1}$&($W_{msbs}=0010.010\ \text{so}\ q_2=2$)\\
+            &$-q_2D     $&$1101.1001\ 0011\ 11$\\
+    \cline{2-3}
+            &$sum       $&$1100.1011\ 1011\ 10$&$\ll2$\\
+            &$carry     $&$0011.0010\ 0000\ 10$&$\ll2$\\
+    \hdashline\\
+    Step 3: &$WS_2      $&$0010.1110\ 1110\ 00$&\\
+            &$WC_2      $&$1100.1000\ 0010\ 0\mathbf{0}$&($W_{msbs}=1111.011\ \text{so}\ q_3=-1$)\\
+            &$-q_3D     $&$0001.0011\ 0110\ 00$\\
+    \cline{2-3}
+            &$sum       $&$1111.0101\ 1010\ 00$&$\ll2$\\
+            &$carry     $&$0001.0100\ 0100\ 00$&$\ll2$\\
+    \hdashline\\
+    Step 4: &$WS_3      $&$1101.0110\ 1000\ 00$&\\
+            &$WC_3      $&$0101.0001\ 0000\ 0\mathbf{1}$&($W_{msbs}=0010.011\ \text{so}\ q_4=2$)\\
+            &$-q_4D     $&$1101.1001\ 0011\ 11$\\
+    \cline{2-3}
+            &$sum       $&$0101.1110\ 1011\ 10$&$\ll2$\\
+            &$carry     $&$1010.0010\ 0000\ 10$&$\ll2$\\
+    \hdashline\\
+    Step 5: &$WS_4      $&$0111.1010\ 1110\ 00$&\\
+            &$WC_4      $&$1000.1000\ 0010\ 0\mathbf{0}$&($W_{msbs}=0000.001\ \text{so}\ q_5=0$)\\
+            &$-q_5D     $&$0000.0000\ 0000\ 00$\\
+    \cline{2-3}
+            &$sum       $&$1111.0010\ 1100\ 00$&$\ll2$\\
+            &$carry     $&$0001.0000\ 0100\ 00$&$\ll2$\\
+    \hdashline\\
+    Terminate&Quotient&$00.11\ 01\ 11\ 10\ (00\ 1)$
+\end{tabular}
+\end{center}
+}
+
+\end{document}
diff --git a/docs/divsqrt_tex/sqrt2.aux b/docs/divsqrt_tex/sqrt2.aux
new file mode 100644
index 000000000..4fd86f1fe
--- /dev/null
+++ b/docs/divsqrt_tex/sqrt2.aux
@@ -0,0 +1,2 @@
+\relax 
+\gdef \@abspage@last{11}
diff --git a/docs/divsqrt_tex/sqrt2.log b/docs/divsqrt_tex/sqrt2.log
new file mode 100644
index 000000000..1019ba309
--- /dev/null
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@@ -0,0 +1,557 @@
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HcmV?d00001

diff --git a/docs/divsqrt_tex/sqrt2.tex b/docs/divsqrt_tex/sqrt2.tex
new file mode 100644
index 000000000..3c40b037c
--- /dev/null
+++ b/docs/divsqrt_tex/sqrt2.tex
@@ -0,0 +1,385 @@
+\documentclass[12pt]{article}
+\usepackage{amssymb, amsmath, amsfonts, amsthm, graphicx, tcolorbox}
+\usepackage{arydshln}
+
+\parskip = .2in
+\parindent  = 0in
+
+\pagestyle{empty}
+
+%==========
+%==========
+
+\begin{document}
+
+X = 0.0111 0011 1001 (1849/4096)
+
+S = 0.1010 1100 0000 (2752/4096)
+{\small
+\begin{center}
+\begin{tabular}{ccccc}
+            &$X             $&$         0000.0111\ 0011\ 1001   $&          &$S_0={\color{blue}0001}.0000\ 0000\ 0000$\\
+            &$WS_0=2(X-1)   $&$         1110.1110\ 0111\ 0010   $&          &$SM_0={\color{blue}0000}.0000\ 0000\ 0000\phantom{M}$\\
+            &$WC_0          $&$         0000.0000\ 0000\ 0000   $&          &$K_0=0001.0000\ 0000\ 0000\ $\\
+            &                &                                   &          &$C_0=1111.0000\ 0000\ 0000\,$\\
+    \hdashline\\
+    Step 1: &$WS_0          $&$         1110.1110\ 0111\ 0010   $&          &\\
+            &$WC_0          $&$         0000.0000\ 0000\ 0000   $&          &($W_{msbs}=1110\ \text{so}\ s_1=-1$)\\
+            &$F_1=2S_0-K_1 $&${\color{blue}0001.1}000\ 0000\ 0000$&          &$S_1={\color{blue}0000.1}000\ 0000\ 0000$\\
+            &                &                                   &          &$SM_1={\color{blue}0000.0}000\ 0000\ 0000\phantom{M}$\\
+    \cline{2-3}
+            &$sum           $&$         1111.0110\ 0111\ 0010   $&$\ll1    $&$K_1=0000.1000\ 0000\ 0000\ $\\
+            &$carry         $&$         0001.0000\ 0000\ 0000   $&$\ll1    $&$C_1=1111.1000\ 0000\ 0000\,$\\
+    \hdashline\\    
+    Step 2: &$WS_1          $&$         1110.1100\ 1110\ 0100   $&          &\\
+            &$WC_1          $&$         0010.0000\ 0000\ 0000   $&          &($W_{msbs}=0000\ \text{so}\ s_2=1$)\\
+            &$F_2=-2S_1-K_2$&${\color{blue}1110.11}00\ 0000\ 0000$&          &$S_2={\color{blue}0000.11}00\ 0000\ 0000$\\
+            &                &                                   &          &$SM_2={\color{blue}0000.10}00\ 0000\ 0000\phantom{M}$\\
+    \cline{2-3}
+            &$sum           $&$         0010.0000\ 1110\ 0100   $&$\ll1    $&$K_2=0000.0100\ 0000\ 0000\ $\\
+            &$carry         $&$         1101.1000\ 0000\ 0000   $&$\ll1    $&$C_2=1111.1100\ 0000\ 0000\,$\\
+    \hdashline\\
+    Step 3: &$WS_2          $&$         0100.0001\ 1100\ 1000   $&          &\\
+            &$WC_2          $&$         1011.0000\ 0000\ 0000   $&          &($W_{msbs}=1111\ \text{so}\ s_3=0$)\\
+            &$F_3=0       $&${\color{blue}0000.000}0\ 0000\ 0000$&          &$S_3={\color{blue}0000.110}0\ 0000\ 0000$\\
+            &                &                                   &          &$SM_3={\color{blue}0000.101}0\ 0000\ 0000\phantom{M}$\\
+    \cline{2-3}
+            &$sum           $&$         1111.0001\ 1100\ 1000   $&$\ll1    $&$K_3=0000.0010\ 0000\ 0000\ $\\
+            &$carry         $&$         0000.0000\ 0000\ 0000   $&$\ll1    $&$C_3=1111.1110\ 0000\ 0000\,$\\
+    \hdashline\\
+    Step 4: &$WS_3          $&$         1110.0011\ 1001\ 0000   $&          &\\
+            &$WC_3          $&$         0000.0000\ 0000\ 0000   $&          &($W_{msbs}=1110\ \text{so}\ s_4=-1$)\\
+            &$F_4=2S_3-K_4 $&${\color{blue}0001.0111}\ 0000\ 0000$&          &$S_4={\color{blue}0000.1011}\ 0000\ 0000$\\
+            &                &                                   &          &$SM_4={\color{blue}0000.1010}\ 0000\ 0000\phantom{M}$\\
+    \cline{2-3}
+            &$sum           $&$         1111.0100\ 1001\ 0000   $&$\ll1    $&$K_4=0000.0001\ 0000\ 0000\ $\\
+            &$carry         $&$         0000.0110\ 0000\ 0000   $&$\ll1    $&$C_4=1111.1111\ 0000\ 0000\,$\\
+    \hdashline\\
+    Step 5: &$WS_4          $&$         1110.1001\ 0010\ 0000   $&          &\\
+            &$WC_4          $&$         0000.1100\ 0000\ 0000   $&          &($W_{msbs}=1110\ \text{so}\ s_5=-1$)\\
+            &$F_5=2S_4-K_5 $&${\color{blue}0001.0101\ 1}000\ 0000$&          &$S_5={\color{blue}0000.1010\ 1}000\ 0000$\\
+            &                &                                   &          &$SM_5={\color{blue}0000.1010\ 0}000\ 0000\phantom{M}$\\
+    \cline{2-3}
+            &$sum           $&$         1111.0000\ 1010\ 0000   $&$\ll1    $&$K_5=0000.0000\ 1000\ 0000\ $\\
+            &$carry         $&$         0001.1010\ 0000\ 0000   $&$\ll1    $&$C_5=1111.1111\ 1000\ 0000\,$\\
+    \hdashline\\
+    Step 6: &$WS_5          $&$         1110.0001\ 0100\ 0000   $&          &\\
+            &$WC_5          $&$         0011.0100\ 0000\ 0000   $&          &($W_{msbs}=0001\ \text{so}\ s_6=1$)\\
+            &$F_6=-2S_5-K_6$&${\color{blue}1110.1010\ 11}00\ 0000$&          &$S_6={\color{blue}0000.1010\ 11}00\ 0000$\\
+            &                &                                   &          &$SM_6={\color{blue}0000.1010\ 10}00\ 0000\phantom{M}$\\
+    \cline{2-3}
+            &$sum           $&$         0011.1111\ 1000\ 0000   $&$\ll1    $&$K_6=0000.0000\ 0100\ 0000\ $\\
+            &$carry         $&$         1100.0000\ 1000\ 0000   $&$\ll1    $&$C_6=1111.1111\ 1100\ 0000\,$\\
+            &                &                                   &          &$sum+carry=0$, terminate\\
+    \hdashline\\
+    Terminate&Square Root&0.101011
+\end{tabular}
+\end{center}
+}
+
+{\small
+\begin{center}
+\begin{tabular}{cccc}
+    \hdashline\\
+    Step 6: &$WS    $&$0111.1111\ 0000\ 00$&\\
+            &$WC    $&$1000.0001\ 0000\ 00$&($W_{msbs}=1111\ \text{so}\ s_6=0$)\\
+            &$F     $&$0000.0000\ 0000\ 00$&$S_6=\mathbf{1.0101\ 10}00\ 00$\\
+            &        &                     &$SM_6=\mathbf{1.0101\ 01}00\ 00\phantom{M}$\\
+    \cline{2-3}
+            &$WS    $&$1111.1110\ 0000\ 00$&$\ll1$\\
+            &$WC    $&$0000.0010\ 0000\ 00$&$\ll1$\\
+    \hdashline\\
+    Step 7: &$WS    $&$1111.1100\ 0000\ 00$&\\
+            &$WC    $&$0000.0100\ 0000\ 00$&($W_{msbs}=1111\ \text{so}\ s_7=0$)\\
+            &$F     $&$0000.0000\ 0000\ 00$&$S_7=\mathbf{1.0101\ 100}0\ 00$\\
+            &        &                     &$SM_7=\mathbf{1.0101\ 011}0\ 00\phantom{M}$\\
+    \cline{2-3}
+            &$WS    $&$1111.1000\ 0000\ 00$&$\ll1$\\
+            &$WC    $&$0000.1000\ 0000\ 00$&$\ll1$\\
+    \hdashline\\
+    Step 8: &$WS    $&$1111.0000\ 0000\ 00$&\\
+            &$WC    $&$0001.0000\ 0000\ 00$&($W_{msbs}=0000\ \text{so}\ s_8=1$)\\
+            &$F     $&$1110.1010\ 0111\ 10$&$S_8=\mathbf{1.0101\ 1001}\ 00$\\
+            &        &                     &$SM_8=\mathbf{1.0101\ 1000}\ 00\phantom{M}$\\
+    \cline{2-3}
+            &$WS    $&$0000.1010\ 0111\ 10$&$\ll1$\\
+            &$WC    $&$1110.0000\ 0000\ 00$&$\ll1$\\
+    \hdashline\\
+    Step 9: &$WS    $&$0001.0100\ 1111\ 00$&\\
+            &$WC    $&$1100.0000\ 0000\ 00$&($W_{msbs}=1101\ \text{so}\ s_9=-1$)\\
+            &$F     $&$0001.0101\ 1000\ 11$&$S_9=\mathbf{1.0101\ 1000\ 1}0$\\
+            &        &                     &$SM_9=\mathbf{1.0101\ 1000\ 0}0\phantom{M}$\\
+    \cline{2-3}
+            &$WS    $&$1100.0001\ 0111\ 11$&$\ll1$\\
+            &$WC    $&$0010.1001\ 0000\ 00$&$\ll1$\\
+    \hdashline\\
+    Step 10:&$WS    $&$1000.0010\ 1111\ 10$&\\
+            &$WC    $&$0101.0010\ 0000\ 00$&($W_{msbs}=1101\ \text{so}\ s_{10}=-1$)\\
+            &$F     $&$0001.0101\ 1000\ 01$&$S_{10}=\mathbf{1.0101\ 1000\ 01}$\\
+            &        &                     &$SM_{10}=\mathbf{1.0101\ 1000\ 00}\phantom{M}$\\
+    \cline{2-3}
+            &$WS    $&$1100.0001\ 0111\ 11$&$\ll1$\\
+            &$WC    $&$0010.0101\ 0000\ 00$&$\ll1$\\
+    \hdashline\\
+    Step 11:&$WS    $&$1000.0010\ 1111\ 10$&\\
+            &$WC    $&$0100.1010\ 0000\ 00$&($W_{msbs}=1101\ \text{so}\ s_{11}=-1$)\\
+            &$F     $&$0001.0101\ 1000\ 00$&$S_{11}=\mathbf{1.0101\ 1000\ 00}$\\
+            &        &                     &$SM_{11}=\mathbf{1.0101\ 1000\ 00}\phantom{M}$\\
+    \cline{2-3}
+            &$WS    $&$1101.1101\ 0111\ 10$&$\ll1$\\
+            &$WC    $&$0000.0101\ 0000\ 00$&$\ll1$\\
+    \hdashline\\
+    Step 12:&$WS    $&$1101.1000\ 0111\ 10$&\\
+            &$WC    $&$0000.1010\ 0000\ 00$&($W_{msbs}=1101\ \text{so}\ s_{12}=-1$)\\
+            &$F     $&$0001.0101\ 1000\ 00$&$S_{12}=\mathbf{1.0101\ 1000\ 00}$\\
+            &        &                     &$SM_{12}=\mathbf{1.0101\ 1000\ 00}\phantom{M}$\\
+    \cline{2-3}
+            &$WS    $&$1100.0111\ 1111\ 10$&$\ll1$\\
+            &$WC    $&$0011.0000\ 0000\ 00$&$\ll1$\\
+\end{tabular}
+\end{center}
+}
+
+{\small
+\begin{center}
+\begin{tabular}{cccc}
+    Step 13:&$WS    $&$1000.1111\ 1111\ 00$&\\
+            &$WC    $&$0110.0000\ 0000\ 00$&($W_{msbs}=1110\ \text{so}\ s_{13}=-1$)\\
+            &$F     $&$0001.0101\ 1000\ 00$&$S_{13}=\mathbf{1.0101\ 1000\ 00}$\\
+            &        &                     &$SM_{13}=\mathbf{1.0101\ 1000\ 00}\phantom{M}$\\
+    \cline{2-3}
+            &$WS    $&$1111.1010\ 0111\ 10$&$\ll1$\\
+            &$WC    $&$0000.1011\ 0000\ 00$&$\ll1$\\
+\end{tabular}
+\end{center}
+}
+
+\vfill
+\eject
+
+{\small
+\begin{center}
+\begin{tabular}{ccccc}
+            &$X             $&$         0000.1100\ 0000     $&          &$S_0={\color{blue}0001}.0000\ 0000\ 00$\\
+            &$WS=X-1        $&$         1111.1100\ 0000     $&          &$SM_0={\color{blue}0000}.0000\ 0000\ 00\phantom{M}$\\
+            &$WC            $&$         0000.0000\ 0000     $&          &$K_0=0000.0100\ 0000\ 00\ $\\
+            &                &                               &          &$C_0=1111.1100\ 0000\ 00\,$\\
+    \hdashline\\
+    Step 1: &$WS            $&$         1111.1100\ 0000     $&          &\\
+            &$WC            $&$         0000.0000\ 0000     $&          &($W_{msbs}=1111\ \text{so}\ s_1=0$)\\
+            &$F_1=0         $&${\color{blue}0000.00}00\ 0000$&          &$S_1={\color{blue}0001.0}000\ 0000\ 00$\\
+            &                &                               &          &$SM_1={\color{blue}0000.1}000\ 0000\ 00\phantom{M}$\\
+    \cline{2-3}
+            &$WS            $&$         1111.1100\ 0000     $&$\ll1    $&$K_1=0000.0010\ 0000\ 00\ $\\
+            &$WC            $&$         0000.0000\ 0000     $&$\ll1    $&$C_1=1111.1110\ 0000\ 00\,$\\
+    \hdashline\\    
+    Step 2: &$WS            $&$         1111.1000\ 0000     $&          &\\
+            &$WC            $&$         0000.0000\ 0000     $&          &($W_{msbs}=1111\ \text{so}\ s_2=0$)\\
+            &$F_2=0         $&${\color{blue}0000.000}0\ 0000$&          &$S_2={\color{blue}0001.00}00\ 0000\ 00$\\
+            &                &                               &          &$SM_2={\color{blue}0000.11}00\ 0000\ 00\phantom{M}$\\
+    \cline{2-3}
+            &$WS            $&$         1111.1000\ 0000     $&$\ll1    $&$K_2=0000.0001\ 0000\ 00\ $\\
+            &$WC            $&$         0000.0000\ 0000     $&$\ll1    $&$C_2=1111.1111\ 0000\ 00\,$\\
+    \hdashline\\
+    Step 3: &$WS            $&$         1111.0000\ 0000     $&          &\\
+            &$WC            $&$         0000.0000\ 0000     $&          &($W_{msbs}=1111\ \text{so}\ s_3=0$)\\
+            &$F_3=0         $&${\color{blue}0000.0000}\ 0000$&          &$S_3={\color{blue}0001.000}0\ 0000\ 00$\\
+            &                &                               &          &$SM_3={\color{blue}0000.111}0\ 0000\ 00\phantom{M}$\\
+    \cline{2-3}
+            &$WS            $&$1111.0000\ 0000              $&$\ll1    $&$K_3=0000.0000\ 1000\ 00\ $\\
+            &$WC            $&$0000.0000\ 0000              $&$\ll1    $&$C_3=1111.1111\ 1000\ 00\,$\\
+    \hdashline\\
+    Step 4: &$WS            $&$1110.0000\ 0000              $&          &\\
+            &$WC            $&$0000.0000\ 0000              $&          &($W_{msbs}=1110\ \text{so}\ s_4=-1$)\\
+            &$F_4=S_3-K_3   $&${\color{blue}0000.1111\ 1}000$&          &$S_4={\color{blue}0000.1111}\ 0000\ 00$\\
+            &                &                               &          &$SM_4={\color{blue}0000.1110}\ 0000\ 00\phantom{M}$\\
+    \cline{2-3}
+            &$WS            $&$1110.1111\ 1000              $&$\ll1    $&$K_4=0000.0000\ 0100\ 00\ $\\
+            &$WC            $&$0000.0000\ 0000              $&$\ll1    $&$C_4=1111.1111\ 1100\ 00\,$\\
+    \hdashline\\
+    Step 5: &$WS            $&$1101.1111\ 0000              $&          &\\
+            &$WC            $&$0000.0000\ 0000              $&          &($W_{msbs}=1101\ \text{so}\ s_5=-1$)\\
+            &$F_5=S_4-K_4   $&${\color{blue}0000.1110\ 11}00$&          &$S_5={\color{blue}0000.1110\ 1}000\ 00$\\
+            &                &                                   &          &$SM_5={\color{blue}0001.1110\ 0}000\ 00\phantom{M}$\\
+    \cline{2-3}
+            &$WS            $&$1101.0001\ 1100              $&$\ll1    $&$K_5=0000.0000\ 0010\ 00\ $\\
+            &$WC            $&$0001.1100\ 0000              $&$\ll1    $&$C_5=1111.1111\ 1110\ 00\,$\\
+    Terminate
+\end{tabular}
+\end{center}
+}
+
+\vfill
+\eject
+
+X = 0.1010101101(685/1024)
+
+S = 0.1101000110(838/1024)
+
+once R4 sslc gets here i can fill this in
+
+\vfill 
+\eject
+
+X = 1.1001 (25/16)
+
+S = 1.0100 (20/16)
+
+{\small
+\begin{center}
+\begin{tabular}{cccc}
+    Attempt 1:& $X$ is normalized& to $1/2<X<2$&$W_{msbs}$ looks at Q4.0\\
+    &&&\\
+            &$X     $&$0001.1001$&\\
+            &$WS=X-1$&$0000.1001$& $s_0=1$\\
+            &$WC    $&$0000.0000$&$S_0=\mathbf{1}.0000,\quad SM_0=\mathbf{0}.0000$ \\
+    \hdashline\\
+    Step 1: &$WS    $&$0000.1001$&\\
+            &$WC    $&$0000.0000$&($W_{msbs}=0000\ \text{so}\ s_1=1$)\\
+            &$F     $&$1110.1100$&$S_1=\mathbf{1.1}000,\quad SM_1=\mathbf{1.0}000$\\
+    \cline{2-3}
+            &$WS    $&$1110.0101$&$\ll1$\\
+            &$WC    $&$0001.0000$&$\ll1$\\
+    \hdashline\\
+    Step 2: &$WS    $&$1100.1010$&\\
+            &$WC    $&$0010.0000$&($W_{msbs}=1110\ \text{so}\ s_2=-1$)\\
+            &$F     $&$0001.0110$&$S_2=\mathbf{1.01}00,\quad SM_2=\mathbf{1.00}00$\\
+    \cline{2-3}
+            &$WS    $&$1111.1110$&$\ll1$\\
+            &$WC    $&$0000.0010$&$\ll1$\\
+    \hdashline\\
+    Step 3: &$WS    $&$1111.1100$&\\
+            &$WC    $&$0000.0100$&($W_{msbs}=1111\ \text{so}\ s_3=0$)\\
+            &$-q_3D $&$0000.0000$&$S_3=\mathbf{1.010}0,\quad SM_3=\mathbf{1.001}0$\\
+    \cline{2-3}
+            &$WS    $&$1111.1000$&$\ll1$\\
+            &$WC    $&$0000.1000$&$\ll1$\\
+    \hdashline\\
+    Step 4: &$WS    $&$1111.0000$&\\
+            &$WC    $&$0001.0000$&($W_{msbs}=0000\ \text{so}\ s_4=1$)\\
+            &$F     $&$0000.0000$&$S_4=\mathbf{1.0101},\quad SM_4=\mathbf{1.0100}$\\
+    Terminate&&&
+\end{tabular}
+\end{center}
+}
+
+
+{\small
+\begin{center}
+\begin{tabular}{cccc}
+    Attempt 2:& $X$ is normalized& to $1/2<X<2$&$W_{msbs}$ looks at Q3.1\\
+    &&&\\
+            &$X     $&$001.1001$&\\
+            &$WS=X-1$&$000.1001$& $s_0=1$\\
+            &$WC    $&$000.0000$&$S_0=\mathbf{1}.0000,\quad SM_0=\mathbf{0}.0000$ \\
+    \hdashline\\
+    Step 1: &$WS    $&$000.1001$&\\
+            &$WC    $&$000.0000$&($W_{msbs}=000.1\ \text{so}\ s_1=1$)\\
+            &$F     $&$110.1000$&$S_1=\mathbf{1.1}000,\quad SM_1=\mathbf{1.0}000$\\
+    \cline{2-3}
+            &$WS    $&$110.0001$&$\ll1$\\
+            &$WC    $&$001.0000$&$\ll1$\\
+    \hdashline\\
+    Step 2: &$WS    $&$100.0010$&\\
+            &$WC    $&$010.0000$&($W_{msbs}=110.0\ \text{so}\ s_2=-1$)\\
+            &$F     $&$001.0100$&$S_2=\mathbf{1.01}00,\quad SM_2=\mathbf{1.00}00$\\
+    \cline{2-3}
+            &$WS    $&$111.0110$&$\ll1$\\
+            &$WC    $&$000.0000$&$\ll1$\\
+    \hdashline\\
+    Step 3: &$WS    $&$110.1100$&\\
+            &$WC    $&$000.0000$&($W_{msbs}=110.1\ \text{so}\ s_3=-1$)\\
+            &$-q_3D $&$001.0010$&$S_3=\mathbf{1.001}0,\quad SM_3=\mathbf{1.000}0$\\
+    \cline{2-3}
+            &$WS    $&$111.1110$&$\ll1$\\
+            &$WC    $&$000.0000$&$\ll1$\\
+    \hdashline\\
+    Step 4: &$WS    $&$111.1110$&\\
+            &$WC    $&$000.0000$&($W_{msbs}=111.1\ \text{so}\ s_4=0$)\\
+            &$F     $&$000.0000$&$S_4=\mathbf{1.0010},\quad SM_4=\mathbf{1.0001}$\\
+    Terminate&&&
+\end{tabular}
+\end{center}
+}
+
+{\small
+\begin{center}
+\begin{tabular}{cccc}
+    Attempt 3:& $X$ is normalized& to $1<X<4$&$W_{msbs}$ looks at Q4.0\\
+    &&&\\
+            &$X     $&$0001.1001$&\\
+            &$WS=X-2$&$1111.1001$& $s_{-1}=10$\\
+            &$WC    $&$0000.0000$&$S_{-1}=\mathbf{1}0.0000,\quad SM_{-1}=\mathbf{0}0.0000$ \\
+    \hdashline\\
+    Step 0: &$WS    $&$1111.1001$&\\
+            &$WC    $&$0000.0000$&($W_{msbs}=1111\ \text{so}\ s_0=0$)\\
+            &$F     $&$0000.0000$&$S_0=\mathbf{10}.0000,\quad SM_0=\mathbf{01}.0000$\\
+    \cline{2-3}
+            &$WS    $&$1111.1001$&$\ll1$\\
+            &$WC    $&$0000.0000$&$\ll1$\\
+    \hdashline\\
+    Step 1: &$WS    $&$1111.0010$&\\
+            &$WC    $&$0000.0000$&($W_{msbs}=1111\ \text{so}\ s_1=0$)\\
+            &$F     $&$0000.0000$&$S_1=\mathbf{10.0}000,\quad SM_1=\mathbf{01.1}000$\\
+    \cline{2-3}
+            &$WS    $&$1111.0010$&$\ll1$\\
+            &$WC    $&$0000.0000$&$\ll1$\\
+    \hdashline\\
+    Step 2: &$WS    $&$1110.0100$&\\
+            &$WC    $&$0000.0000$&($W_{msbs}=1110\ \text{so}\ s_2=-1$)\\
+            &$-q_3D $&$0001.1100$&$S_2=\mathbf{01.01}00,\quad SM_2=\mathbf{01.00}00$\\
+    \cline{2-3}
+            &$WS    $&$1111.1000$&$\ll1$\\
+            &$WC    $&$0000.1000$&$\ll1$\\
+    Terminate&&&
+\end{tabular}
+\end{center}
+}
+
+\vfill
+\eject
+
+X = 0.011001 (25/64)
+
+S = 0.101000 (40/64)
+
+{\small
+\begin{center}
+\begin{tabular}{cccc}
+    Attempt 4:& $X$ is normalized& to $1/4<X<1$&$W_{msbs}$ looks at Q3.1\\
+    &&&\\
+            &$X     $&$000.0110\ 01$&\\
+            &$WS=X-1$&$111.0110\ 01$& $s_0=1$\\
+            &$WC    $&$000.0000\ 00$&$S_0=\mathbf{1}.000000,\quad SM_0=\mathbf{0}.000000$ \\
+    \hdashline\\
+    Step 1: &$WS    $&$111.0110\ 01$&\\
+            &$WC    $&$000.0000\ 00$&($W_{msbs}=111.0\ \text{so}\ s_1=-1$)\\
+            &$F     $&$000.1000\ 00$&$S_1=\mathbf{0.1}00000,\quad SM_1=\mathbf{0.0}00000$\\
+    \cline{2-3}
+            &$WS    $&$111.1110\ 01$&$\ll1$\\
+            &$WC    $&$000.0000\ 00$&$\ll1$\\
+    \hdashline\\
+    Step 2: &$WS    $&$111.1100\ 10$&\\
+            &$WC    $&$000.0000\ 00$&($W_{msbs}=111.1\ \text{so}\ s_2=0$)\\
+            &$F     $&$000.0000\ 00$&$S_2=\mathbf{0.10}0000,\quad SM_2=\mathbf{0.01}0000$\\
+    \cline{2-3}
+            &$WS    $&$111.1100\ 10$&$\ll1$\\
+            &$WC    $&$000.0000\ 00$&$\ll1$\\
+    \hdashline\\
+    Step 3: &$WS    $&$111.1001\ 00$&\\
+            &$WC    $&$000.0000\ 00$&($W_{msbs}=010.0\ \text{so}\ s_3=1$)\\
+            &$-q_3D $&$111.0010\ 00$&$S_3=\mathbf{0.111}000,\quad SM_3=\mathbf{0.110}000$\\
+    \cline{2-3}
+            &$WS    $&$1111.1110$&$\ll1$\\
+            &$WC    $&$0000.0000$&$\ll1$\\
+    \hdashline\\
+    Step 4: &$WS    $&$1111.1110$&\\
+            &$WC    $&$0000.0000$&($W_{msbs}=111.1\ \text{so}\ s_4=0$)\\
+            &$F     $&$0000.0000$&$S_4=\mathbf{1.0010}00,\quad SM_4=\mathbf{1.0001}00$\\
+    Terminate&&&
+\end{tabular}
+\end{center}
+}
+
+
+\end{document}
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diff --git a/docs/divsqrt_tex/sqrt4.tex b/docs/divsqrt_tex/sqrt4.tex
new file mode 100644
index 000000000..1d40864eb
--- /dev/null
+++ b/docs/divsqrt_tex/sqrt4.tex
@@ -0,0 +1,147 @@
+\documentclass[12pt]{article}
+
+\usepackage{amssymb, amsmath, amsfonts, amsthm, graphicx, tcolorbox}
+
+\usepackage{arydshln}
+
+\parskip = .2in
+\parindent  = 0in
+
+\pagestyle{empty}
+
+%==========
+%==========
+
+\begin{document}
+
+
+
+X = 0.1011 0111 10 (734/1024)
+
+S = 0.1101 1000 11\ 00 (3468/4096), negative sticky bit
+{\small
+\begin{center}
+\begin{tabular}{ccccc}
+            &$X             $&$         0000.1011\ 0111\ 1000   $&          &$S_0={\color{blue}0001}.0000\ 0000\ 0000$\\
+            &$WS_0=4(X-1)   $&$         1110.1101\ 1110\ 0000   $&          &$SM_0={\color{blue}0000}.0000\ 0000\ 0000\phantom{M}$\\
+            &$WC_0          $&$         0000.0000\ 0000\ 0000   $&          &$K_0=0001.0000\ 0000\ 0000\ $\\
+            &                &                                   &          &$C_0=1111.0000\ 0000\ 0000\,$\\
+    \hdashline\\
+    Step 1: &$WS_0          $&$         1110.1101\ 1110\ 0000   $&          &\\
+            &$WC_0          $&$         0000.0000\ 0000\ 0000   $&          &($W_{msbs}=1110.110\ \text{so}\ s_1=-1$)\\
+            &$F_1=2S_0-K_1$&${\color{blue}0001.11}00\ 0000\ 0000$&          &$S_1={\color{blue}0000.11}00\ 0000\ 0000$\\
+            &                &                                   &          &$SM_1={\color{blue}0000.10}00\ 0000\ 0000\phantom{M}$\\
+    \cline{2-3}
+            &$sum           $&$         1111.0001\ 1110\ 0000   $&$\ll2    $&$K_1=0000.0100\ 0000\ 0000\ $\\
+            &$carry         $&$         0001.1000\ 0000\ 0000   $&$\ll2    $&$C_1=1111.1100\ 0000\ 0000\,$\\
+    \hdashline\\    
+    Step 2: &$WS_1          $&$         1100.0111\ 1000\ 0000   $&          &\\
+            &$WC_1          $&$         0110.0000\ 0000\ 0000   $&          &($W_{msbs}=0010.011\ \text{so}\ s_2=2$)\\
+            &$F_2=-4S_1-4K_2$&${\color{blue}1100.1100}\ 0000\ 0000$&        &$S_2={\color{blue}0000.1110}\ 0000\ 0000$\\
+            &                &                                   &          &$SM_2={\color{blue}0000.1101}\ 0000\ 0000\phantom{M}$\\
+    \cline{2-3}
+            &$sum           $&$         0110.1011\ 1000\ 0000   $&$\ll2    $&$K_2=0000.0001\ 0000\ 0000\ $\\
+            &$carry         $&$         1000.1000\ 0000\ 0000   $&$\ll2    $&$C_2=1111.1111\ 0000\ 0000\,$\\
+    \hdashline\\
+    Step 3: &$WS_2          $&$         1010.1110\ 0000\ 0000   $&          &\\
+            &$WC_2          $&$         0010.0000\ 0000\ 0000   $&          &($W_{msbs}=1100.111\ \text{so}\ s_3=-2$)\\
+            &$F_3=4S_2-4K_3$&${\color{blue}0011.0111\ 00}00\ 0000$&         &$S_3={\color{blue}0000.1101\ 10}00\ 0000$\\
+            &                &                                   &          &$SM_3={\color{blue}0000.1101\ 01}00\ 0000\phantom{M}$\\
+    \cline{2-3}
+            &$sum           $&$         1011.1001\ 0000\ 0000   $&$\ll2    $&$K_3=0000.0000\ 0100\ 0000\ $\\
+            &$carry         $&$         0100.1100\ 0000\ 0000   $&$\ll2    $&$C_3=1111.1111\ 1100\ 0000\,$\\
+    \hdashline\\
+    Step 4: &$WS_3          $&$         1110.0100\ 0000\ 0000   $&          &\\
+            &$WC_3          $&$         0011.0000\ 0000\ 0000   $&          &($W_{msbs}=0001.010\ \text{so}\ s_4=1$)\\
+            &$F_4=-2S_3-K_4$&${\color{blue}1110.0100\ 1111}\ 0000$&        &$S_4={\color{blue}0000.1101\ 1001}\ 0000$\\
+            &                &                                   &          &$SM_4={\color{blue}0000.1101\ 1000}\ 0000\phantom{M}$\\
+    \cline{2-3}
+            &$sum           $&$         0011.0000\ 1111\ 0000   $&$\ll2    $&$K_4=0000.0000\ 0001\ 0000\ $\\
+            &$carry         $&$         1100.1000\ 0000\ 0000   $&$\ll2    $&$C_4=1111.1111\ 1111\ 0000\,$\\
+    \hdashline\\
+    Step 5: &$WS_4          $&$         1100.0011\ 1100\ 0000   $&          &\\
+            &$WC_4          $&$         0010.0000\ 0000\ 0000   $&          &($W_{msbs}=1110.001\ \text{so}\ s_5=-1$)\\
+            &$F_5=2S_4-K_5 $&${\color{blue}0001.1011\ 0001\ 11}00$&        &$S_5={\color{blue}0000.1101\ 1000\ 11}00$\\
+            &                &                                   &          &$SM_5={\color{blue}0000.1101\ 1000\ 10}00\phantom{M}$\\
+    \cline{2-3}
+            &$sum           $&$         1111.1000\ 1101\ 1100   $&$\ll2    $&$K_5=0000.0000\ 0000\ 0100\ $\\
+            &$carry         $&$         0000.0110\ 0000\ 0000   $&$\ll2    $&$C_5=1111.1111\ 1111\ 1100\,$\\
+    \hdashline\\
+    Step 6: &$WS_5          $&$         1110.0011\ 0111\ 0000   $&          &\\
+            &$WC_5          $&$         0001.1000\ 0000\ 0000   $&          &($W_{msbs}=1111.101\ \text{so}\ s_6=0$)\\
+            &$F_6=0        $&${\color{blue}0000.0000\ 0000\ 0000}$&         &$S_6={\color{blue}0000.1101\ 1000\ 1100}$\\
+            &                &                                   &          &$SM_6={\color{blue}0000.1101\ 1000\ 1011}\phantom{M}$\\
+    \cline{2-3}
+            &$sum           $&$         1111.1011\ 0111\ 0111   $&$\ll2    $&$K_6=0000.0000\ 0000\ 0001\ $\\
+            &$carry         $&$         0000.0000\ 0000\ 0000   $&$\ll2    $&$C_6=1111.1111\ 1111\ 1111\,$\\
+    \hdashline\\
+    Terminate&Square Root&0000.11 01\ 10 00\ 10 (11)
+\end{tabular}
+\end{center}
+}
+
+X = 0.1001\ 0101\ 00 (596/1024)
+
+S = 0.1100 0011 01\ 01 (3125/4096)
+{\small
+\begin{center}
+\begin{tabular}{ccccc}
+            &$X             $&$         0000.1001\ 0101\ 0000   $&          &$S_0={\color{blue}0001}.0000\ 0000\ 0000$\\
+            &$WS_0=4(X-1)   $&$         1110.0101\ 0100\ 0000   $&          &$SM_0={\color{blue}0000}.0000\ 0000\ 0000\phantom{M}$\\
+            &$WC_0          $&$         0000.0000\ 0000\ 0000   $&          &$K_0=0001.0000\ 0000\ 0000\ $\\
+            &                &                                   &          &$C_0=1111.0000\ 0000\ 0000\,$\\
+    \hdashline\\
+    Step 1: &$WS_0          $&$         1110.0101\ 0100\ 0000   $&          &\\
+            &$WC_0          $&$         0000.0000\ 0000\ 0000   $&          &($W_{msbs}=1110.010\ \text{so}\ s_1=-1$)\\
+            &$F_1=2S_0-K_1  $&${\color{blue}0001.11}00\ 0000\ 0000$&        &$S_1={\color{blue}0000.11}00\ 0000\ 0000$\\
+            &                &                                   &          &$SM_1={\color{blue}0000.10}00\ 0000\ 0000\phantom{M}$\\
+    \cline{2-3}
+            &$sum           $&$         1111.1001\ 0100\ 0000   $&$\ll2    $&$K_1=0000.0100\ 0000\ 0000\ $\\
+            &$carry         $&$         0000.1000\ 0000\ 0000   $&$\ll2    $&$C_1=1111.1100\ 0000\ 0000\,$\\
+    \hdashline\\    
+    Step 2: &$WS_1          $&$         1110.0101\ 0000\ 0000   $&          &\\
+            &$WC_2          $&$         0010.0000\ 0000\ 0000   $&          &($W_{msbs}=0000.010\ \text{so}\ s_2=0$)\\
+            &$F_2=0       $&${\color{blue}0000.0000}\ 0000\ 0000$&          &$S_2={\color{blue}0000.1100}\ 0000\ 0000$\\
+            &                &                                   &          &$SM_2={\color{blue}0000.1110}\ 0000\ 0000\phantom{M}$\\
+    \cline{2-3}
+            &$sum           $&$         1100.0101\ 0000\ 0000   $&$\ll2    $&$K_2=0000.0001\ 0000\ 0000\ $\\
+            &$carry         $&$         0100.0000\ 0000\ 0000   $&$\ll2    $&$C_2=1111.1111\ 0000\ 0000\,$\\
+    \hdashline\\
+    Step 3: &$WS_2          $&$         0001.0100\ 0000\ 0000   $&          &\\
+            &$WC_2          $&$         0000.0000\ 0000\ 0000   $&          &($W_{msbs}=0001.010\ \text{so}\ s_3=1$)\\
+            &$F_3=-2S_2-K_3$&${\color{blue}1110.0111\ 11}00\ 0000$&         &$S_3={\color{blue}0000.1100\ 01}00\ 0000$\\
+            &                &                                   &          &$SM_3={\color{blue}0000.1100\ 00}00\ 0000\phantom{M}$\\
+    \cline{2-3}
+            &$sum           $&$         1111.0011\ 1100\ 0000   $&$\ll2    $&$K_3=0000.0000\ 0100\ 0000\ $\\
+            &$carry         $&$         1000.1000\ 0000\ 0000   $&$\ll2    $&$C_3=1111.1111\ 1100\ 0000\,$\\
+    \hdashline\\
+    Step 4: &$WS_3          $&$         1100.1111\ 0000\ 0000   $&          &\\
+            &$WC_3          $&$         0010.0000\ 0000\ 0000   $&          &($W_{msbs}=1110.111\ \text{so}\ s_4=-1$)\\
+            &$F_4=2S_3-K_3  $&${\color{blue}0001.1000\ 0111}\ 0000$&        &$S_4={\color{blue}0000.1100\ 0011}\ 0000$\\
+            &                &                                   &          &$SM_4={\color{blue}0000.1100\ 0010}\ 0000\phantom{M}$\\
+    \cline{2-3}
+            &$sum           $&$         1111.0111\ 0111\ 0000   $&$\ll2    $&$K_4=0000.0000\ 0001\ 0000\ $\\
+            &$carry         $&$         0001.0000\ 0000\ 0000   $&$\ll2    $&$C_4=1111.1111\ 1111\ 0000\,$\\
+    \hdashline\\
+    Step 5: &$WS_4          $&$         1101.1101\ 1100\ 0000   $&          &\\
+            &$WC_4          $&$         0100.0000\ 0000\ 0000   $&          &($W_{msbs}=0001.110\ \text{so}\ s_5=1$)\\
+            &$F_5=-2S_4-K_4 $&${\color{blue}1110.0111\ 1001\ 11}00$&        &$S_5={\color{blue}0000.1100\ 0011\ 01}00$\\
+            &                &                                   &          &$SM_5={\color{blue}0000.1100\ 0011\ 00}00\phantom{M}$\\
+    \cline{2-3}
+            &$sum           $&$         0111.1010\ 0101\ 1100   $&$\ll1    $&$K_5=0000.0000\ 0000\ 0100\ $\\
+            &$carry         $&$         1000.1011\ 0000\ 0000   $&$\ll1    $&$C_5=1111.1111\ 1111\ 1100\,$\\
+    \hdashline\\
+    Step 6: &$WS_5          $&$         1110.1001\ 0111\ 0000   $&          &\\
+            &$WC_5          $&$         0010.1100\ 0000\ 0000   $&          &($W_{msbs}=0001.010\ \text{so}\ s_6=1$)\\
+            &$F_6=          $&$                                 $&          &$S_5={\color{blue}0000.1100\ 0011\ 0101}$\\
+            &                &                                   &          &$SM_5={\color{blue}0000.1100\ 0011\ 0100}\phantom{M}$\\
+    \cline{2-3}
+            &$sum           $&$         0001.1110\ 1001\ 0111   $&$\ll1    $&$K_5=0000.0000\ 0000\ 0001\ $\\
+            &$carry         $&$         1110.0010\ 1100\ 0000   $&$\ll1    $&$C_5=1111.1111\ 1111\ 1111\,$\\
+    \hdashline\\
+    Terminate
+\end{tabular}
+\end{center}
+}
+
+\end{document}

From 58e7be233809ac49982c05936d2dec99587c3439 Mon Sep 17 00:00:00 2001
From: "James E. Stine" <james.stine@okstate.edu>
Date: Tue, 3 Oct 2023 08:11:45 -0500
Subject: [PATCH 24/32] Fix testfloat testbench to work properly with
 parameters

---
 testbench/testbench-fp.sv | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv
index 08d674f1d..2ddd13072 100644
--- a/testbench/testbench-fp.sv
+++ b/testbench/testbench-fp.sv
@@ -1000,7 +1000,7 @@ module testbenchfp;
 endmodule
 
 
-module readvectors (
+module readvectors import cvw::*; #(parameter cvw_t P) (
 		    input logic 	        clk,
 		    input logic [P.FLEN*4+7:0]  TestVector,
 		    input logic [P.FMTBITS-1:0] ModFmt,
@@ -1026,7 +1026,7 @@ module readvectors (
 		    );
 
    localparam Q_LEN = 32'd128;
-  `include "parameter-defs.vh"   
+  //`include "parameter-defs.vh"   
    
    logic 					XEn;
    logic 					YEn;

From 8b9ddd731ce194f70d7003ffc731ff1459c82890 Mon Sep 17 00:00:00 2001
From: "James E. Stine" <james.stine@okstate.edu>
Date: Tue, 3 Oct 2023 09:25:26 -0500
Subject: [PATCH 25/32] Update TeX docs divsqrt examples by removing ancillary
 files (apologies for previously pushing)

---
 docs/divsqrt_tex/div2.aux  |   2 -
 docs/divsqrt_tex/div2.log  | 531 -----------------------------------
 docs/divsqrt_tex/div2.pdf  | Bin 110314 -> 0 bytes
 docs/divsqrt_tex/div4.aux  |   2 -
 docs/divsqrt_tex/div4.log  | 527 -----------------------------------
 docs/divsqrt_tex/div4.pdf  | Bin 88257 -> 0 bytes
 docs/divsqrt_tex/sqrt2.aux |   2 -
 docs/divsqrt_tex/sqrt2.log | 557 -------------------------------------
 docs/divsqrt_tex/sqrt2.pdf | Bin 105524 -> 0 bytes
 docs/divsqrt_tex/sqrt4.aux |   2 -
 docs/divsqrt_tex/sqrt4.log | 534 -----------------------------------
 docs/divsqrt_tex/sqrt4.pdf | Bin 75105 -> 0 bytes
 12 files changed, 2157 deletions(-)
 delete mode 100644 docs/divsqrt_tex/div2.aux
 delete mode 100644 docs/divsqrt_tex/div2.log
 delete mode 100644 docs/divsqrt_tex/div2.pdf
 delete mode 100644 docs/divsqrt_tex/div4.aux
 delete mode 100644 docs/divsqrt_tex/div4.log
 delete mode 100644 docs/divsqrt_tex/div4.pdf
 delete mode 100644 docs/divsqrt_tex/sqrt2.aux
 delete mode 100644 docs/divsqrt_tex/sqrt2.log
 delete mode 100644 docs/divsqrt_tex/sqrt2.pdf
 delete mode 100644 docs/divsqrt_tex/sqrt4.aux
 delete mode 100644 docs/divsqrt_tex/sqrt4.log
 delete mode 100644 docs/divsqrt_tex/sqrt4.pdf

diff --git a/docs/divsqrt_tex/div2.aux b/docs/divsqrt_tex/div2.aux
deleted file mode 100644
index a79beafe4..000000000
--- a/docs/divsqrt_tex/div2.aux
+++ /dev/null
@@ -1,2 +0,0 @@
-\relax 
-\gdef \@abspage@last{3}
diff --git a/docs/divsqrt_tex/div2.log b/docs/divsqrt_tex/div2.log
deleted file mode 100644
index 56ed865dc..000000000
--- a/docs/divsqrt_tex/div2.log
+++ /dev/null
@@ -1,531 +0,0 @@
-This is pdfTeX, Version 3.141592653-2.6-1.40.25 (TeX Live 2023) (preloaded format=pdflatex 2023.7.19)  20 AUG 2023 13:10
-entering extended mode
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- %&-line parsing enabled.
-**div2.tex
-(./div2.tex
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-File: size12.clo 2022/07/02 v1.4n Standard LaTeX file (size option)
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From 999a50d9ee543cf02dae90d3dcf88ddc7d80ee44 Mon Sep 17 00:00:00 2001
From: VictorClements <104516656+VictorClements@users.noreply.github.com>
Date: Tue, 3 Oct 2023 07:32:45 -0700
Subject: [PATCH 26/32] Update Makefile

"make riscof" and "make testfloat" were run in backward order, leading to some of the make issues when a user is setting up for the very first time.
---
 Makefile | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Makefile b/Makefile
index 8336fe017..2c445fc46 100644
--- a/Makefile
+++ b/Makefile
@@ -4,8 +4,8 @@
 
 all:
 	make install
-	make testfloat	
-	make riscof
+	make riscof	
+	make testfloat
 	make verify
 	make coverage
 	make benchmarks

From 3156d5ababd6de4d8398f2635536892145bed72c Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Tue, 3 Oct 2023 17:37:13 -0500
Subject: [PATCH 27/32] Somehow the arty A7 was missing the update for the
 console baud rate setting.

---
 linux/devicetree/wally-artya7.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/linux/devicetree/wally-artya7.dts b/linux/devicetree/wally-artya7.dts
index 57b9599e5..4206c7804 100644
--- a/linux/devicetree/wally-artya7.dts
+++ b/linux/devicetree/wally-artya7.dts
@@ -9,7 +9,7 @@
 	chosen {
 		linux,initrd-end = <0x85c43a00>;
 		linux,initrd-start = <0x84200000>;
-		bootargs = "root=/dev/vda ro";
+		bootargs = "root=/dev/vda ro  console=ttyS0,115200";
 		stdout-path = "/soc/uart@10000000";
 	};
 

From d526d288048b0635a4ca1849edc8a05042860c02 Mon Sep 17 00:00:00 2001
From: David Harris <David_Harris@hmc.edu>
Date: Wed, 4 Oct 2023 09:34:28 -0700
Subject: [PATCH 28/32] Added MENVCFG.HADE bit and updated SVADU to depend on
 this bit

---
 src/ifu/ifu.sv                                | 27 +++++------
 src/lsu/lsu.sv                                |  5 +-
 src/mmu/hptw.sv                               | 12 +++--
 src/mmu/mmu.sv                                |  3 +-
 src/mmu/tlb/tlb.sv                            |  3 +-
 src/mmu/tlb/tlbcontrol.sv                     | 46 ++-----------------
 src/privileged/csr.sv                         |  2 +
 src/privileged/csrm.sv                        |  3 +-
 src/privileged/privileged.sv                  |  3 +-
 src/wally/wallypipelinedcore.sv               |  6 ++-
 .../WALLY-mmu-sv32-svadu-01.reference_output  | 11 ++++-
 .../rv32i_m/privilege/src/WALLY-TEST-LIB-32.h | 12 +++++
 .../privilege/src/WALLY-mmu-sv32-svadu-01.S   | 19 +++++++-
 ...9-svadu-svnapot-svpbmt-01.reference_output | 18 +++++++-
 .../WALLY-mmu-sv48-svadu-01.reference_output  | 18 +++++++-
 .../WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S  | 20 +++++++-
 .../privilege/src/WALLY-mmu-sv48-svadu-01.S   | 16 +++++++
 17 files changed, 147 insertions(+), 77 deletions(-)

diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv
index 6c81c6b99..d63a987b2 100644
--- a/src/ifu/ifu.sv
+++ b/src/ifu/ifu.sv
@@ -70,23 +70,24 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   output logic                 IClassWrongM,                             // Class prediction is wrong
   output logic                 ICacheStallF,                             // I$ busy with multicycle operation
   // Faults
-  input logic                  IllegalBaseInstrD,                        // Illegal non-compressed instruction
-  input logic                  IllegalFPUInstrD,                         // Illegal FP instruction
+  input  logic                 IllegalBaseInstrD,                        // Illegal non-compressed instruction
+  input  logic                 IllegalFPUInstrD,                         // Illegal FP instruction
   output logic                 InstrPageFaultF,                          // Instruction page fault 
   output logic                 IllegalIEUFPUInstrD,                      // Illegal instruction including compressed & FP
   output logic                 InstrMisalignedFaultM,                    // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
   // mmu management
-  input logic [1:0]            PrivilegeModeW,                           // Priviledge mode in Writeback stage
-  input logic [P.XLEN-1:0]     PTE,                                      // Hardware page table walker (HPTW) writes Page table entry (PTE) to ITLB
-  input logic [1:0]            PageType,                                 // Hardware page table walker (HPTW) writes PageType to ITLB
-  input logic                  ITLBWriteF,                               // Writes PTE and PageType to ITLB
-  input logic [P.XLEN-1:0]     SATP_REGW,                                // Location of the root page table and page table configuration
-  input logic                  STATUS_MXR,                               // Status CSR: make executable page readable 
-  input logic                  STATUS_SUM,                               // Status CSR: Supervisor access to user memory
-  input logic                  STATUS_MPRV,                              // Status CSR: modify machine privilege
-  input logic [1:0]            STATUS_MPP,                               // Status CSR: previous machine privilege level
+  input  logic [1:0]           PrivilegeModeW,                           // Priviledge mode in Writeback stage
+  input  logic [P.XLEN-1:0]    PTE,                                      // Hardware page table walker (HPTW) writes Page table entry (PTE) to ITLB
+  input  logic [1:0]           PageType,                                 // Hardware page table walker (HPTW) writes PageType to ITLB
+  input  logic                 ITLBWriteF,                               // Writes PTE and PageType to ITLB
+  input  logic [P.XLEN-1:0]    SATP_REGW,                                // Location of the root page table and page table configuration
+  input  logic                 STATUS_MXR,                               // Status CSR: make executable page readable 
+  input  logic                 STATUS_SUM,                               // Status CSR: Supervisor access to user memory
+  input  logic                 STATUS_MPRV,                              // Status CSR: modify machine privilege
+  input  logic [1:0]           STATUS_MPP,                               // Status CSR: previous machine privilege level
   input  logic                 ENVCFG_PBMTE,                             // Page-based memory types enabled
-  input logic                  sfencevmaM,                               // Virtual memory address fence, invalidate TLB entries
+  input  logic                 ENVCFG_HADE,                              // HPTW A/D Update enable
+  input  logic                 sfencevmaM,                               // Virtual memory address fence, invalidate TLB entries
   output logic                 ITLBMissF,                                // ITLB miss causes HPTW (hardware pagetable walker) walk
   output logic                 InstrUpdateDAF,                           // ITLB hit needs to update dirty or access bits
   input  var logic [7:0]       PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0],     // PMP configuration from privileged unit
@@ -171,7 +172,7 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
     assign TLBFlush = sfencevmaM & ~StallMQ;
 
     mmu #(.P(P), .TLB_ENTRIES(P.ITLB_ENTRIES), .IMMU(1))
-    immu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE,
+    immu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_HADE,
          .PrivilegeModeW, .DisableTranslation(1'b0),
          .VAdr(PCFExt),
          .Size(2'b10),
diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv
index e120d454b..191599f12 100644
--- a/src/lsu/lsu.sv
+++ b/src/lsu/lsu.sv
@@ -81,6 +81,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
   input  logic                    STATUS_MXR, STATUS_SUM, STATUS_MPRV,  // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege
   input  logic [1:0]              STATUS_MPP,                           // Machine previous privilege mode
   input  logic                    ENVCFG_PBMTE,                         // Page-based memory types enabled
+  input  logic                    ENVCFG_HADE,                          // HPTW A/D Update enable
   input  logic [P.XLEN-1:0]       PCSpillF,                             // Fetch PC 
   input  logic                    ITLBMissF,                            // ITLB miss causes HPTW (hardware pagetable walker) walk
   input  logic                    InstrUpdateDAF,                       // ITLB hit needs to update dirty or access bits
@@ -153,7 +154,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
     hptw #(P) hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF,
       .DTLBMissM, .DTLBWriteM, .InstrUpdateDAF, .DataUpdateDAM,
       .FlushW, .DCacheStallM, .SATP_REGW, .PCSpillF,
-      .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW,
+      .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_HADE, .PrivilegeModeW,
       .ReadDataM(ReadDataM[P.XLEN-1:0]), // ReadDataM is LLEN, but HPTW only needs XLEN
       .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M,
       .IEUAdrExtM, .PTE, .IHWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM,
@@ -190,7 +191,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
     assign DisableTranslation = SelHPTW | FlushDCacheM;
     assign WriteAccessM = PreLSURWM[0] | (|CMOpM);
     mmu #(.P(P), .TLB_ENTRIES(P.DTLB_ENTRIES), .IMMU(0))
-    dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE,
+    dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_HADE,
       .PrivilegeModeW, .DisableTranslation, .VAdr(IHAdrM), .Size(LSUFunct3M[1:0]),
       .PTE, .PageTypeWriteVal(PageType), .TLBWrite(DTLBWriteM), .TLBFlush(sfencevmaM),
       .PhysicalAddress(PAdrM), .TLBMiss(DTLBMissM), .Cacheable(CacheableM), .Idempotent(), .SelTIM(SelDTIM), 
diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv
index 410d1bf91..64752a992 100644
--- a/src/mmu/hptw.sv
+++ b/src/mmu/hptw.sv
@@ -38,6 +38,7 @@ module hptw import cvw::*;  #(parameter cvw_t P) (
   // system status
   input  logic              STATUS_MXR, STATUS_SUM, STATUS_MPRV,
   input  logic [1:0]        STATUS_MPP,
+  input  logic              ENVCFG_HADE,            // HPTW A/D Update enable
   input  logic [1:0]        PrivilegeModeW,
   input  logic [P.XLEN-1:0] ReadDataM,              // page table entry from LSU 
   input  logic [P.XLEN-1:0] WriteDataM,
@@ -153,7 +154,7 @@ module hptw import cvw::*;  #(parameter cvw_t P) (
     logic [P.XLEN-1:0]    AccessedPTE;
 
     assign AccessedPTE = {PTE[P.XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]}; // set accessed bit, conditionally set dirty bit
-    mux2 #(P.XLEN) NextPTEMux(ReadDataM, AccessedPTE, UpdatePTE, NextPTE);
+    mux2 #(P.XLEN) NextPTEMux(ReadDataM, AccessedPTE, UpdatePTE, NextPTE); // NextPTE = ReadDataM when HADE = 0 because UpdatePTE = 0
     flopenr #(P.PA_BITS) HPTWAdrWriteReg(clk, reset, SaveHPTWAdr, HPTWReadAdr, HPTWWriteAdr);
     
     assign SaveHPTWAdr = WalkerState == L0_ADR;
@@ -182,11 +183,12 @@ module hptw import cvw::*;  #(parameter cvw_t P) (
     // hptw needs to know if there is a Dirty or Access fault occuring on this
     // memory access.  If there is the PTE needs to be updated seting Access
     // and possibly also Dirty.  Dirty is set if the operation is a store/amo.
-    // However any other fault should not cause the update.
-    assign HPTWUpdateDA = ValidLeafPTE & (~Accessed | SetDirty) & ~OtherPageFault;
+    // However any other fault should not cause the update, and updates are in software when ENVCFG_HADE = 0
+    assign HPTWUpdateDA = ValidLeafPTE & (~Accessed | SetDirty) & ENVCFG_HADE & ~OtherPageFault;  
+
+    assign HPTWRW[0] = (WalkerState == UPDATE_PTE);           // HPTWRW[0] will always be 0 if HADE = 0 because HPTWUpdateDA will be 0 so WalkerState never is UPDATE_PTE
+    assign UpdatePTE = (WalkerState == LEAF) & HPTWUpdateDA;  // UpdatePTE will always be 0 if HADE = 0 because HPTWUpdateDA will be 0
 
-    assign HPTWRW[0] = (WalkerState == UPDATE_PTE);
-    assign UpdatePTE = (WalkerState == LEAF) & HPTWUpdateDA;
   end else begin // block: hptwwrites
     assign NextPTE = ReadDataM;
     assign HPTWAdr = HPTWReadAdr;
diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv
index e8e06fde0..32fed853d 100644
--- a/src/mmu/mmu.sv
+++ b/src/mmu/mmu.sv
@@ -35,6 +35,7 @@ module mmu import cvw::*;  #(parameter cvw_t P,
   input  logic                 STATUS_MPRV,        // Status CSR: modify machine privilege
   input  logic [1:0]           STATUS_MPP,         // Status CSR: previous machine privilege level
   input  logic                 ENVCFG_PBMTE,       // Page-based memory types enabled
+  input  logic                 ENVCFG_HADE,        // HPTW A/D Update enable
   input  logic [1:0]           PrivilegeModeW,     // Current privilege level of the processeor
   input  logic                 DisableTranslation, // virtual address translation disabled during D$ flush and HPTW walk that use physical addresses
   input  logic [P.XLEN+1:0]    VAdr,               // virtual/physical address from IEU or physical address from HPTW
@@ -82,7 +83,7 @@ module mmu import cvw::*;  #(parameter cvw_t P,
           .clk, .reset,
           .SATP_MODE(SATP_REGW[P.XLEN-1:P.XLEN-P.SVMODE_BITS]),
           .SATP_ASID(SATP_REGW[P.ASID_BASE+P.ASID_BITS-1:P.ASID_BASE]),
-          .VAdr(VAdr[P.XLEN-1:0]), .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE,
+          .VAdr(VAdr[P.XLEN-1:0]), .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_HADE,
           .PrivilegeModeW, .ReadAccess, .WriteAccess,
           .DisableTranslation, .PTE, .PageTypeWriteVal,
           .TLBWrite, .TLBFlush, .TLBPAdr, .TLBMiss, .TLBHit, 
diff --git a/src/mmu/tlb/tlb.sv b/src/mmu/tlb/tlb.sv
index 9619c958d..861e721b6 100644
--- a/src/mmu/tlb/tlb.sv
+++ b/src/mmu/tlb/tlb.sv
@@ -58,6 +58,7 @@ module tlb import cvw::*;  #(parameter cvw_t P,
   input  logic                     STATUS_MXR, STATUS_SUM, STATUS_MPRV,
   input  logic [1:0]               STATUS_MPP,
   input  logic                     ENVCFG_PBMTE,     // Page-based memory types enabled
+  input  logic                     ENVCFG_HADE,      // HPTW A/D Update enable
   input  logic [1:0]               PrivilegeModeW,   // Current privilege level of the processeor
   input  logic                     ReadAccess, 
   input  logic                     WriteAccess,
@@ -104,7 +105,7 @@ module tlb import cvw::*;  #(parameter cvw_t P,
 
   assign VPN = VAdr[P.VPN_BITS+11:12];
 
-  tlbcontrol #(P, ITLB) tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE,
+  tlbcontrol #(P, ITLB) tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_HADE,
     .PrivilegeModeW, .ReadAccess, .WriteAccess, .DisableTranslation, .TLBFlush,
     .PTEAccessBits, .CAMHit, .Misaligned, 
     .TLBMiss, .TLBHit, .TLBPageFault, 
diff --git a/src/mmu/tlb/tlbcontrol.sv b/src/mmu/tlb/tlbcontrol.sv
index 3c2f81697..666448b12 100644
--- a/src/mmu/tlb/tlbcontrol.sv
+++ b/src/mmu/tlb/tlbcontrol.sv
@@ -32,10 +32,11 @@ module tlbcontrol import cvw::*;  #(parameter cvw_t P, ITLB = 0) (
   input  logic                     STATUS_MXR, STATUS_SUM, STATUS_MPRV,
   input  logic [1:0]               STATUS_MPP,
   input  logic                     ENVCFG_PBMTE,       // Page-based memory types enabled
-  input  logic [1:0]               PrivilegeModeW, // Current privilege level of the processeor
+  input  logic                     ENVCFG_HADE,        // HPTW A/D Update enable
+  input  logic [1:0]               PrivilegeModeW,     // Current privilege level of the processeor
   input  logic                     ReadAccess, WriteAccess,
   input  logic                     DisableTranslation,
-  input  logic                     TLBFlush, // Invalidate all TLB entries
+  input  logic                     TLBFlush,           // Invalidate all TLB entries
   input  logic [11:0]              PTEAccessBits,
   input  logic                     CAMHit,
   input  logic                     Misaligned,
@@ -114,50 +115,13 @@ module tlbcontrol import cvw::*;  #(parameter cvw_t P, ITLB = 0) (
   end
 
   // Determine wheter to update DA bits.  With SVADU, it is done in hardware
-  if (P.SVADU_SUPPORTED) assign UpdateDA = PreUpdateDA & Translate & TLBHit & ~TLBPageFault;
+  if (P.SVADU_SUPPORTED) assign UpdateDA = PreUpdateDA & Translate & TLBHit & ~TLBPageFault & ENVCFG_HADE;
   else                   assign UpdateDA = PreUpdateDA;
 
   // Determine whether page fault occurs
-  assign PrePageFault = UpperBitsUnequal | Misaligned | ~PTE_V | ImproperPrivilege | (P.XLEN == 64 & (BadPBMT | BadNAPOT | BadReserved)) | (PreUpdateDA & ~P.SVADU_SUPPORTED);
+  assign PrePageFault = UpperBitsUnequal | Misaligned | ~PTE_V | ImproperPrivilege | (P.XLEN == 64 & (BadPBMT | BadNAPOT | BadReserved)) | (PreUpdateDA & (~P.SVADU_SUPPORTED | ~ENVCFG_HADE));
   assign TLBPageFault = Translate & TLBHit & (PrePageFault | InvalidAccess);
 
-/*
-  // Check whether the access is allowed, page faulting if not.
-  if (ITLB == 1) begin:itlb // Instruction TLB fault checking
-    // User mode may only execute user mode pages, and supervisor mode may
-    // only execute non-user mode pages.
-    assign ImproperPrivilege = ((EffectivePrivilegeMode == P.U_MODE) & ~PTE_U) |
-      ((EffectivePrivilegeMode == P.S_MODE) & PTE_U);
-    assign CausePageFault = ImproperPrivilege | ~PTE_X | UpperBitsUnequal | BadPTE | BadPBMT | Misaligned | ~PTE_V | (~PTE_A & P.SVADU_SUPPORTED);
-    assign TLBPageFault = Translate  & TLBHit & CausePageFault;
-    // Determine wheter to update DA bits
-    if(P.SVADU_SUPPORTED) assign UpdateDA = Translate & TLBHit & ~PTE_A & ~TLBPageFault;
-    else                  assign UpdateDA = ~PTE_A;
-  end else begin:dtlb // Data TLB fault checking
-    logic InvalidRead, InvalidWrite;
-
-    // User mode may only load/store from user mode pages, and supervisor mode
-    // may only access user mode pages when STATUS_SUM is low.
-    assign ImproperPrivilege = ((EffectivePrivilegeMode == P.U_MODE) & ~PTE_U) |
-      ((EffectivePrivilegeMode == P.S_MODE) & PTE_U & ~STATUS_SUM);
-    // Check for read error. Reads are invalid when the page is not readable
-    // (and executable pages are not readable) or when the page is neither
-    // readable nor executable (and executable pages are readable).
-    assign InvalidRead = ReadAccess & ~PTE_R & (~STATUS_MXR | ~PTE_X);
-    // Check for write error. Writes are invalid when the page's write bit is
-    // low.
-    assign InvalidWrite = WriteAccess & ~PTE_W;
-    if(P.SVADU_SUPPORTED) begin : hptwwrites
-      assign UpdateDA = Translate & TLBHit & (~PTE_A | WriteAccess & ~PTE_D) & ~TLBPageFault; 
-      assign TLBPageFault =  (Translate & TLBHit & (ImproperPrivilege | InvalidRead | InvalidWrite | UpperBitsUnequal | Misaligned | ~PTE_V)); // *** update to match
-    end else begin
-      // Fault for software handling if access bit is off or writing a page with dirty bit off
-      assign UpdateDA = ~PTE_A | WriteAccess & ~PTE_D; 
-      assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | InvalidRead | InvalidWrite | UpdateDA | UpperBitsUnequal | Misaligned | ~PTE_V));
-    end
-  end
-*/
-
   assign TLBHit = CAMHit & TLBAccess;
   assign TLBMiss = ~CAMHit & TLBAccess & Translate ;
 endmodule
diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv
index f99ee28b1..4cdce4989 100644
--- a/src/privileged/csr.sv
+++ b/src/privileged/csr.sv
@@ -86,6 +86,7 @@ module csr import cvw::*;  #(parameter cvw_t P) (
   output logic [2:0]               FRM_REGW, 
   output logic [3:0]               ENVCFG_CBE,
   output logic                     ENVCFG_PBMTE,              // Page-based memory type enable
+  output logic                     ENVCFG_HADE,               // HPTW A/D Update enable
   //
   output logic [P.XLEN-1:0]        CSRReadValW,               // value read from CSR
   output logic [P.XLEN-1:0]        UnalignedPCNextF,          // Next PC, accounting for traps and returns
@@ -292,6 +293,7 @@ module csr import cvw::*;  #(parameter cvw_t P) (
    // Broadcast appropriate environment configuration based on privilege mode
   assign ENVCFG_STCE =  MENVCFG_REGW[63]; // supervisor timer counter enable
   assign ENVCFG_PBMTE = MENVCFG_REGW[62]; // page-based memory types enable
+  assign ENVCFG_HADE  = MENVCFG_REGW[61]; // Hardware A/D Update enable
   assign ENVCFG_CBE =   (PrivilegeModeW == P.M_MODE) ? 4'b1111 : 
                         (PrivilegeModeW == P.S_MODE | !P.S_SUPPORTED) ? MENVCFG_REGW[7:4] : 
                                                                        (MENVCFG_REGW[7:4] & SENVCFG_REGW[7:4]);
diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv
index 359406b1f..ad1f9b75d 100644
--- a/src/privileged/csrm.sv
+++ b/src/privileged/csrm.sv
@@ -172,7 +172,8 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
     assign MENVCFG_WriteValM = {
       MENVCFG_PreWriteValM[63]  & P.SSTC_SUPPORTED,
       MENVCFG_PreWriteValM[62]  & P.SVPBMT_SUPPORTED,
-      54'b0,
+      MENVCFG_PreWriteValM[61]  & P.SVADU_SUPPORTED,
+      53'b0,
       MENVCFG_PreWriteValM[7]   & P.ZICBOZ_SUPPORTED,
       MENVCFG_PreWriteValM[6:4] & {3{P.ZICBOM_SUPPORTED}},
       3'b0,
diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv
index 619ed2b32..fff4af8b8 100644
--- a/src/privileged/privileged.sv
+++ b/src/privileged/privileged.sv
@@ -84,6 +84,7 @@ module privileged import cvw::*;  #(parameter cvw_t P) (
   output logic [2:0]        FRM_REGW,                                       // FPU rounding mode
   output logic [3:0]        ENVCFG_CBE,                                     // Cache block operation enables
   output logic              ENVCFG_PBMTE,                                   // Page-based memory type enable
+  output logic              ENVCFG_HADE,                                    // HPTW A/D Update enable
   // PC logic output in privileged unit                                    
   output logic [P.XLEN-1:0] UnalignedPCNextF,                               // Next PC from trap/return PC logic
   // control outputs                                                       
@@ -138,7 +139,7 @@ module privileged import cvw::*;  #(parameter cvw_t P) (
     .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW, .STATUS_FS,
     .MEDELEG_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
     .SATP_REGW, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
-    .SetFflagsM, .FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE,
+    .SetFflagsM, .FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_HADE,
     .CSRReadValW,.UnalignedPCNextF, .IllegalCSRAccessM, .BigEndianM);
 
   // pipeline early-arriving trap sources
diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv
index 5fbc89a26..00b348660 100644
--- a/src/wally/wallypipelinedcore.sv
+++ b/src/wally/wallypipelinedcore.sv
@@ -78,6 +78,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
   logic                          LoadStallD, StoreStallD, MDUStallD, CSRRdStallD;
   logic                          SquashSCW;
   logic                          MDUActiveE;                      // Mul/Div instruction being executed
+  logic                          ENVCFG_HADE;                     // HPTW A/D Update enable
   logic                          ENVCFG_PBMTE;                    // Page-based memory type enable
   logic [3:0]                    ENVCFG_CBE;                      // Cache Block operation enables
   logic [3:0]                    CMOpM;                           // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
@@ -185,7 +186,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
     .IllegalBaseInstrD, .IllegalFPUInstrD, .InstrPageFaultF, .IllegalIEUFPUInstrD, .InstrMisalignedFaultM,
     // mmu management
     .PrivilegeModeW, .PTE, .PageType, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV,
-    .STATUS_MPP, .ENVCFG_PBMTE, .ITLBWriteF, .sfencevmaM, .ITLBMissF,
+    .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_HADE, .ITLBWriteF, .sfencevmaM, .ITLBMissF,
     // pmp/pma (inside mmu) signals. 
     .PMPCFG_ARRAY_REGW,  .PMPADDR_ARRAY_REGW, .InstrAccessFaultF, .InstrUpdateDAF); 
     
@@ -234,6 +235,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
     .STATUS_MPRV,                 // from csr            
     .STATUS_MPP,                  // from csr     
     .ENVCFG_PBMTE,                // from csr
+    .ENVCFG_HADE,                 // from csr
     .sfencevmaM,                  // connects to privilege
     .DCacheStallM,                // connects to privilege
     .LoadPageFaultM,              // connects to privilege
@@ -296,7 +298,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
       .PrivilegeModeW, .SATP_REGW,
       .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS, 
       .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, 
-      .FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .BreakpointFaultM, .EcallFaultM, .wfiM, .IntPendingM, .BigEndianM);
+      .FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_HADE, .BreakpointFaultM, .EcallFaultM, .wfiM, .IntPendingM, .BigEndianM);
   end else begin
     assign CSRReadValW      = 0;
     assign UnalignedPCNextF = PC2NextF;
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mmu-sv32-svadu-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mmu-sv32-svadu-01.reference_output
index 9d88117e6..6a88d9ec7 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mmu-sv32-svadu-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mmu-sv32-svadu-01.reference_output
@@ -35,8 +35,15 @@ beef0110
 0000000f
 0000000c
 00000bad
-beef0770 # Test 11.3.1.3.5: check successful read/write when A=0 and SVADU=1
-beef0aa0 # Test 11.3.1.3.6: check successful read/write when D=0 and SVADU=1
+0000000f # Test 11.3.1.3.6(a) page fault on write when A = 0
+0000000d # Test 11.3.1.3.6(a) page fault on read when A = 0
+00000bad
+0000000f # Test 11.3.1.3.7(a) page fault on write when D = 0
+deadbeef # Test 11.3.1.3.7(a) successful read when D = 0
+00000009 # call from going to m mode from s mode
+0000000b # ecall from going to S mode from m mode
+beef0770 # Test 11.3.1.3.6: check successful read/write when A=0 and MENVCFG.HADE=1
+beef0aa0 # Test 11.3.1.3.7: check successful read/write when D=0 and MENVCFG.HADE=1
 beef0077 # Test 11.3.1.4.1: successful read back of saved value with new memory mapping
 00000009 # Test 11.3.1.5.1: ecall from going to m mode from s mode
 00000000 # previous value of mprv before being set
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
index c51eec965..b6304fbc6 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
@@ -1324,6 +1324,18 @@ write_mideleg:
     csrw mideleg, t4
     j test_loop
 
+write_menvcfg:
+    // writes the value in t4 to the menvcfg register
+    // Doesn't log anything
+    csrw menvcfg, t4
+    j test_loop
+
+write_menvcfgh:
+    // writes the value in t4 to the menvcfgh register
+    // Doesn't log anything
+    csrw menvcfgh, t4
+    j test_loop
+
 executable_test:
     // Execute the code at the address in t3, returning the value in t2.
     // Assumes the code modifies t2, to become the value stored in t4 for this test.  
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S
index 1a4a32cba..6a40d3b17 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S
@@ -157,13 +157,28 @@ test_cases:
 .4byte 0xBFFDE0, 0xbad, executable_test             # instr page fault when X=0 
 
 # In the following two tests, SVADU is supported, so the hardware handles the A/D bits
+# Initially test with HADE = 0, so needing to set A/D bits triggers page fault
+
+# test 11.3.1.3.6(a) Accessed flag == 0
+.4byte 0x3020, 0xBEEF0770, write32_test     # store page fault when A=0
+.4byte 0x3020, 0xBEEF0770, read32_test  # load page fault when A=0
+
+# test 11.3.1.3.7(a) Dirty flag == 0
+.4byte 0x4658, 0xBEEF0AA0, write32_test # store page fault when D=0
+.4byte 0x4658, 0xDEADBEEF, read32_test  # read success when D=0; default DEADBEEF value wasn't changed
+
+# Now set HADE bit
+.4byte 0x0, 0x0, goto_m_mode # change to M mode, 0x9 written to output
+.4byte 0x0, 0x20000000, write_menvcfgh  # set menvcfg.HADE = 1
+.4byte 0x0, 0x0, goto_s_mode # change to S mode, 0xb written to output
+
 # Since SVADU is 1, there are no faults when A/D=0
 
-# test 11.3.1.3.6 Accessed flag == 0
+# test 11.3.1.3.6(b) Accessed flag == 0
 .4byte 0x3020, 0xBEEF0770, write32_test # Write success when A=0 and SVADU is enabled
 .4byte 0x3020, 0xBEEF0770, read32_test # Read success when A=0 and SVADU is enabled
 
-# test 11.3.1.3.7 Dirty flag == 0
+# test 11.3.1.3.7(b) Dirty flag == 0
 .4byte 0x4658, 0xBEEF0AA0, write32_test # write successs when D=0 and SVADU is enabled
 .4byte 0x4658, 0xBEEF0AA0, read32_test # read success when D=0
 
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.reference_output
index 93e4557a5..320d3f9c4 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.reference_output
@@ -84,9 +84,23 @@ beef0110 # Test 11.3.1.3.4: read test success
 00000000
 00000bad
 00000000
-beef0770 # Test 11.3.1.3.6: check successful read/write when A=0 and SVADU=1 
+0000000f # Test 11.3.1.3.6(a): write test with page fault
+00000000
+0000000d # read test with page fault
+00000000
+00000bad
+00000000
+0000000f # Test 11.3.1.3.7(a): write test with page fault
+00000000
+deadbeef # read test success but nothing was written so read back default
+deadbeef
+00000009 # ecall from going to M mode from S mode
+00000000
+0000000B # ecall from going to S mode from M mode
+00000000
+beef0770 # Test 11.3.1.3.6(b): check successful read/write when A=0 and SVADU=1 
 0990dead
-beef0aa0 # Test 11.3.1.3.7: check successful read/write when D=0 and SVADU=1
+beef0aa0 # Test 11.3.1.3.7(b): check successful read/write when D=0 and SVADU=1
 0440dead
 0000000d # Test 11.3.1.3.8: read test with page fault for nonzero reserved bit
 00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv48-svadu-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv48-svadu-01.reference_output
index 60fce42ef..dd3801705 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv48-svadu-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv48-svadu-01.reference_output
@@ -92,9 +92,23 @@ beef0110 # Test 11.3.1.3.4: read test success
 00000000
 00000bad
 00000000 
-beef0770 # Test 11.3.1.3.5: check successful read/write when A=0 and SVADU=1
+0000000f # Test 11.3.1.3.6(a): write test with page fault
+00000000
+0000000d # read test with page fault
+00000000
+00000bad
+00000000
+0000000f # Test 11.3.1.3.7(a): write test with page fault
+00000000
+deadbeef # read test success but get deadbeef because nothing was written
+deadbeef
+00000009 # ecall from going to M mode from S mode
+00000000
+0000000B # ecall from going to S mode from M mode
+00000000
+beef0770 # Test 11.3.1.3.6(b): check successful read/write when A=0 and SVADU=1
 0990dead
-beef0aa0 # Test 11.3.1.3.6: check successful read/write when D=0 and SVADU=1
+beef0aa0 # Test 11.3.1.3.7(b): check successful read/write when D=0 and SVADU=1
 0440dead
 beef0000 # Test 11.3.1.4.1: read test success on new page table mapping
 0000dead 
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S
index aae04dd68..7da29bb94 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S
@@ -194,13 +194,29 @@ test_cases:
 # *** fetches on pages with X = 1 already tested in 11.3.1.3.1
 .8byte 0x5AA0, 0x1, executable_test                 # instr page fault when X=0
 
+
 # In the following two tests, SVADU is supported, so the hardware handles the A/D bits
+# Initially test with HADE = 0, so needing to set A/D bits triggers page fault
+
+# test 11.3.1.3.6(a) Accessed flag == 0
+.8byte 0x36D0, 0x0990DEADBEEF0770, write64_test# store page fault when A=0
+.8byte 0x3AB8, 0x0990DEADBEEF0990, read64_test# load page fault when A=0
+
+# test 11.3.1.3.7(a) Dirty flag == 0
+.8byte 0x4658, 0x0440DEADBEEF0AA0, write64_test# store page fault when D=0
+.8byte 0x4AA0, 0xDEADBEEFDEADBEEF, read64_test# read success when D=0
+
+# Now set HADE bit
+.8byte 0x0, 0x0, goto_m_mode # change to M mode, 0x9 written to output
+.8byte 0x0, 0x2000000000000000, write_menvcfg  # set menvcfg.HADE = 1
+.8byte 0x0, 0x0, goto_s_mode # change to S mode, 0xb written to output
+
 # Since SVADU is 1, there are no faults when A/D=0
-# test 11.3.1.3.6 Accessed flag == 0
+# test 11.3.1.3.6(b) Accessed flag == 0
 .8byte 0x36D0, 0x0990DEADBEEF0770, write64_test # Write success when A=0 and SVADU is enabled
 .8byte 0x36D0, 0x0990DEADBEEF0770, read64_test # Read success when A=0 and SVADU is enabled
 
-# test 11.3.1.3.7 Dirty flag == 0
+# test 11.3.1.3.7(b) Dirty flag == 0
 .8byte 0x4658, 0x0440DEADBEEF0AA0, write64_test # Write success when D=0 and SVADU is enabled
 .8byte 0x4658, 0x0440DEADBEEF0AA0, read64_test # read success when D=0
 
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S
index dc8424f14..96d5aec11 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S
@@ -187,7 +187,23 @@ test_cases:
 # executes on pages with X = 1 already tested in 11.3.1.3.1
 .8byte 0x010088888000, 0x2, executable_test               # execute fault when X=0 
 
+
 # In the following two tests, SVADU is supported, so the hardware handles the A/D bits
+# Initially test with HADE = 0, so needing to set A/D bits triggers page fault
+
+# test 11.3.1.3.6(a) Accessed flag == 0
+.8byte 0x802036D0, 0x0990DEADBEEF0770, write64_test # store page fault when A=0
+.8byte 0x802036D0, 0x0990DEADBEEF0990, read64_test  # load page fault when A=0
+
+# test 11.3.1.3.7(a) Dirty flag == 0
+.8byte 0x80204658, 0x0440DEADBEEF0AA0, write64_test # store page fault when D=0
+.8byte 0x80204658, 0xDEADBEEFDEADBEEF, read64_test  # read success when D=0
+
+# Now set HADE bit
+.8byte 0x0, 0x0, goto_m_mode # change to M mode, 0x9 written to output
+.8byte 0x0, 0x2000000000000000, write_menvcfg  # set menvcfg.HADE = 1
+.8byte 0x0, 0x0, goto_s_mode # change to S mode, 0xb written to output
+
 # Since SVADU is 1, there are no faults when A/D=0
 
 # test 11.3.1.3.6 Accessed flag == 0

From 19a6bbb01bf1c2b379446a4166e6cd1b96ae42f8 Mon Sep 17 00:00:00 2001
From: David Harris <David_Harris@hmc.edu>
Date: Wed, 4 Oct 2023 09:57:13 -0700
Subject: [PATCH 29/32] UpdateDA cleanup: don't assert UpdateDA when there is
 no SVADU

---
 src/ifu/spill.sv          | 1 +
 src/mmu/tlb/tlbcontrol.sv | 3 +--
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/ifu/spill.sv b/src/ifu/spill.sv
index a82f4e9bf..d6e6a75e4 100644
--- a/src/ifu/spill.sv
+++ b/src/ifu/spill.sv
@@ -83,6 +83,7 @@ module spill import cvw::*;  #(parameter cvw_t P) (
     assign SpillF = CacheableF ? SpillCachedF : SpillUncachedF;
   end else
     assign SpillF = PCF[1]; // *** might relax - only spill if next instruction is uncompressed
+  // Don't take the spill if there is a stall, TLB miss, or hardware update to the D/A bits
   assign TakeSpillF = SpillF & ~IFUCacheBusStallF & ~(ITLBMissF | (P.SVADU_SUPPORTED & InstrUpdateDAF));
   
   always_ff @(posedge clk)
diff --git a/src/mmu/tlb/tlbcontrol.sv b/src/mmu/tlb/tlbcontrol.sv
index 666448b12..31312f767 100644
--- a/src/mmu/tlb/tlbcontrol.sv
+++ b/src/mmu/tlb/tlbcontrol.sv
@@ -115,8 +115,7 @@ module tlbcontrol import cvw::*;  #(parameter cvw_t P, ITLB = 0) (
   end
 
   // Determine wheter to update DA bits.  With SVADU, it is done in hardware
-  if (P.SVADU_SUPPORTED) assign UpdateDA = PreUpdateDA & Translate & TLBHit & ~TLBPageFault & ENVCFG_HADE;
-  else                   assign UpdateDA = PreUpdateDA;
+  assign UpdateDA = P.SVADU_SUPPORTED & PreUpdateDA & Translate & TLBHit & ~TLBPageFault & ENVCFG_HADE;
 
   // Determine whether page fault occurs
   assign PrePageFault = UpperBitsUnequal | Misaligned | ~PTE_V | ImproperPrivilege | (P.XLEN == 64 & (BadPBMT | BadNAPOT | BadReserved)) | (PreUpdateDA & (~P.SVADU_SUPPORTED | ~ENVCFG_HADE));

From 28752303be0b8a0386aaa7a99ad64baba8700824 Mon Sep 17 00:00:00 2001
From: David Harris <David_Harris@hmc.edu>
Date: Wed, 4 Oct 2023 12:28:12 -0700
Subject: [PATCH 30/32] Added ZCA/ZCF/ZCD/ZCB support.  Doesn't break
 regression, but not tested.  Need to get tests for Zcb.  Draft tests are in
 riscv-arch-test but not yet committed there

---
 config/buildroot/config.vh          |   6 ++
 config/fpga/config.vh               |   6 ++
 config/rv32e/config.vh              |   6 ++
 config/rv32gc/config.vh             |   6 ++
 config/rv32i/config.vh              |   6 ++
 config/rv32imc/config.vh            |   6 ++
 config/rv64fpquad/config.vh         |   6 ++
 config/rv64gc/config.vh             |   6 ++
 config/rv64i/config.vh              |   6 ++
 config/shared/parameter-defs.vh     |   4 +
 src/cvw.sv                          |   6 ++
 src/ifu/decompress.sv               | 116 ++++++++++++++++++++++------
 src/ifu/ifu.sv                      |   4 +-
 testbench/common/riscvassertions.sv |   5 ++
 14 files changed, 163 insertions(+), 26 deletions(-)

diff --git a/config/buildroot/config.vh b/config/buildroot/config.vh
index 79ee99f3c..b25e8fe9c 100644
--- a/config/buildroot/config.vh
+++ b/config/buildroot/config.vh
@@ -158,6 +158,12 @@ localparam ZBB_SUPPORTED = 0;
 localparam ZBC_SUPPORTED = 0;
 localparam ZBS_SUPPORTED = 0;
 
+// New compressed instructions
+localparam ZCB_SUPPORTED = 1;
+localparam ZCA_SUPPORTED = 0;
+localparam ZCF_SUPPORTED = 0;
+localparam ZCD_SUPPORTED = 0;
+
 // Memory synthesis configuration
 localparam USE_SRAM = 0;
 
diff --git a/config/fpga/config.vh b/config/fpga/config.vh
index 27903d0be..2508b557e 100644
--- a/config/fpga/config.vh
+++ b/config/fpga/config.vh
@@ -171,6 +171,12 @@ localparam ZBB_SUPPORTED = 1;
 localparam ZBC_SUPPORTED = 1;
 localparam ZBS_SUPPORTED = 1;
 
+// New compressed instructions
+localparam ZCB_SUPPORTED = 1;
+localparam ZCA_SUPPORTED = 0;
+localparam ZCF_SUPPORTED = 0;
+localparam ZCD_SUPPORTED = 0;
+
 // Memory synthesis configuration
 localparam USE_SRAM = 0;
 
diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh
index c67e71c13..35e85003d 100644
--- a/config/rv32e/config.vh
+++ b/config/rv32e/config.vh
@@ -159,6 +159,12 @@ localparam ZBB_SUPPORTED = 0;
 localparam ZBC_SUPPORTED = 0;
 localparam ZBS_SUPPORTED = 0;
 
+// New compressed instructions
+localparam ZCB_SUPPORTED = 0;
+localparam ZCA_SUPPORTED = 0;
+localparam ZCF_SUPPORTED = 0;
+localparam ZCD_SUPPORTED = 0;
+
 // Memory synthesis configuration
 localparam USE_SRAM = 0;
 
diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh
index de966b1f2..06be2e01b 100644
--- a/config/rv32gc/config.vh
+++ b/config/rv32gc/config.vh
@@ -171,6 +171,12 @@ localparam ZBB_SUPPORTED = 1;
 localparam ZBC_SUPPORTED = 1;
 localparam ZBS_SUPPORTED = 1;
 
+// New compressed instructions
+localparam ZCB_SUPPORTED = 1;
+localparam ZCA_SUPPORTED = 0;
+localparam ZCF_SUPPORTED = 0;
+localparam ZCD_SUPPORTED = 0;
+
 // Memory synthesis configuration
 localparam USE_SRAM = 0;
 
diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh
index a31e034df..5e03d3e93 100644
--- a/config/rv32i/config.vh
+++ b/config/rv32i/config.vh
@@ -159,6 +159,12 @@ localparam ZBB_SUPPORTED = 0;
 localparam ZBC_SUPPORTED = 0;
 localparam ZBS_SUPPORTED = 0;
 
+// New compressed instructions
+localparam ZCB_SUPPORTED = 0;
+localparam ZCA_SUPPORTED = 0;
+localparam ZCF_SUPPORTED = 0;
+localparam ZCD_SUPPORTED = 0;
+
 // Memory synthesis configuration
 localparam USE_SRAM = 0;
 
diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh
index 61eea7325..cb031d2db 100644
--- a/config/rv32imc/config.vh
+++ b/config/rv32imc/config.vh
@@ -158,6 +158,12 @@ localparam ZBB_SUPPORTED = 0;
 localparam ZBC_SUPPORTED = 0;
 localparam ZBS_SUPPORTED = 0;
 
+// New compressed instructions
+localparam ZCB_SUPPORTED = 0;
+localparam ZCA_SUPPORTED = 0;
+localparam ZCF_SUPPORTED = 0;
+localparam ZCD_SUPPORTED = 0;
+
 // Memory synthesis configuration
 localparam USE_SRAM = 0;
 
diff --git a/config/rv64fpquad/config.vh b/config/rv64fpquad/config.vh
index d8bf3e6fc..63a35c7f5 100644
--- a/config/rv64fpquad/config.vh
+++ b/config/rv64fpquad/config.vh
@@ -161,6 +161,12 @@ localparam ZBB_SUPPORTED = 0;
 localparam ZBC_SUPPORTED = 0;
 localparam ZBS_SUPPORTED = 0;
 
+// New compressed instructions
+localparam ZCB_SUPPORTED = 0;
+localparam ZCA_SUPPORTED = 0;
+localparam ZCF_SUPPORTED = 0;
+localparam ZCD_SUPPORTED = 0;
+
 // Memory synthesis configuration
 localparam USE_SRAM = 0;
 
diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh
index 36d99020e..f17761e33 100644
--- a/config/rv64gc/config.vh
+++ b/config/rv64gc/config.vh
@@ -164,6 +164,12 @@ localparam ZBB_SUPPORTED = 1;
 localparam ZBC_SUPPORTED = 1;
 localparam ZBS_SUPPORTED = 1;
 
+// New compressed instructions
+localparam ZCB_SUPPORTED = 1;
+localparam ZCA_SUPPORTED = 0;
+localparam ZCF_SUPPORTED = 0;
+localparam ZCD_SUPPORTED = 0;
+
 // Memory synthesis configuration
 localparam USE_SRAM = 0;
 
diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh
index 6add96e78..d87708c18 100644
--- a/config/rv64i/config.vh
+++ b/config/rv64i/config.vh
@@ -161,6 +161,12 @@ localparam ZBB_SUPPORTED = 0;
 localparam ZBC_SUPPORTED = 0;
 localparam ZBS_SUPPORTED = 0;
 
+// New compressed instructions
+localparam ZCB_SUPPORTED = 0;
+localparam ZCA_SUPPORTED = 0;
+localparam ZCF_SUPPORTED = 0;
+localparam ZCD_SUPPORTED = 0;
+
 // Memory synthesis configuration
 localparam USE_SRAM = 0;
 
diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh
index 4921f6a3d..f3f216062 100644
--- a/config/shared/parameter-defs.vh
+++ b/config/shared/parameter-defs.vh
@@ -96,6 +96,10 @@ localparam cvw_t P = '{
   ZBB_SUPPORTED :        ZBB_SUPPORTED,
   ZBC_SUPPORTED :        ZBC_SUPPORTED,
   ZBS_SUPPORTED :        ZBS_SUPPORTED,
+  ZCA_SUPPORTED :        ZCA_SUPPORTED,
+  ZCB_SUPPORTED :        ZCB_SUPPORTED,
+  ZCD_SUPPORTED :        ZCD_SUPPORTED,
+  ZCF_SUPPORTED :        ZCF_SUPPORTED,
   USE_SRAM :        USE_SRAM,
   M_MODE  : M_MODE, 
   S_MODE  : S_MODE, 
diff --git a/src/cvw.sv b/src/cvw.sv
index f64618574..01e0d6376 100644
--- a/src/cvw.sv
+++ b/src/cvw.sv
@@ -161,6 +161,12 @@ typedef struct packed {
   logic         ZBC_SUPPORTED;
   logic         ZBS_SUPPORTED;
 
+// compressed
+  logic         ZCA_SUPPORTED;
+  logic         ZCB_SUPPORTED;
+  logic         ZCD_SUPPORTED;
+  logic         ZCF_SUPPORTED;
+
 // Memory synthesis configuration
   logic         USE_SRAM;
 
diff --git a/src/ifu/decompress.sv b/src/ifu/decompress.sv
index 1605ed039..5c4395a12 100644
--- a/src/ifu/decompress.sv
+++ b/src/ifu/decompress.sv
@@ -30,7 +30,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 
-module decompress #(parameter XLEN)(
+module decompress import cvw::*;  #(parameter cvw_t P) (
   input  logic [31:0] InstrRawD,         // 32-bit instruction or raw compressed 16-bit instruction in bottom half
   output logic [31:0] InstrD,            // Decompressed instruction
   output logic        IllegalCompInstrD  // Invalid decompressed instruction
@@ -88,20 +88,60 @@ module decompress #(parameter XLEN)(
                     IllegalCompInstrD = 1;
                     InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
                   end
-        5'b00001: InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000111}; // c.fld
+        5'b00001: if (P.C_SUPPORTED & P.D_SUPPORTED | P.ZCD_SUPPORTED)
+                    InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000111}; // c.fld
+                  else begin // unsupported instruction
+                    IllegalCompInstrD = 1;
+                    InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
+                  end
         5'b00010: InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000011}; // c.lw
-        5'b00011: if (XLEN==32)
-                    InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000111}; // c.flw
+        5'b00011: if (P.XLEN==32)
+                    if (P.C_SUPPORTED & P.F_SUPPORTED | P.ZCF_SUPPORTED) 
+                      InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000111}; // c.flw
+                    else begin
+                      IllegalCompInstrD = 1;
+                      InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
+                    end
                   else
                     InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000011}; // c.ld;
-        5'b00101: InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100111}; // c.fsd
+        5'b00100: if (P.ZCB_SUPPORTED) 
+                    if (instr16[12:10] == 3'b000) 
+                      InstrD = {10'b0, instr16[6:5], rs1p, 3'b100, rdp, 7'b0000011}; // c.lbu
+                    else if (instr16[12:10] == 3'b001) begin
+                      if (instr16[6]) 
+                        InstrD = {10'b0, instr16[5], 1'b0, rs1p, 3'b001, rdp, 7'b0000011}; // c.lh
+                      else
+                        InstrD = {10'b0, instr16[5], 1'b0, rs1p, 3'b101, rdp, 7'b0000011}; // c.lhu
+                    end else if (instr16[12:10] == 3'b010)
+                      InstrD = {7'b0, rs2p, rs1p, 3'b000, 3'b000, instr16[6:5], 7'b0000011}; // c.sb 
+                    else if (instr16[12:10] == 3'b011 & instr16[6] == 1'b0)
+                      InstrD = {7'b0, rs2p, rs1p, 3'b001, 3'b000, instr16[5], 1'b0, 7'b0000011}; // c.sh
+                    else begin
+                      IllegalCompInstrD = 1;
+                      InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
+                    end
+                 else begin
+                    IllegalCompInstrD = 1;
+                    InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
+                  end
+        5'b00101: if (P.C_SUPPORTED & P.D_SUPPORTED | P.ZCD_SUPPORTED)
+                    InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100111}; // c.fsd
+                  else begin // unsupported instruction
+                    IllegalCompInstrD = 1;
+                    InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
+                  end
         5'b00110: InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100011}; // c.sw
-        5'b00111: if (XLEN==32)
-                    InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111}; // c.fsw
+        5'b00111: if (P.XLEN==32)
+                    if (P.C_SUPPORTED & P.F_SUPPORTED | P.ZCF_SUPPORTED) 
+                      InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111}; // c.fsw
+                    else begin
+                      IllegalCompInstrD = 1;
+                      InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
+                    end
                   else
                     InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100011}; //c.sd
         5'b01000: InstrD = {immCI, rds1, 3'b000, rds1, 7'b0010011}; // c.addi
-        5'b01001: if (XLEN==32) 
+        5'b01001: if (P.XLEN==32) 
                     InstrD = {immCJ, 5'b00001, 7'b1101111}; // c.jal
                   else
                     InstrD = {immCI, rds1, 3'b000, rds1, 7'b0011011}; // c.addiw
@@ -125,33 +165,51 @@ module decompress #(parameter XLEN)(
                       InstrD = {7'b0000000, rs2p, rds1p, 3'b110, rds1p, 7'b0110011}; // c.or
                     else // if (instr16[6:5] == 2'b11) 
                       InstrD = {7'b0000000, rs2p, rds1p, 3'b111, rds1p, 7'b0110011}; // c.and
-                  else if (XLEN > 32) //if (instr16[12:10] == 3'b111) full truth table no need to check [12:10] 
-                    if (instr16[6:5] == 2'b00)
+                  else if (instr16[12:10] == 3'b111) begin
+                    if (instr16[6:5] == 2'b00 & P.XLEN > 32)
                       InstrD = {7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.subw
-                    else if (instr16[6:5] == 2'b01)
+                    else if (instr16[6:5] == 2'b01 & P.XLEN > 32)
                       InstrD = {7'b0000000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.addw
+                    else if (instr16[6:2] == 5'b11000 & P.ZCB_SUPPORTED) 
+                      InstrD = {12'b000011111111, rds1p, 3'b111, rds1p, 7'b0010011}; // c.zext.b = andi rd, rs1, 255
+                    else if (instr16[6:2] == 5'b10101 & P.ZCB_SUPPORTED) 
+                      InstrD = {12'b011000000100, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.b
+                    else if (instr16[6:2] == 5'b11010 & P.ZCB_SUPPORTED) 
+                      InstrD = {7'b0000100, 5'b00000, rds1p, 3'b100, rds1p, 3'b011, P.XLEN > 32, 3'b011};  // c.zext.h
+                    else if (instr16[6:2] == 5'b11011 & P.ZCB_SUPPORTED) 
+                      InstrD = {12'b011000000101, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.h
+                    else if (instr16[6:2] == 5'b11101 & P.ZCB_SUPPORTED) 
+                      InstrD = {12'b111111111111, rds1p, 3'b100, rds1p, 7'b0010011}; // c.not = xori
+                    else if (instr16[6:2] == 5'b11100 & P.ZCB_SUPPORTED & P.XLEN > 32) 
+                      InstrD = {7'b0000100, 5'b00000, rds1p, 3'b000, rds1p, 7'b0111011}; // c.zext.w = add.uw rd, rs1, 0
+                    else if (instr16[6:5] == 2'b10 & P.ZCB_SUPPORTED) 
+                      InstrD = {7'b0000001, rs2p, rds1p, 3'b000, rds1p, 7'b0110011}; // c.mul
                     else begin // reserved  
                       IllegalCompInstrD = 1;
                       InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
                     end
-                  // coverage off
-                  // are excluding this branch from coverage because in rv64gc XLEN is always 64 and thus greater than 32 bits
-                  // This branch will only be taken if instr16[12:10] == 3'b111 and 'XLEN !> 32, because all other 
-                  // possible values for instr16[12:10] are covered by branches above. XLEN !> 32 
-                  // will never occur in rv64gc so this branch can not be covered
-                  else begin // illegal instruction
+                  end else begin // illegal instruction
                     IllegalCompInstrD = 1;
                     InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
                   end
-                  // coverage on
         5'b01101: InstrD = {immCJ, 5'b00000, 7'b1101111}; // c.j
         5'b01110: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b000, immCB[4:0], 7'b1100011}; // c.beqz
         5'b01111: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b001, immCB[4:0], 7'b1100011}; // c.bnez
         5'b10000: InstrD = {6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli
-        5'b10001: InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp
+        5'b10001: if (P.C_SUPPORTED & P.D_SUPPORTED | P.ZCD_SUPPORTED)
+                    InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp
+                  else begin // unsupported instruction
+                    IllegalCompInstrD = 1;
+                    InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
+                  end
         5'b10010: InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp
-        5'b10011: if (XLEN == 32)
-                    InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp
+        5'b10011: if (P.XLEN == 32)
+                    if (P.C_SUPPORTED & P.F_SUPPORTED | P.ZCF_SUPPORTED) 
+                      InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp
+                    else begin
+                      IllegalCompInstrD = 1;
+                      InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
+                    end                    
                   else 
                     InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000011}; // c.ldsp
         5'b10100: if (instr16[12] == 0)
@@ -167,10 +225,20 @@ module decompress #(parameter XLEN)(
                         InstrD = {12'b0, rds1, 3'b000, 5'b00001, 7'b1100111}; // c.jalr
                     else
                       InstrD = {7'b0000000, rs2, rds1, 3'b000, rds1, 7'b0110011}; // c.add
-        5'b10101: InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100111}; // c.fsdsp
+        5'b10101: if (P.C_SUPPORTED & P.D_SUPPORTED | P.ZCD_SUPPORTED)
+                    InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100111}; // c.fsdsp
+                  else begin // unsupported instruction
+                    IllegalCompInstrD = 1;
+                    InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
+                  end
         5'b10110: InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100011}; // c.swsp
-        5'b10111: if (XLEN==32)
-                    InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100111}; // c.fswsp
+        5'b10111: if (P.XLEN==32)
+                    if (P.C_SUPPORTED & P.F_SUPPORTED | P.ZCF_SUPPORTED) 
+                      InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100111}; // c.fswsp
+                    else begin
+                      IllegalCompInstrD = 1;
+                      InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
+                    end                    
                   else
                     InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100011}; // c.sdsp
         default: begin // illegal instruction
diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv
index d63a987b2..af6f70898 100644
--- a/src/ifu/ifu.sv
+++ b/src/ifu/ifu.sv
@@ -353,9 +353,9 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   flopenrc #(P.XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
    
   // expand 16-bit compressed instructions to 32 bits
-  if (P.C_SUPPORTED) begin
+  if (P.C_SUPPORTED | P.ZCA_SUPPORTED) begin
     logic IllegalCompInstrD;
-    decompress #(P.XLEN) decomp(.InstrRawD, .InstrD, .IllegalCompInstrD); 
+    decompress #(P) decomp(.InstrRawD, .InstrD, .IllegalCompInstrD); 
     assign IllegalIEUInstrD = IllegalBaseInstrD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
   end else begin  
     assign InstrD = InstrRawD;
diff --git a/testbench/common/riscvassertions.sv b/testbench/common/riscvassertions.sv
index a6cee910e..815478390 100644
--- a/testbench/common/riscvassertions.sv
+++ b/testbench/common/riscvassertions.sv
@@ -63,6 +63,11 @@ module riscvassertions import cvw::*; #(parameter cvw_t P);
     assert ((P.ZICBOP_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $error("ZICBOP requires DCACHE_SUPPORTED");
     assert ((P.SVPBMT_SUPPORTED == 0) || (P.VIRTMEM_SUPPORTED == 1 && P.XLEN==64)) else $error("SVPBMT requires VIRTMEM_SUPPORTED and RV64");
     assert ((P.SVNAPOT_SUPPORTED == 0) || (P.VIRTMEM_SUPPORTED == 1 && P.XLEN==64)) else $error("SVNAPOT requires VIRTMEM_SUPPORTED and RV64");
+    assert ((P.ZCB_SUPPORTED == 0) || (P.M_SUPPORTED == 1 && (P.ZBA_SUPPORTED == 1 || P.XLEN == 32) && P.ZBB_SUPPORTED == 1)) else $error("ZCB requires M and ZBB (and also ZBA for RV64)");
+    assert ((P.C_SUPPORTED == 0) || (P.ZCA_SUPPORTED == 0 && P.ZCF_SUPPORTED == 0 && P.ZCD_SUPPORTED == 0)) else $error("C and ZCA/ZCD/ZCF cannot simultaneously be supported");
+    assert ((P.ZCA_SUPPORTED == 1) || (P.ZCD_SUPPORTED == 0 && P.ZCF_SUPPORTED == 0)) else $error("ZCF or ZCD requires ZCA");
+    assert ((P.ZCF_SUPPORTED == 0) || (P.F_SUPPORTED == 1)) else $error("ZCF requires F");
+    assert ((P.ZCD_SUPPORTED == 0) || (P.D_SUPPORTED == 1)) else $error("ZCD requires D");   
   end
 
 endmodule

From 81c44a4cb3d9eca3c54b89f3b8d34bd4679724c2 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 4 Oct 2023 17:11:47 -0500
Subject: [PATCH 31/32] Fixed imperas linux testbench.

---
 testbench/common/wallyTracer.sv      |  10 +-
 testbench/testbench-linux-imperas.sv | 137 ++++++++++++++-------------
 2 files changed, 76 insertions(+), 71 deletions(-)

diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv
index 42f55bf09..499233b93 100644
--- a/testbench/common/wallyTracer.sv
+++ b/testbench/common/wallyTracer.sv
@@ -40,7 +40,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   logic                          StallF, StallD;
   logic                          STATUS_SXL, STATUS_UXL;
   logic [P.XLEN-1:0] 			 PCNextF, PCF, PCD, PCE, PCM, PCW;
-  logic [P.XLEN-1:0] 			 InstrRawD, InstrRawE, InstrRawM, InstrRawW;
+  logic [31:0]      			 InstrRawD, InstrRawE, InstrRawM, InstrRawW;
   logic 						 InstrValidM, InstrValidW;
   logic 						 StallE, StallM, StallW;
   logic 						 FlushD, FlushE, FlushM, FlushW;
@@ -259,10 +259,10 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   assign CSRWriteM = testbench.dut.core.priv.priv.csr.CSRWriteM;
   
   // pipeline to writeback stage
-  flopenrc #(P.XLEN) InstrRawEReg (clk, reset, FlushE, ~StallE, InstrRawD, InstrRawE);
-  flopenrc #(P.XLEN) InstrRawMReg (clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM);
-  flopenrc #(P.XLEN) InstrRawWReg (clk, reset, FlushW, ~StallW, InstrRawM, InstrRawW);
-  flopenrc #(P.XLEN) PCWReg (clk, reset, FlushW, ~StallW, PCM, PCW);
+  flopenrc #(32)    InstrRawEReg (clk, reset, FlushE, ~StallE, InstrRawD, InstrRawE);
+  flopenrc #(32)    InstrRawMReg (clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM);
+  flopenrc #(32)    InstrRawWReg (clk, reset, FlushW, ~StallW, InstrRawM, InstrRawW);
+  flopenrc #(32)    PCWReg (clk, reset, FlushW, ~StallW, PCM, PCW);
   flopenrc #(1)     InstrValidMReg (clk, reset, FlushW, ~StallW, InstrValidM, InstrValidW);
   flopenrc #(1)     TrapWReg (clk, reset, 1'b0, ~StallW, TrapM, TrapW);
   flopenrc #(1)     HaltWReg (clk, reset, 1'b0, ~StallW, HaltM, HaltW);
diff --git a/testbench/testbench-linux-imperas.sv b/testbench/testbench-linux-imperas.sv
index 79b354cb0..cca3dd5e5 100644
--- a/testbench/testbench-linux-imperas.sv
+++ b/testbench/testbench-linux-imperas.sv
@@ -24,7 +24,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
+`include "config.vh"
+`include "BranchPredictorType.vh"
 
 // This is set from the command line script
 // `define USE_IMPERAS_DV
@@ -33,6 +34,8 @@
     `include "idv/idv.svh"
 `endif
 
+import cvw::*;
+
 `define DEBUG_TRACE 0
 // Debug Levels
 // 0: don't check against QEMU
@@ -61,8 +64,7 @@ module testbench;
   `endif
 
 
-
-
+  `include "parameter-defs.vh"
 
 
 
@@ -96,40 +98,40 @@ module testbench;
       integer TokenIndex``STAGE; \
       integer MarkerIndex``STAGE; \
       integer NumCSR``STAGE; \
-      logic [`XLEN-1:0] ExpectedPC``STAGE; \
+      logic [P.XLEN-1:0] ExpectedPC``STAGE; \
       logic [31:0]      ExpectedInstr``STAGE; \
       string            text``STAGE; \
       string            MemOp``STAGE; \
       string            RegWrite``STAGE; \
       integer           ExpectedRegAdr``STAGE; \
-      logic [`XLEN-1:0] ExpectedRegValue``STAGE; \
-      logic [`XLEN-1:0] ExpectedIEUAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \
+      logic [P.XLEN-1:0] ExpectedRegValue``STAGE; \
+      logic [P.XLEN-1:0] ExpectedIEUAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \
       string            ExpectedCSRArray``STAGE[10:0]; \
-      logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0]; // *** might be redundant?
+      logic [P.XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0]; // *** might be redundant?
   `DECLARE_TRACE_SCANNER_SIGNALS(E)
   `DECLARE_TRACE_SCANNER_SIGNALS(M)
   //  M-stage expected values
   logic             checkInstrM;
   integer           MIPexpected, SIPexpected;
   string            name;
-  logic [`AHBW-1:0] readDataExpected;
+  logic [P.AHBW-1:0] readDataExpected;
   // W-stage expected values
   logic             checkInstrW;
-  logic [`XLEN-1:0] ExpectedPCW;
+  logic [P.XLEN-1:0] ExpectedPCW;
   logic [31:0]      ExpectedInstrW;
   string            textW;
   string            RegWriteW;
   integer           ExpectedRegAdrW;
-  logic [`XLEN-1:0] ExpectedRegValueW;
+  logic [P.XLEN-1:0] ExpectedRegValueW;
   string            MemOpW;
-  logic [`XLEN-1:0] ExpectedIEUAdrW, ExpectedMemReadDataW, ExpectedMemWriteDataW;
+  logic [P.XLEN-1:0] ExpectedIEUAdrW, ExpectedMemReadDataW, ExpectedMemWriteDataW;
   integer           NumCSRW;
   string            ExpectedCSRArrayW[10:0];
-  logic [`XLEN-1:0] ExpectedCSRArrayValueW[10:0];
-  logic [`XLEN-1:0] ExpectedIntType;
+  logic [P.XLEN-1:0] ExpectedCSRArrayValueW[10:0];
+  logic [P.XLEN-1:0] ExpectedIntType;
   integer           NumCSRWIndex;
   integer           NumCSRPostWIndex;
-  logic [`XLEN-1:0] InstrCountW;
+  logic [P.XLEN-1:0] InstrCountW;
   // ========== Interrupt parsing & spoofing ==========
   string  interrupt;
   string  interruptLine;
@@ -143,7 +145,7 @@ module testbench;
   string  interruptDesc;
   integer           NextMIPexpected, NextSIPexpected;
   integer           NextMepcExpected;
-  logic [`XLEN-1:0] AttemptedInstructionCount;
+  logic [P.XLEN-1:0] AttemptedInstructionCount;
   // ========== Misc Aliases ==========
   `define RF dut.core.ieu.dp.regf.rf
   `define PC dut.core.ifu.pcreg.q
@@ -168,7 +170,7 @@ module testbench;
   `define SSCRATCH    `CSR_BASE.csrs.csrs.SSCRATCHreg.q
   `define MTVEC       `CSR_BASE.csrm.MTVECreg.q
   `define STVEC       `CSR_BASE.csrs.csrs.STVECreg.q
-  `define SATP        `CSR_BASE.csrs.csrs.genblk1.SATPreg.q
+  `define SATP        `CSR_BASE.csrs.csrs.genblk2.SATPreg.q
   `define INSTRET     `CSR_BASE.counters.counters.HPMCOUNTER_REGW[2]
   `define MSTATUS     `CSR_BASE.csrsr.MSTATUS_REGW
   `define SSTATUS     `CSR_BASE.csrsr.SSTATUS_REGW  
@@ -249,14 +251,14 @@ module testbench;
   initial begin reset_ext <= 1; # 22; reset_ext <= 0; end
   always begin clk <= 1; # 5; clk <= 0; # 5; end
   // Wally Interface
-  logic [`AHBW-1:0] HRDATAEXT;
+  logic [P.AHBW-1:0] HRDATAEXT;
   logic             HREADYEXT, HRESPEXT;
   logic             HCLK, HRESETn;
   logic             HREADY;
   logic 	    HSELEXT;
-  logic [`PA_BITS-1:0] HADDR;
-  logic [`AHBW-1:0] HWDATA;
-  logic [`XLEN/8-1:0] HWSTRB;
+  logic [P.PA_BITS-1:0] HADDR;
+  logic [P.AHBW-1:0] HWDATA;
+  logic [P.XLEN/8-1:0] HWSTRB;
   logic             HWRITE;
   logic [2:0]       HSIZE;
   logic [2:0]       HBURST;
@@ -273,10 +275,13 @@ module testbench;
   logic SDCCmdOut;
   logic SDCCmdOE;
   logic [3:0] SDCDatIn;
+  logic       SDCIntr;
+  
 
   // Hardwire UART, GPIO pins
-  assign GPIOPinsIn = 0;
+  assign GPIOIN = 0;
   assign UARTSin = 1;
+  assign SDCIntr = 0;
 
   
   
@@ -284,8 +289,8 @@ module testbench;
 
       logic         DCacheFlushDone, DCacheFlushStart;
 
-      rvviTrace #(.XLEN(`XLEN), .FLEN(`FLEN)) rvvi();
-      wallyTracer wallyTracer(rvvi);
+      rvviTrace #(.XLEN(P.XLEN), .FLEN(P.FLEN)) rvvi();
+      wallyTracer #(P) wallyTracer(rvvi);
 
       trace2log idv_trace2log(rvvi);
 //      trace2cov idv_trace2cov(rvvi);
@@ -344,23 +349,23 @@ module testbench;
         // Privileges for PMA are set in the imperas.ic
         // volatile (IO) regions are defined here
         // only real ROM/RAM areas are BOOTROM and UNCORE_RAM
-        if (`CLINT_SUPPORTED) begin
-            void'(rvviRefMemorySetVolatile(`CLINT_BASE, (`CLINT_BASE + `CLINT_RANGE)));
+        if (P.CLINT_SUPPORTED) begin
+            void'(rvviRefMemorySetVolatile(P.CLINT_BASE, (P.CLINT_BASE + P.CLINT_RANGE)));
         end
-        if (`GPIO_SUPPORTED) begin
-            void'(rvviRefMemorySetVolatile(`GPIO_BASE, (`GPIO_BASE + `GPIO_RANGE)));
+        if (P.GPIO_SUPPORTED) begin
+            void'(rvviRefMemorySetVolatile(P.GPIO_BASE, (P.GPIO_BASE + P.GPIO_RANGE)));
         end
-        if (`UART_SUPPORTED) begin
-            void'(rvviRefMemorySetVolatile(`UART_BASE, (`UART_BASE + `UART_RANGE)));
+        if (P.UART_SUPPORTED) begin
+            void'(rvviRefMemorySetVolatile(P.UART_BASE, (P.UART_BASE + P.UART_RANGE)));
         end
-        if (`PLIC_SUPPORTED) begin
-            void'(rvviRefMemorySetVolatile(`PLIC_BASE, (`PLIC_BASE + `PLIC_RANGE)));
+        if (P.PLIC_SUPPORTED) begin
+            void'(rvviRefMemorySetVolatile(P.PLIC_BASE, (P.PLIC_BASE + P.PLIC_RANGE)));
         end
-        if (`SDC_SUPPORTED) begin
-            void'(rvviRefMemorySetVolatile(`SDC_BASE, (`SDC_BASE + `SDC_RANGE)));
+        if (P.SDC_SUPPORTED) begin
+            void'(rvviRefMemorySetVolatile(P.SDC_BASE, (P.SDC_BASE + P.SDC_RANGE)));
         end
 
-        if(`XLEN==32) begin
+        if(P.XLEN==32) begin
             void'(rvviRefCsrSetVolatile(0, 32'hC80));   // CYCLEH
             void'(rvviRefCsrSetVolatile(0, 32'hB80));   // MCYCLEH
             void'(rvviRefCsrSetVolatile(0, 32'hC82));   // INSTRETH
@@ -427,28 +432,28 @@ module testbench;
   
 
   // Wally
-  wallypipelinedsoc dut(.clk, .reset, .reset_ext,
+  wallypipelinedsoc #(P) dut(.clk, .reset, .reset_ext,
                         .HRDATAEXT, .HREADYEXT, .HREADY, .HSELEXT, .HRESPEXT, .HCLK, 
 			.HRESETn, .HADDR, .HWDATA, .HWRITE, .HWSTRB, .HSIZE, .HBURST, .HPROT, 
 			.HTRANS, .HMASTLOCK, 
 			.TIMECLK('0), .GPIOIN, .GPIOOUT, .GPIOEN,
                         .UARTSin, .UARTSout,
-			.SDCCLK, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn);
+			.SDCIntr);
 
   // W-stage hardware not needed by Wally itself 
   parameter nop = 'h13;
-  logic [`XLEN-1:0] PCW;
+  logic [P.XLEN-1:0] PCW;
   logic [31:0]      InstrW;
   logic             InstrValidW;
-  logic [`XLEN-1:0] IEUAdrW, WriteDataW;
+  logic [P.XLEN-1:0] IEUAdrW, WriteDataW;
   logic             TrapW;
   `define FLUSHW dut.core.FlushW
   `define STALLW dut.core.StallW
-  flopenrc #(`XLEN)         PCWReg(clk, reset, `FLUSHW, ~`STALLW, `PCM, PCW);
+  flopenrc #(P.XLEN)         PCWReg(clk, reset, `FLUSHW, ~`STALLW, `PCM, PCW);
   flopenr #(32)          InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : dut.core.ifu.InstrM, InstrW);
   flopenrc #(1)        controlregW(clk, reset, `FLUSHW, ~`STALLW, dut.core.ieu.c.InstrValidM, InstrValidW);
-  flopenrc #(`XLEN)     IEUAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.IEUAdrM, IEUAdrW);
-  flopenrc #(`XLEN)  WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.lsu.WriteDataM, WriteDataW);  
+  flopenrc #(P.XLEN)     IEUAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.IEUAdrM, IEUAdrW);
+  flopenrc #(P.XLEN)  WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.lsu.WriteDataM, WriteDataW);  
   flopenr #(1)            TrapWReg(clk, reset, ~`STALLW, dut.core.hzu.TrapM, TrapW);
 
 
@@ -524,29 +529,29 @@ module testbench;
     end
 
   genvar i;
-  `INIT_CHECKPOINT_SIMPLE_ARRAY(RF,         [`XLEN-1:0],31,1);
-  `INIT_CHECKPOINT_SIMPLE_ARRAY(HPMCOUNTER, [`XLEN-1:0],`COUNTERS-1,0);
-  `INIT_CHECKPOINT_VAL(PC,         [`XLEN-1:0]);
-  `INIT_CHECKPOINT_VAL(MEDELEG,    [`XLEN-1:0]);
-  `INIT_CHECKPOINT_VAL(MIDELEG,    [`XLEN-1:0]);
+  `INIT_CHECKPOINT_SIMPLE_ARRAY(RF,         [P.XLEN-1:0],31,1);
+  `INIT_CHECKPOINT_SIMPLE_ARRAY(HPMCOUNTER, [P.XLEN-1:0],P.COUNTERS-1,0);
+  `INIT_CHECKPOINT_VAL(PC,         [P.XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(MEDELEG,    [P.XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(MIDELEG,    [P.XLEN-1:0]);
   if(!NO_SPOOFING) begin
     `INIT_CHECKPOINT_VAL(MIE,        [11:0]);
     `INIT_CHECKPOINT_VAL(MIP,        [11:0]);
     end
-  `INIT_CHECKPOINT_VAL(MCAUSE,     [`XLEN-1:0]);
-  `INIT_CHECKPOINT_VAL(SCAUSE,     [`XLEN-1:0]);
-  `INIT_CHECKPOINT_VAL(MEPC,       [`XLEN-1:0]);
-  `INIT_CHECKPOINT_VAL(SEPC,       [`XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(MCAUSE,     [P.XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(SCAUSE,     [P.XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(MEPC,       [P.XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(SEPC,       [P.XLEN-1:0]);
   `INIT_CHECKPOINT_VAL(MCOUNTEREN, [31:0]);
   `INIT_CHECKPOINT_VAL(SCOUNTEREN, [31:0]);
-  `INIT_CHECKPOINT_VAL(MSCRATCH,   [`XLEN-1:0]);
-  `INIT_CHECKPOINT_VAL(SSCRATCH,   [`XLEN-1:0]);
-  `INIT_CHECKPOINT_VAL(MTVEC,      [`XLEN-1:0]);
-  `INIT_CHECKPOINT_VAL(STVEC,      [`XLEN-1:0]);
-  `INIT_CHECKPOINT_VAL(SATP,       [`XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(MSCRATCH,   [P.XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(SSCRATCH,   [P.XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(MTVEC,      [P.XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(STVEC,      [P.XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(SATP,       [P.XLEN-1:0]);
   `INIT_CHECKPOINT_VAL(PRIV,       [1:0]);
-  `INIT_CHECKPOINT_PACKED_ARRAY(PLIC_INT_PRIORITY, [2:0],`PLIC_NUM_SRC,1);
-  `MAKE_CHECKPOINT_INIT_SIGNAL(PLIC_INT_ENABLE, [`PLIC_NUM_SRC:0],1,0);
+  `INIT_CHECKPOINT_PACKED_ARRAY(PLIC_INT_PRIORITY, [2:0],P.PLIC_NUM_SRC,1);
+  `MAKE_CHECKPOINT_INIT_SIGNAL(PLIC_INT_ENABLE, [P.PLIC_NUM_SRC:0],1,0);
   `INIT_CHECKPOINT_PACKED_ARRAY(PLIC_THRESHOLD, [2:0],1,0);
   // UART checkpointing does not cover entire UART state
   //     Many UART registers are difficult to initialize because under the hood
@@ -561,8 +566,8 @@ module testbench;
   `INIT_CHECKPOINT_VAL(UART_SCR,   [7:0]);
   // xSTATUS need to be handled manually because the most upstream signals
   // are made of individual bits, not registers
-  `MAKE_CHECKPOINT_INIT_SIGNAL(MSTATUS, [`XLEN-1:0],0,0);
-  `MAKE_CHECKPOINT_INIT_SIGNAL(SSTATUS, [`XLEN-1:0],0,0);  
+  `MAKE_CHECKPOINT_INIT_SIGNAL(MSTATUS, [P.XLEN-1:0],0,0);
+  `MAKE_CHECKPOINT_INIT_SIGNAL(SSTATUS, [P.XLEN-1:0],0,0);  
 
   // ========== INITIALIZATION ==========
   initial begin
@@ -618,7 +623,7 @@ module testbench;
       force {`STATUS_SPIE} = initMSTATUS[0][5];
       force {`STATUS_MIE} = initMSTATUS[0][3];
       force {`STATUS_SIE} = initMSTATUS[0][1];
-      force `PLIC_INT_ENABLE = {initPLIC_INT_ENABLE[1][`PLIC_NUM_SRC:1],initPLIC_INT_ENABLE[0][`PLIC_NUM_SRC:1]}; // would need to expand into a generate loop to cover an arbitrary number of contexts
+      force `PLIC_INT_ENABLE = {initPLIC_INT_ENABLE[1][P.PLIC_NUM_SRC:1],initPLIC_INT_ENABLE[0][P.PLIC_NUM_SRC:1]}; // would need to expand into a generate loop to cover an arbitrary number of contexts
       force `INSTRET = CHECKPOINT;
       while (reset!==1) #1;
       while (reset!==0) #1;
@@ -871,7 +876,7 @@ module testbench;
             "scause":  `checkCSR(`CSR_BASE.csrs.csrs.SCAUSE_REGW)
             "stvec":   `checkCSR(`CSR_BASE.csrs.csrs.STVEC_REGW)
             "stval":   `checkCSR(`CSR_BASE.csrs.csrs.STVAL_REGW)
-            "senvcfg": `checkCSR(`CSR_BASE.csrs.SENVCFG_REGW)
+            // "senvcfg": `checkCSR(`CSR_BASE.csrs.SENVCFG_REGW) // *** fix me
             "mip": begin
                        `checkCSR(`CSR_BASE.csrm.MIP_REGW)
                        if(!NO_SPOOFING) begin
@@ -951,7 +956,7 @@ module testbench;
   //////////////////////////////// Extra Features ///////////////////////////////
   ///////////////////////////////////////////////////////////////////////////////
   // Function Tracking
-  FunctionName FunctionName(.reset(reset),
+  FunctionName #(P) FunctionName(.reset(reset),
                             .clk(clk),
                             .ProgramAddrMapFile(ProgramAddrMapFile),
                             .ProgramLabelMapFile(ProgramLabelMapFile));
@@ -976,12 +981,12 @@ module testbench;
    * explanation of the below algorithm.
    */
   logic             SvMode, PTE_R, PTE_X;
-  logic [`XLEN-1:0] SATP, PTE;
+  logic [P.XLEN-1:0] SATP, PTE;
   logic [55:0]      BaseAdr, PAdr;
   logic [8:0]       VPN [2:0];
   logic [11:0]      Offset;
-  function logic [`XLEN-1:0] adrTranslator( 
-    input logic [`XLEN-1:0] adrIn);
+  function logic [P.XLEN-1:0] adrTranslator( 
+    input logic [P.XLEN-1:0] adrIn);
     begin
       int i;
       // Grab the SATP register from privileged unit
@@ -995,7 +1000,7 @@ module testbench;
       SvMode = SATP[63];
       // Only perform translation if translation is on and the processor is not
       // in machine mode
-      if (SvMode & (dut.core.priv.priv.PrivilegeModeW != `M_MODE)) begin
+      if (SvMode & (dut.core.priv.priv.PrivilegeModeW != P.M_MODE)) begin
         BaseAdr = SATP[43:0] << 12;
         for (i = 2; i >= 0; i--) begin
           PAdr = BaseAdr + (VPN[i] << 3);

From fc83f33615f5c75336f9c927d2486db53d38a20d Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Thu, 5 Oct 2023 13:00:46 -0500
Subject: [PATCH 32/32] Oups. When fixing the linux-imperasdv testbench I
 accidentally introduced a bug to the tracer.

---
 testbench/common/wallyTracer.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv
index 499233b93..d79c7c6cb 100644
--- a/testbench/common/wallyTracer.sv
+++ b/testbench/common/wallyTracer.sv
@@ -262,7 +262,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   flopenrc #(32)    InstrRawEReg (clk, reset, FlushE, ~StallE, InstrRawD, InstrRawE);
   flopenrc #(32)    InstrRawMReg (clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM);
   flopenrc #(32)    InstrRawWReg (clk, reset, FlushW, ~StallW, InstrRawM, InstrRawW);
-  flopenrc #(32)    PCWReg (clk, reset, FlushW, ~StallW, PCM, PCW);
+  flopenrc #(P.XLEN)PCWReg       (clk, reset, FlushW, ~StallW, PCM, PCW);
   flopenrc #(1)     InstrValidMReg (clk, reset, FlushW, ~StallW, InstrValidM, InstrValidW);
   flopenrc #(1)     TrapWReg (clk, reset, 1'b0, ~StallW, TrapM, TrapW);
   flopenrc #(1)     HaltWReg (clk, reset, 1'b0, ~StallW, HaltM, HaltW);