diff --git a/src/cache/cache.sv b/src/cache/cache.sv index 4721eb167..ebee8f4f1 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// cache +// cache.sv // // Written: Ross Thompson ross1728@gmail.com // Created: 7 July 2021 @@ -167,22 +167,22 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE // Adjust byte mask from word to cache line onehotdecoder #(LOGCWPL) adrdec(.bin(PAdr[LOGCWPL+LOGLLENBYTES-1:LOGLLENBYTES]), .decoded(MemPAdrDecoded)); for(index = 0; index < 2**LOGCWPL; index++) begin - assign DemuxedByteMask[(index+1)*(WORDLEN/8)-1:index*(WORDLEN/8)] = MemPAdrDecoded[index] ? ByteMask : '0; + assign DemuxedByteMask[(index+1)*(WORDLEN/8)-1:index*(WORDLEN/8)] = MemPAdrDecoded[index] ? ByteMask : '0; end assign FetchBufferByteSel = SetValid & ~SetDirty ? '1 : ~DemuxedByteMask; // If load miss set all muxes to 1. // Merge write data into fetched cache line for store miss for(index = 0; index < LINELEN/8; index++) begin - mux2 #(8) WriteDataMux(.d0(CacheWriteData[(8*index)%WORDLEN+7:(8*index)%WORDLEN]), - .d1(FetchBuffer[8*index+7:8*index]), .s(FetchBufferByteSel[index]), .y(LineWriteData[8*index+7:8*index])); + mux2 #(8) WriteDataMux(.d0(CacheWriteData[(8*index)%WORDLEN+7:(8*index)%WORDLEN]), + .d1(FetchBuffer[8*index+7:8*index]), .s(FetchBufferByteSel[index]), .y(LineWriteData[8*index+7:8*index])); end assign LineByteMask = SetValid ? '1 : SetDirty ? DemuxedByteMask : '0; end else begin:WriteSelLogic - // No need for this mux if the cache does not handle writes. - assign LineWriteData = FetchBuffer; - assign LineByteMask = '1; + // No need for this mux if the cache does not handle writes. + assign LineWriteData = FetchBuffer; + assign LineByteMask = '1; end ///////////////////////////////////////////////////////////////////////////////////////////// // Flush logic @@ -203,8 +203,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE assign FlushWayFlag = FlushWay[NUMWAYS-1]; end // block: flushlogic else begin:flushlogic - assign FlushWayFlag = 0; - assign FlushAdrFlag = 0; + assign FlushWayFlag = 0; + assign FlushAdrFlag = 0; end ///////////////////////////////////////////////////////////////////////////////////////////// diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv index 1e7101365..87d9f072a 100644 --- a/src/cache/cacheLRU.sv +++ b/src/cache/cacheLRU.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// dcache (data cache) +// cacheLRU.sv // // Written: Ross Thompson ross1728@gmail.com // Created: 20 July 2021 @@ -37,7 +37,7 @@ module cacheLRU input logic CacheEn, // Enable the cache memory arrays. Disable hold read data constant input logic [NUMWAYS-1:0] HitWay, // Which way is valid and matches PAdr's tag input logic [NUMWAYS-1:0] ValidWay, // Which ways for a particular set are valid, ignores tag - input logic [SETLEN-1:0] CacheSet, // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr + input logic [SETLEN-1:0] CacheSet, // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr input logic [SETLEN-1:0] PAdr, // Physical address input logic LRUWriteEn, // Update the LRU state input logic SetValid, // Set the dirty bit in the selected way and set diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 2a5cb8235..525d7524f 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -1,11 +1,11 @@ /////////////////////////////////////////// -// dcache (data cache) fsm +// cachefsm.sv // // Written: Ross Thompson ross1728@gmail.com // Created: 25 August 2021 // Modified: 20 January 2023 // -// Purpose: Controller for the dcache fsm +// Purpose: Controller for the cache fsm // // Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.14 and Table 7.1) // diff --git a/src/cache/subcachelineread.sv b/src/cache/subcachelineread.sv index 58d022a71..ea305fb6c 100644 --- a/src/cache/subcachelineread.sv +++ b/src/cache/subcachelineread.sv @@ -1,11 +1,11 @@ /////////////////////////////////////////// -// subcachelineread +// subcachelineread.sv // // Written: Ross Thompson ross1728@gmail.com // Created: 4 February 2022 // Modified: 20 January 2023 // -// Purpose: Muxes the cache line downto the word size. Also include possilbe save/restore registers/muxes. +// Purpose: Muxes the cache line down to the word size. Also include possible save/restore registers/muxes. // // Documentation: RISC-V System on Chip Design Chapter 7 @@ -31,7 +31,6 @@ module subcachelineread #(parameter LINELEN, WORDLEN, parameter MUXINTERVAL )( // The number of bits between mux. Set to 16 for I$ to support compressed. Set to `LLEN for D$ - input logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr, // Physical address input logic [LINELEN-1:0] ReadDataLine,// Read data of the whole cacheline output logic [WORDLEN-1:0] ReadDataWord // read data of selected word. diff --git a/src/ebu/ahbcacheinterface.sv b/src/ebu/ahbcacheinterface.sv index e2e7d3696..38b1e6879 100644 --- a/src/ebu/ahbcacheinterface.sv +++ b/src/ebu/ahbcacheinterface.sv @@ -38,27 +38,27 @@ module ahbcacheinterface #( )( input logic HCLK, HRESETn, // bus interface controls - input logic HREADY, // AHB peripheral ready + input logic HREADY, // AHB peripheral ready output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ output logic HWRITE, // AHB 0: Read operation 1: Write operation output logic [2:0] HSIZE, // AHB transaction width output logic [2:0] HBURST, // AHB burst length // bus interface buses - input logic [`AHBW-1:0] HRDATA, // AHB read data + input logic [`AHBW-1:0] HRDATA, // AHB read data output logic [`PA_BITS-1:0] HADDR, // AHB address output logic [`AHBW-1:0] HWDATA, // AHB write data output logic [`AHBW/8-1:0] HWSTRB, // AHB byte mask // cache interface - input logic [`PA_BITS-1:0] CacheBusAdr, // Address of cache line - input logic [`LLEN-1:0] CacheReadDataWordM, // one word of cache line during a writeback - input logic CacheableOrFlushCacheM, // Memory operation is cacheable or flushing D$ - input logic Cacheable, // Memory operation is cachable - input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch - output logic CacheBusAck, // Handshack to $ indicating bus transaction completed - output logic [LINELEN-1:0] FetchBuffer, // Register to hold beats of cache line as the arrive from bus - output logic [AHBWLOGBWPL-1:0] BeatCount, // Beat position within the cache line in the Address Phase - output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr + input logic [`PA_BITS-1:0] CacheBusAdr, // Address of cache line + input logic [`LLEN-1:0] CacheReadDataWordM, // One word of cache line during a writeback + input logic CacheableOrFlushCacheM, // Memory operation is cacheable or flushing D$ + input logic Cacheable, // Memory operation is cachable + input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch + output logic CacheBusAck, // Handshake to $ indicating bus transaction completed + output logic [LINELEN-1:0] FetchBuffer, // Register to hold beats of cache line as the arrive from bus + output logic [AHBWLOGBWPL-1:0] BeatCount, // Beat position within the cache line in the Address Phase + output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr // uncached interface input logic [`PA_BITS-1:0] PAdr, // Physical address of uncached memory operation @@ -77,7 +77,7 @@ module ahbcacheinterface #( logic [`PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation logic [AHBWLOGBWPL-1:0] BeatCountDelayed; // Beat within the cache line in the second (Data) cache stage logic CaptureEn; // Enable updating the Fetch buffer with valid data from HRDATA - logic [`AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s + logic [`AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s logic [`AHBW-1:0] PreHWDATA; // AHB Address phase write data genvar index; @@ -107,7 +107,7 @@ module ahbcacheinterface #( end else assign CacheReadDataWordAHB = CacheReadDataWordM[`AHBW-1:0]; mux2 #(`AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[`AHBW-1:0]), - .s(~(CacheableOrFlushCacheM)), .y(PreHWDATA)); + .s(~(CacheableOrFlushCacheM)), .y(PreHWDATA)); flopen #(`AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec // *** bummer need a second byte mask for bus as it is AHBW rather than LLEN. @@ -119,5 +119,5 @@ module ahbcacheinterface #( buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE) AHBBuscachefsm( .HCLK, .HRESETn, .Flush, .BusRW, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat, .CacheBusRW, .CacheBusAck, .BeatCount, .BeatCountDelayed, - .HREADY, .HTRANS, .HWRITE, .HBURST); + .HREADY, .HTRANS, .HWRITE, .HBURST); endmodule diff --git a/src/ebu/ahbinterface.sv b/src/ebu/ahbinterface.sv index 579791032..1a9308dd4 100644 --- a/src/ebu/ahbinterface.sv +++ b/src/ebu/ahbinterface.sv @@ -32,21 +32,21 @@ module ahbinterface #( parameter LSU = 0 // 1: LSU bus width is `XLEN, 0: IFU bus width is 32 bits )( - input logic HCLK, HRESETn, + input logic HCLK, HRESETn, // bus interface - input logic HREADY, // AHB peripheral ready + input logic HREADY, // AHB peripheral ready output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ output logic HWRITE, // AHB 0: Read operation 1: Write operation - input logic [`XLEN-1:0] HRDATA, // AHB read data + input logic [`XLEN-1:0] HRDATA, // AHB read data output logic [`XLEN-1:0] HWDATA, // AHB write data output logic [`XLEN/8-1:0] HWSTRB, // AHB byte mask // lsu/ifu interface - input logic Stall, // Core pipeline is stalled - input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting - input logic [1:0] BusRW, // Memory operation read/write control: 10: read, 01: write - input logic [`XLEN/8-1:0] ByteMask, // Bytes enables within a word - input logic [`XLEN-1:0] WriteData, // IEU write data for a store + input logic Stall, // Core pipeline is stalled + input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting + input logic [1:0] BusRW, // Memory operation read/write control: 10: read, 01: write + input logic [`XLEN/8-1:0] ByteMask, // Bytes enables within a word + input logic [`XLEN-1:0] WriteData, // IEU write data for a store output logic BusStall, // Bus is busy with an in flight memory operation output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt output logic [(LSU ? `XLEN : 32)-1:0] FetchBuffer // Register to hold HRDATA after arriving from the bus diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv index e0efcf3a3..7456cac8b 100644 --- a/src/ebu/buscachefsm.sv +++ b/src/ebu/buscachefsm.sv @@ -40,29 +40,29 @@ module buscachefsm #( input logic HRESETn, // IEU interface - input logic Stall, // Core pipeline is stalled - input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting - input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write - output logic BusStall, // Bus is busy with an in flight memory operation - output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt + input logic Stall, // Core pipeline is stalled + input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting + input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write + output logic BusStall, // Bus is busy with an in flight memory operation + output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt // ahb cache interface locals. - output logic CaptureEn, // Enable updating the Fetch buffer with valid data from HRDATA + output logic CaptureEn, // Enable updating the Fetch buffer with valid data from HRDATA // cache interface - input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch - output logic CacheBusAck, // Handshack to $ indicating bus transaction completed + input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch + output logic CacheBusAck, // Handshack to $ indicating bus transaction completed // lsu interface output logic [AHBWLOGBWPL-1:0] BeatCount, // Beat position within the cache line in the Address Phase output logic [AHBWLOGBWPL-1:0] BeatCountDelayed, // Beat within the cache line in the second (Data) cache stage - output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr + output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr // BUS interface - input logic HREADY, // AHB peripheral ready - output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ - output logic HWRITE, // AHB 0: Read operation 1: Write operation - output logic [2:0] HBURST // AHB burst length + input logic HREADY, // AHB peripheral ready + output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ + output logic HWRITE, // AHB 0: Read operation 1: Write operation + output logic [2:0] HBURST // AHB burst length ); typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, MEM3, CACHE_FETCH, CACHE_WRITEBACK} busstatetype; @@ -78,8 +78,8 @@ module buscachefsm #( logic CacheAccess; always_ff @(posedge HCLK) - if (~HRESETn | Flush) CurrState <= #1 ADR_PHASE; - else CurrState <= #1 NextState; + if (~HRESETn | Flush) CurrState <= #1 ADR_PHASE; + else CurrState <= #1 NextState; always_comb begin case(CurrState) diff --git a/src/ebu/controllerinput.sv b/src/ebu/controllerinput.sv index a8c8e8308..6e3c27d3b 100644 --- a/src/ebu/controllerinput.sv +++ b/src/ebu/controllerinput.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// controller input stage +// controllerinput.sv // // Written: Ross Thompson ross1728@gmail.com // Created: August 31, 2022 @@ -36,26 +36,26 @@ module controllerinput #( parameter SAVE_ENABLED = 1 // 1: Save manager inputs if Save = 1, 0: Don't save inputs )( - input logic HCLK, - input logic HRESETn, - input logic Save, // Two or more managers requesting (HTRANS != 00) at the same time. Save the non-granted manager inputs - input logic Restore, // Restore a saved manager inputs when it is finally granted - input logic Disable, // Supress HREADY to the non-granted manager + input logic HCLK, + input logic HRESETn, + input logic Save, // Two or more managers requesting (HTRANS != 00) at the same time. Save the non-granted manager inputs + input logic Restore, // Restore a saved manager inputs when it is finally granted + input logic Disable, // Suppress HREADY to the non-granted manager output logic Request, // This manager is making a request // controller input - input logic [1:0] HTRANSIn, // Manager input. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ - input logic HWRITEIn, // Manager input. AHB 0: Read operation 1: Write operation - input logic [2:0] HSIZEIn, // Manager input. AHB transaction width - input logic [2:0] HBURSTIn, // Manager input. AHB burst length - input logic [`PA_BITS-1:0] HADDRIn, // Manager input. AHB address - output logic HREADYOut, // Indicate to manager the peripherial is not busy and another manager does not have priority + input logic [1:0] HTRANSIn, // Manager input. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ + input logic HWRITEIn, // Manager input. AHB 0: Read operation 1: Write operation + input logic [2:0] HSIZEIn, // Manager input. AHB transaction width + input logic [2:0] HBURSTIn, // Manager input. AHB burst length + input logic [`PA_BITS-1:0] HADDRIn, // Manager input. AHB address + output logic HREADYOut, // Indicate to manager the peripheral is not busy and another manager does not have priority // controller output - output logic [1:0] HTRANSOut, // Aribrated manager transaction. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ - output logic HWRITEOut, // Aribrated manager transaction. AHB 0: Read operation 1: Write operation - output logic [2:0] HSIZEOut, // Aribrated manager transaction. AHB transaction width - output logic [2:0] HBURSTOut, // Aribrated manager transaction. AHB burst length - output logic [`PA_BITS-1:0] HADDROut, // Aribrated manager transaction. AHB address - input logic HREADYIn // Peripherial ready + output logic [1:0] HTRANSOut, // Arbitrated manager transaction. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ + output logic HWRITEOut, // Arbitrated manager transaction. AHB 0: Read operation 1: Write operation + output logic [2:0] HSIZEOut, // Arbitrated manager transaction. AHB transaction width + output logic [2:0] HBURSTOut, // Arbitrated manager transaction. AHB burst length + output logic [`PA_BITS-1:0] HADDROut, // Arbitrated manager transaction. AHB address + input logic HREADYIn // Peripheral ready ); logic HWRITESave; diff --git a/src/ebu/ebufsmarb.sv b/src/ebu/ebufsmarb.sv index ec1a3d674..a61a3961f 100644 --- a/src/ebu/ebufsmarb.sv +++ b/src/ebu/ebufsmarb.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// ebufsmarb +// ebufsmarb.sv // // Written: Ross Thompson ross1728@gmail.com // Created: 23 January 2023 @@ -55,7 +55,7 @@ module ebufsmarb ( logic IFUReqD; // 1 cycle delayed IFU request. Part of arbitration logic FinalBeat, FinalBeatD; // Indicates the last beat of a burst logic BeatCntEn; - logic [3:0] BeatCount; // Position within a burst transfer + logic [3:0] BeatCount; // Position within a burst transfer logic BeatCntReset; logic [3:0] Threshold; // Number of beats derived from HBURST @@ -86,7 +86,7 @@ module ebufsmarb ( // Controller 1 (LSU) // When both the IFU and LSU request at the same time, the FSM will go into the arbitrate state. // Once the LSU request is done the fsm returns to IDLE. To prevent the LSU from regaining - // priority and re issuing the same memroy operation, the delayed IFUReqD squashes the LSU request. + // priority and re-issuing the same memory operation, the delayed IFUReqD squashes the LSU request. // This is necessary because the pipeline is stalled for the entire duration of both transactions, // and the LSU memory request will stil be active. flopr #(1) ifureqreg(HCLK, ~HRESETn, IFUReq, IFUReqD); diff --git a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv index 482fed842..aa8ae051d 100644 --- a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// fdivsqrtpreproc.sv +// fdivsqrtexpcalc.sv // // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu // Modified:13 January 2022 @@ -30,11 +30,11 @@ module fdivsqrtexpcalc( input logic [`FMTBITS-1:0] Fmt, - input logic [`NE-1:0] Xe, Ye, - input logic Sqrt, - input logic XZero, - input logic [`DIVBLEN:0] ell, m, - output logic [`NE+1:0] Qe + input logic [`NE-1:0] Xe, Ye, + input logic Sqrt, + input logic XZero, + input logic [`DIVBLEN:0] ell, m, + output logic [`NE+1:0] Qe ); logic [`NE-2:0] Bias; logic [`NE+1:0] SXExp; @@ -42,28 +42,28 @@ module fdivsqrtexpcalc( logic [`NE+1:0] DExp; if (`FPSIZES == 1) begin - assign Bias = (`NE-1)'(`BIAS); + assign Bias = (`NE-1)'(`BIAS); end else if (`FPSIZES == 2) begin - assign Bias = Fmt ? (`NE-1)'(`BIAS) : (`NE-1)'(`BIAS1); + assign Bias = Fmt ? (`NE-1)'(`BIAS) : (`NE-1)'(`BIAS1); end else if (`FPSIZES == 3) begin - always_comb - case (Fmt) - `FMT: Bias = (`NE-1)'(`BIAS); - `FMT1: Bias = (`NE-1)'(`BIAS1); - `FMT2: Bias = (`NE-1)'(`BIAS2); - default: Bias = 'x; - endcase + always_comb + case (Fmt) + `FMT: Bias = (`NE-1)'(`BIAS); + `FMT1: Bias = (`NE-1)'(`BIAS1); + `FMT2: Bias = (`NE-1)'(`BIAS2); + default: Bias = 'x; + endcase end else if (`FPSIZES == 4) begin - always_comb - case (Fmt) - 2'h3: Bias = (`NE-1)'(`Q_BIAS); - 2'h1: Bias = (`NE-1)'(`D_BIAS); - 2'h0: Bias = (`NE-1)'(`S_BIAS); - 2'h2: Bias = (`NE-1)'(`H_BIAS); - endcase + always_comb + case (Fmt) + 2'h3: Bias = (`NE-1)'(`Q_BIAS); + 2'h1: Bias = (`NE-1)'(`D_BIAS); + 2'h0: Bias = (`NE-1)'(`S_BIAS); + 2'h2: Bias = (`NE-1)'(`H_BIAS); + endcase end assign SXExp = {2'b0, Xe} - {{(`NE+1-`DIVBLEN){1'b0}}, ell} - (`NE+2)'(`BIAS); assign SExp = {SXExp[`NE+1], SXExp[`NE+1:1]} + {2'b0, Bias}; diff --git a/src/fpu/fdivsqrt/fdivsqrtfgen2.sv b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv index 9c13a91da..250fb4fbd 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfgen2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv @@ -29,7 +29,7 @@ `include "wally-config.vh" module fdivsqrtfgen2 ( - input logic up, uz, + input logic up, uz, input logic [`DIVb+3:0] C, U, UM, output logic [`DIVb+3:0] F ); diff --git a/src/fpu/fdivsqrt/fdivsqrtfgen4.sv b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv index 975d58ebd..a07e504f4 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfgen4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv @@ -29,7 +29,7 @@ `include "wally-config.vh" module fdivsqrtfgen4 ( - input logic [3:0] udigit, + input logic [3:0] udigit, input logic [`DIVb+3:0] C, U, UM, output logic [`DIVb+3:0] F ); diff --git a/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/src/fpu/fdivsqrt/fdivsqrtfsm.sv index 4cfede605..559e4b775 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -29,24 +29,24 @@ `include "wally-config.vh" module fdivsqrtfsm( - input logic clk, - input logic reset, + input logic clk, + input logic reset, input logic [`FMTBITS-1:0] FmtE, - input logic XInfE, YInfE, - input logic XZeroE, YZeroE, - input logic XNaNE, YNaNE, - input logic FDivStartE, IDivStartE, - input logic XsE, - input logic SqrtE, - input logic StallM, - input logic FlushE, - input logic WZeroE, - input logic IntDivE, - input logic [`DIVBLEN:0] nE, - input logic ISpecialCaseE, - output logic IFDivStartE, - output logic FDivBusyE, FDivDoneE, - output logic SpecialCaseM + input logic XInfE, YInfE, + input logic XZeroE, YZeroE, + input logic XNaNE, YNaNE, + input logic FDivStartE, IDivStartE, + input logic XsE, + input logic SqrtE, + input logic StallM, + input logic FlushE, + input logic WZeroE, + input logic IntDivE, + input logic [`DIVBLEN:0] nE, + input logic ISpecialCaseE, + output logic IFDivStartE, + output logic FDivBusyE, FDivDoneE, + output logic SpecialCaseM ); typedef enum logic [1:0] {IDLE, BUSY, DONE} statetype; diff --git a/src/fpu/fdivsqrt/fdivsqrtiter.sv b/src/fpu/fdivsqrt/fdivsqrtiter.sv index 7de120eda..ec15423e4 100644 --- a/src/fpu/fdivsqrt/fdivsqrtiter.sv +++ b/src/fpu/fdivsqrt/fdivsqrtiter.sv @@ -29,10 +29,10 @@ `include "wally-config.vh" module fdivsqrtiter( - input logic clk, - input logic IFDivStartE, - input logic FDivBusyE, - input logic SqrtE, + input logic clk, + input logic IFDivStartE, + input logic FDivBusyE, + input logic SqrtE, input logic [`DIVb+3:0] X, input logic [`DIVb-1:0] DPreproc, output logic [`DIVb-1:0] D, diff --git a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index 7b92f8c83..b8575f7fe 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -112,7 +112,7 @@ module fdivsqrtpostproc( // Select quotient or remainder and do normalization shift mux2 #(`DIVBLEN+1) normshiftmux(((`DIVBLEN+1)'(`DIVb) - (nM * (`DIVBLEN+1)'(`LOGR))), (mM + (`DIVBLEN+1)'(`DIVa)), RemOpM, NormShiftM); - mux2 #(`DIVb+4) presresultmux(NormQuotM, NormRemM, RemOpM, PreResultM); + mux2 #(`DIVb+4) presresultmux(NormQuotM, NormRemM, RemOpM, PreResultM); assign PreIntResultM = $signed(PreResultM >>> NormShiftM); // special case logic diff --git a/src/fpu/fdivsqrt/fdivsqrtqsel2.sv b/src/fpu/fdivsqrt/fdivsqrtqsel2.sv index fd0a2a469..18c577b97 100644 --- a/src/fpu/fdivsqrt/fdivsqrtqsel2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtqsel2.sv @@ -30,7 +30,7 @@ module fdivsqrtqsel2 ( input logic [3:0] ps, pc, - output logic up, uz, un + output logic up, uz, un ); logic [3:0] p, g; diff --git a/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/src/fpu/fdivsqrt/fdivsqrtstage4.sv index ee92d263b..f2ff3734b 100644 --- a/src/fpu/fdivsqrt/fdivsqrtstage4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtstage4.sv @@ -31,7 +31,7 @@ module fdivsqrtstage4 ( input logic [`DIVb-1:0] D, input logic [`DIVb+3:0] DBar, D2, DBar2, - input logic [`DIVb:0] U,UM, + input logic [`DIVb:0] U,UM, input logic [`DIVb+3:0] WS, WC, input logic [`DIVb+1:0] C, input logic SqrtE, j1, @@ -58,8 +58,8 @@ module fdivsqrtstage4 ( // 0000 = 0 // 0010 = -1 // 0001 = -2 - assign Smsbs = U[`DIVb:`DIVb-4]; - assign Dmsbs = D[`DIVb-1:`DIVb-3]; + assign Smsbs = U[`DIVb:`DIVb-4]; + assign Dmsbs = D[`DIVb-1:`DIVb-3]; assign WCmsbs = WC[`DIVb+3:`DIVb-4]; assign WSmsbs = WS[`DIVb+3:`DIVb-4]; diff --git a/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv index 65b8940ac..33956a0fd 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv @@ -32,10 +32,10 @@ // Unified OTFC, Radix 2 // /////////////////////////////// module fdivsqrtuotfc2( - input logic up, un, + input logic up, un, input logic [`DIVb+1:0] C, - input logic [`DIVb:0] U, UM, - output logic [`DIVb:0] UNext, UMNext + input logic [`DIVb:0] U, UM, + output logic [`DIVb:0] UNext, UMNext ); // The on-the-fly converter transfers the divsqrt // bits to the quotient as they come. diff --git a/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv index a1416384b..57298b4c8 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv @@ -29,7 +29,7 @@ `include "wally-config.vh" module fdivsqrtuotfc4( - input logic [3:0] udigit, + input logic [3:0] udigit, input logic [`DIVb:0] U, UM, input logic [`DIVb:0] C, output logic [`DIVb:0] UNext, UMNext diff --git a/src/generic/lzc.sv b/src/generic/lzc.sv index 9b7c841b2..aa5381a22 100644 --- a/src/generic/lzc.sv +++ b/src/generic/lzc.sv @@ -24,7 +24,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module lzc #(parameter WIDTH = 1) ( - input logic [WIDTH-1:0] num, // number to count the leading zeroes of + input logic [WIDTH-1:0] num, // number to count the leading zeroes of output logic [$clog2(WIDTH+1)-1:0] ZeroCnt // the number of leading zeroes ); diff --git a/src/generic/onehotdecoder.sv b/src/generic/onehotdecoder.sv index 6334e91f8..5e8f01c26 100644 --- a/src/generic/onehotdecoder.sv +++ b/src/generic/onehotdecoder.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// oneHotDecoder.sv +// onehotdecoder.sv // // Written: ross1728@gmail.com July 09, 2021 // Modified: diff --git a/src/hazard/hazard.sv b/src/hazard/hazard.sv index 224ff8b37..51f2ccf40 100644 --- a/src/hazard/hazard.sv +++ b/src/hazard/hazard.sv @@ -30,13 +30,13 @@ module hazard ( // Detect hazards - input logic BPWrongE, CSRWriteFenceM, RetM, TrapM, - input logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD, - input logic LSUStallM, IFUStallF, - input logic FCvtIntStallD, FPUStallD, - input logic DivBusyE, FDivBusyE, - input logic EcallFaultM, BreakpointFaultM, - input logic wfiM, IntPendingM, + input logic BPWrongE, CSRWriteFenceM, RetM, TrapM, + input logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD, + input logic LSUStallM, IFUStallF, + input logic FCvtIntStallD, FPUStallD, + input logic DivBusyE, FDivBusyE, + input logic EcallFaultM, BreakpointFaultM, + input logic wfiM, IntPendingM, // Stall & flush outputs output logic StallF, StallD, StallE, StallM, StallW, output logic FlushD, FlushE, FlushM, FlushW diff --git a/src/ieu/bmu/byte.sv b/src/ieu/bmu/byte.sv index db7a3b45c..32031059a 100644 --- a/src/ieu/bmu/byte.sv +++ b/src/ieu/bmu/byte.sv @@ -31,7 +31,7 @@ module byteUnit #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, // Operands - input logic ByteSelect, // LSB of Immediate + input logic ByteSelect, // LSB of Immediate output logic [WIDTH-1:0] ByteResult); // rev8, orcb result logic [WIDTH-1:0] OrcBResult, Rev8Result; diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index 75ace3ac7..a1f82eb7e 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -32,8 +32,8 @@ module cnt #(parameter WIDTH = 32) ( input logic [WIDTH-1:0] A, RevA, // Operands - input logic [1:0] B, // Last 2 bits of immediate - input logic W64, // Indicates word operation + input logic [1:0] B, // Last 2 bits of immediate + input logic W64, // Indicates word operation output logic [WIDTH-1:0] CntResult // count result ); diff --git a/src/ieu/bmu/ext.sv b/src/ieu/bmu/ext.sv index 12e690436..438addaa8 100644 --- a/src/ieu/bmu/ext.sv +++ b/src/ieu/bmu/ext.sv @@ -32,7 +32,7 @@ module ext #(parameter WIDTH = 32) ( input logic [WIDTH-1:0] A, // Operands - input logic [1:0] ExtSelect, // B[2], B[0] of immediate + input logic [1:0] ExtSelect, // B[2], B[0] of immediate output logic [WIDTH-1:0] ExtResult); // Extend Result logic [WIDTH-1:0] sexthResult, zexthResult, sextbResult; diff --git a/src/ieu/bmu/popcnt.sv b/src/ieu/bmu/popcnt.sv index 8732f29f2..7701c0d65 100644 --- a/src/ieu/bmu/popcnt.sv +++ b/src/ieu/bmu/popcnt.sv @@ -27,7 +27,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module popcnt #(parameter WIDTH = 32) ( - input logic [WIDTH-1:0] num, // number to count total ones + input logic [WIDTH-1:0] num, // number to count total ones output logic [$clog2(WIDTH):0] PopCnt // the total number of ones ); diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index d5b3e8f40..02fa1dd7c 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -29,7 +29,7 @@ `include "wally-config.vh" module ieu ( - input logic clk, reset, + input logic clk, reset, // Decode stage signals input logic [31:0] InstrD, // Instruction input logic IllegalIEUFPUInstrD, // Illegal instruction diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv index 5227ee3bd..11ae1cf0a 100644 --- a/src/ieu/shifter.sv +++ b/src/ieu/shifter.sv @@ -35,9 +35,9 @@ module shifter ( input logic Right, Rotate, W64, SubArith, // Shift right, rotate, W64-type operation, arithmetic shift output logic [`XLEN-1:0] Y); // Shifted result - logic [2*`XLEN-2:0] Z, ZShift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits - logic [`LOG_XLEN-1:0] TruncAmt, Offset; // Shift amount adjusted for RV64, right-shift amount - logic Sign; // Sign bit for sign extension + logic [2*`XLEN-2:0] Z, ZShift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits + logic [`LOG_XLEN-1:0] TruncAmt, Offset; // Shift amount adjusted for RV64, right-shift amount + logic Sign; // Sign bit for sign extension assign Sign = A[`XLEN-1] & SubArith; // sign bit for sign extension if (`XLEN==32) begin // rv32 diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index e74d19870..881150b3f 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -48,25 +48,25 @@ module bpred ( input logic [`XLEN-1:0] PCE, // Execution stage instruction address input logic [`XLEN-1:0] PCM, // Memory stage instruction address - input logic [31:0] PostSpillInstrRawF, // Instruction + input logic [31:0] PostSpillInstrRawF, // Instruction // Branch and jump outcome - input logic InstrValidD, InstrValidE, + input logic InstrValidD, InstrValidE, input logic BranchD, BranchE, input logic JumpD, JumpE, - input logic PCSrcE, // Executation stage branch is taken - input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address - input logic [`XLEN-1:0] IEUAdrM, // The branch/jump target address - input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address) + input logic PCSrcE, // Executation stage branch is taken + input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address + input logic [`XLEN-1:0] IEUAdrM, // The branch/jump target address + input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address) output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as call, return, jr (not return), j, br // Report branch prediction status - output logic BPWrongE, // Prediction is wrong - output logic BPWrongM, // Prediction is wrong + output logic BPWrongE, // Prediction is wrong + output logic BPWrongM, // Prediction is wrong output logic BPDirPredWrongM, // Prediction direction is wrong - output logic BTAWrongM, // Prediction target wrong + output logic BTAWrongM, // Prediction target wrong output logic RASPredPCWrongM, // RAS prediction is wrong - output logic IClassWrongM // Class prediction is wrong + output logic IClassWrongM // Class prediction is wrong ); logic [1:0] BPDirPredF; @@ -187,7 +187,7 @@ module bpred ( // Correct branch/jump target. mux2 #(`XLEN) pccorrectemux(PCLinkE, IEUAdrE, PCSrcE, PCCorrectE); - // If the fence/csrw was predicted as a taken branch then we select PCF, rather PCE. + // If the fence/csrw was predicted as a taken branch then we select PCF, rather than PCE. // Effectively this is PCM+4 or the non-existant PCLinkM if(`INSTR_CLASS_PRED) mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPWrongM, NextValidPCE); else assign NextValidPCE = PCE; @@ -201,11 +201,11 @@ module bpred ( // 3. target ras (ras target wrong / class[2]) // 4. direction (br dir wrong / class[0]) - // Unforuantely we can't use PCD to infer the correctness of the BTB or RAS because the class prediction + // Unfortunately we can't use PCD to infer the correctness of the BTB or RAS because the class prediction // could be wrong or the fall through address selected for branch predict not taken. // By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of // both without the above inaccuracies. - // **** use BPBTAWrongM from BTB. + // **** use BPBTAWrongM from BTB. assign BTAWrongE = (BPBTAE != IEUAdrE) & (BranchE | JumpE & ~ReturnE) & PCSrcE; assign RASPredPCWrongE = (RASPCE != IEUAdrE) & ReturnE & PCSrcE; diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv index 90246e0ea..2689b4128 100644 --- a/src/ifu/bpred/btb.sv +++ b/src/ifu/bpred/btb.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // btb.sv // -// Written: Ross Thomposn ross1728@gmail.com +// Written: Ross Thompson ross1728@gmail.com // Created: February 15, 2021 // Modified: 24 January 2023 // @@ -34,19 +34,19 @@ module btb #(parameter Depth = 10 ) ( input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, FlushD, FlushE, FlushM, FlushW, - input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,// PC at various stages - output logic [`XLEN-1:0] BPBTAF, // BTB's guess at PC + input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, // PC at various stages + output logic [`XLEN-1:0] BPBTAF, // BTB's guess at PC output logic [`XLEN-1:0] BPBTAD, output logic [`XLEN-1:0] BPBTAE, - output logic [3:0] BTBIClassF, // BTB's guess at instruction class + output logic [3:0] BTBIClassF, // BTB's guess at instruction class // update - input logic IClassWrongM, // BTB's instruction class guess was wrong + input logic IClassWrongM, // BTB's instruction class guess was wrong input logic IClassWrongE, - input logic [`XLEN-1:0] IEUAdrE, // Branch/jump target address to insert into btb - input logic [`XLEN-1:0] IEUAdrM, // Branch/jump target address to insert into btb - input logic [3:0] InstrClassD, // Instruction class to insert into btb - input logic [3:0] InstrClassE, // Instruction class to insert into btb - input logic [3:0] InstrClassM, // Instruction class to insert into btb + input logic [`XLEN-1:0] IEUAdrE, // Branch/jump target address to insert into btb + input logic [`XLEN-1:0] IEUAdrM, // Branch/jump target address to insert into btb + input logic [3:0] InstrClassD, // Instruction class to insert into btb + input logic [3:0] InstrClassE, // Instruction class to insert into btb + input logic [3:0] InstrClassM, // Instruction class to insert into btb input logic [3:0] InstrClassW ); @@ -73,7 +73,7 @@ module btb #(parameter Depth = 10 ) ( // must output a valid PC and valid bit during reset. Because only PCF, not PCNextF is reset, PCNextF is invalid // during reset. The BTB must produce a non X PC1NextF to allow the simulation to run. - // While thie mux could be included in IFU it is not necessary for the IROM/I$/bus. + // While the mux could be included in IFU it is not necessary for the IROM/I$/bus. // For now it is optimal to leave it here. assign ResetPC = `RESET_VECTOR; assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; diff --git a/testbench/testbench.sv b/testbench/testbench.sv index b3c0efeab..9021b6448 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -52,29 +52,29 @@ module testbench; string tests[]; logic [3:0] dummy; - logic [`AHBW-1:0] HRDATAEXT; - logic HREADYEXT, HRESPEXT; + logic [`AHBW-1:0] HRDATAEXT; + logic HREADYEXT, HRESPEXT; logic [`PA_BITS-1:0] HADDR; - logic [`AHBW-1:0] HWDATA; - logic [`XLEN/8-1:0] HWSTRB; - logic HWRITE; - logic [2:0] HSIZE; - logic [2:0] HBURST; - logic [3:0] HPROT; - logic [1:0] HTRANS; - logic HMASTLOCK; - logic HCLK, HRESETn; - logic [`XLEN-1:0] PCW; + logic [`AHBW-1:0] HWDATA; + logic [`XLEN/8-1:0] HWSTRB; + logic HWRITE; + logic [2:0] HSIZE; + logic [2:0] HBURST; + logic [3:0] HPROT; + logic [1:0] HTRANS; + logic HMASTLOCK; + logic HCLK, HRESETn; + logic [`XLEN-1:0] PCW; - string ProgramAddrMapFile, ProgramLabelMapFile; - integer ProgramAddrLabelArray [string] = '{ "begin_signature" : 0, "tohost" : 0 }; + string ProgramAddrMapFile, ProgramLabelMapFile; + integer ProgramAddrLabelArray [string] = '{ "begin_signature" : 0, "tohost" : 0 }; - logic DCacheFlushDone, DCacheFlushStart; + logic DCacheFlushDone, DCacheFlushStart; logic riscofTest; logic StartSample, EndSample; flopenr #(`XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW); - flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.InstrM, InstrW); + flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.InstrM, InstrW); // check assertions for a legal configuration riscvassertions riscvassertions(); @@ -85,62 +85,62 @@ module testbench; //tests = '{}; if (`XLEN == 64) begin // RV64 case (TEST) - "arch64i": tests = arch64i; - "arch64priv": tests = arch64priv; + "arch64i": tests = arch64i; + "arch64priv": tests = arch64priv; "arch64c": if (`C_SUPPORTED) - if (`ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv}; - else tests = {arch64c}; - "arch64m": if (`M_SUPPORTED) tests = arch64m; - "arch64f": if (`F_SUPPORTED) tests = arch64f; - "arch64d": if (`D_SUPPORTED) tests = arch64d; + if (`ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv}; + else tests = {arch64c}; + "arch64m": if (`M_SUPPORTED) tests = arch64m; + "arch64f": if (`F_SUPPORTED) tests = arch64f; + "arch64d": if (`D_SUPPORTED) tests = arch64d; "arch64zi": if (`ZIFENCEI_SUPPORTED) tests = arch64zi; - "imperas64i": tests = imperas64i; - "imperas64f": if (`F_SUPPORTED) tests = imperas64f; - "imperas64d": if (`D_SUPPORTED) tests = imperas64d; - "imperas64m": if (`M_SUPPORTED) tests = imperas64m; - "wally64a": if (`A_SUPPORTED) tests = wally64a; - "imperas64c": if (`C_SUPPORTED) tests = imperas64c; - else tests = imperas64iNOc; - "custom": tests = custom; - "wally64i": tests = wally64i; - "wally64priv": tests = wally64priv; - "wally64periph": tests = wally64periph; - "coremark": tests = coremark; - "fpga": tests = fpga; - "ahb" : tests = ahb; - "coverage64gc" : tests = coverage64gc; - "arch64zba": if (`ZBA_SUPPORTED) tests = arch64zba; - "arch64zbb": if (`ZBB_SUPPORTED) tests = arch64zbb; - "arch64zbc": if (`ZBC_SUPPORTED) tests = arch64zbc; - "arch64zbs": if (`ZBS_SUPPORTED) tests = arch64zbs; + "imperas64i": tests = imperas64i; + "imperas64f": if (`F_SUPPORTED) tests = imperas64f; + "imperas64d": if (`D_SUPPORTED) tests = imperas64d; + "imperas64m": if (`M_SUPPORTED) tests = imperas64m; + "wally64a": if (`A_SUPPORTED) tests = wally64a; + "imperas64c": if (`C_SUPPORTED) tests = imperas64c; + else tests = imperas64iNOc; + "custom": tests = custom; + "wally64i": tests = wally64i; + "wally64priv": tests = wally64priv; + "wally64periph": tests = wally64periph; + "coremark": tests = coremark; + "fpga": tests = fpga; + "ahb" : tests = ahb; + "coverage64gc" : tests = coverage64gc; + "arch64zba": if (`ZBA_SUPPORTED) tests = arch64zba; + "arch64zbb": if (`ZBB_SUPPORTED) tests = arch64zbb; + "arch64zbc": if (`ZBC_SUPPORTED) tests = arch64zbc; + "arch64zbs": if (`ZBS_SUPPORTED) tests = arch64zbs; endcase end else begin // RV32 case (TEST) - "arch32i": tests = arch32i; - "arch32priv": tests = arch32priv; + "arch32i": tests = arch32i; + "arch32priv": tests = arch32priv; "arch32c": if (`C_SUPPORTED) - if (`ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv}; - else tests = {arch32c}; - "arch32m": if (`M_SUPPORTED) tests = arch32m; - "arch32f": if (`F_SUPPORTED) tests = arch32f; - "arch32d": if (`D_SUPPORTED) tests = arch32d; + if (`ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv}; + else tests = {arch32c}; + "arch32m": if (`M_SUPPORTED) tests = arch32m; + "arch32f": if (`F_SUPPORTED) tests = arch32f; + "arch32d": if (`D_SUPPORTED) tests = arch32d; "arch32zi": if (`ZIFENCEI_SUPPORTED) tests = arch32zi; - "imperas32i": tests = imperas32i; - "imperas32f": if (`F_SUPPORTED) tests = imperas32f; - "imperas32m": if (`M_SUPPORTED) tests = imperas32m; - "wally32a": if (`A_SUPPORTED) tests = wally32a; - "imperas32c": if (`C_SUPPORTED) tests = imperas32c; - else tests = imperas32iNOc; - "wally32i": tests = wally32i; - "wally32e": tests = wally32e; - "wally32priv": tests = wally32priv; - "wally32periph": tests = wally32periph; - "embench": tests = embench; - "coremark": tests = coremark; - "arch32zba": if (`ZBA_SUPPORTED) tests = arch32zba; - "arch32zbb": if (`ZBB_SUPPORTED) tests = arch32zbb; - "arch32zbc": if (`ZBC_SUPPORTED) tests = arch32zbc; - "arch32zbs": if (`ZBS_SUPPORTED) tests = arch32zbs; + "imperas32i": tests = imperas32i; + "imperas32f": if (`F_SUPPORTED) tests = imperas32f; + "imperas32m": if (`M_SUPPORTED) tests = imperas32m; + "wally32a": if (`A_SUPPORTED) tests = wally32a; + "imperas32c": if (`C_SUPPORTED) tests = imperas32c; + else tests = imperas32iNOc; + "wally32i": tests = wally32i; + "wally32e": tests = wally32e; + "wally32priv": tests = wally32priv; + "wally32periph": tests = wally32periph; + "embench": tests = embench; + "coremark": tests = coremark; + "arch32zba": if (`ZBA_SUPPORTED) tests = arch32zba; + "arch32zbb": if (`ZBB_SUPPORTED) tests = arch32zbb; + "arch32zbc": if (`ZBC_SUPPORTED) tests = arch32zbc; + "arch32zbs": if (`ZBS_SUPPORTED) tests = arch32zbs; endcase end if (tests.size() == 0) begin @@ -149,7 +149,7 @@ module testbench; end end - string signame, memfilename, pathname, objdumpfilename, adrstr, outputfile; + string signame, memfilename, pathname, objdumpfilename, adrstr, outputfile; integer outputFilePointer; logic [31:0] GPIOIN, GPIOOUT, GPIOEN; @@ -160,16 +160,16 @@ module testbench; logic SDCCmdOut; logic SDCCmdOE; logic [3:0] SDCDatIn; - tri1 [3:0] SDCDat; + tri1 [3:0] SDCDat; tri1 SDCCmd; logic HREADY; logic HSELEXT; - logic InitializingMemories; - integer ResetCount, ResetThreshold; - logic InReset; - logic Begin; + logic InitializingMemories; + integer ResetCount, ResetThreshold; + logic InReset; + logic BeginSample; // instantiate device to be tested assign GPIOIN = 0; @@ -225,13 +225,14 @@ module testbench; totalerrors = 0; testadr = 0; testadrNoBase = 0; - // riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests and tests[0] == "2" refers to WallyRiscvArchTests + // riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests + // and tests[0] == "2" refers to WallyRiscvArchTests riscofTest = tests[0] == "1" | tests[0] == "2"; // fill memory with defined values to reduce Xs in simulation // Quick note the memory will need to be initialized. The C library does not - // guarantee the initialized reads. For example a strcmp can read 6 byte - // strings, but uses a load double to read them in. If the last 2 bytes are - // not initialized the compare results in an 'x' which propagates through + // guarantee the initialized reads. For example a strcmp can read 6 byte + // strings, but uses a load double to read them in. If the last 2 bytes are + // not initialized the compare results in an 'x' which propagates through // the design. if (TEST == "coremark") for (i=MemStartAddr; i