diff --git a/config/rv32gc/imperas.ic b/config/rv32gc/imperas.ic
index 011c3622e..76bc2bf54 100644
--- a/config/rv32gc/imperas.ic
+++ b/config/rv32gc/imperas.ic
@@ -17,7 +17,7 @@
 --override cpu/Zicboz=T
 --override cmomp_bytes=64  # Zic64b
 --override cmoz_bytes=64   # Zic64b
---override lr_sc_grain=0   # Za64rs requires <=64; we use native word size
+--override lr_sc_grain=4   # Za64rs requires <=64; we use native word size
 
 # Virtual memory
 --override cpu/Sv_modes=3 # SV32 supported
@@ -45,7 +45,7 @@
 
 # PMP Configuration
 --override cpu/PMP_registers=16
---override cpu/PMP_grain=4   # 64-byte grains to match cache line width
+--override cpu/PMP_grain=0   # 64-byte grains to match cache line width
 --override cpu/PMP_decompose=T  # unaligned accesses are decomposed into separate aligned accesses
 --override cpu/PMP_undefined=T # access to unimplemented PMP registers cause illegal instruction exception
 
diff --git a/testbench/common/riscvassertions.sv b/testbench/common/riscvassertions.sv
index 4c4d873fc..7f6f61c52 100644
--- a/testbench/common/riscvassertions.sv
+++ b/testbench/common/riscvassertions.sv
@@ -22,9 +22,9 @@
 module riscvassertions import cvw::*; #(parameter cvw_t P);
   initial begin
     assert (P.PMP_ENTRIES == 0 | P.PMP_ENTRIES==16 | P.PMP_ENTRIES==64) else $fatal(1, "Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
-    assert (P.PMP_G > 0 | P.XLEN == 32 | P.PMP_ENTRIES == 0) else $fatal(1, "RV64 requires PMP_G at least 1 to avoid checking for 8-byte accesses to 4-byte region");
-    assert ((P.PMP_G >= $clog2(P.DCACHE_LINELENINBITS/8)-2) | !P.ZICCLSM_SUPPORTED | P.PMP_ENTRIES == 0) else $fatal(1, "Systems that support misaligned data with PMP must have grain size of at least one cache line so accesses that span grains will also cause spills");
-    assert ((P.PMP_G >= $clog2(P.ICACHE_LINELENINBITS/8)-2) | !P.ZCA_SUPPORTED | (P.PMP_ENTRIES == 0) | !P.ICACHE_SUPPORTED) else $fatal(1, "Systems that support compressed instructions with PMP must have grain size of at least one cache line so fetches that span grains will also cause spills");
+//    assert (P.PMP_G > 0 | P.XLEN == 32 | P.PMP_ENTRIES == 0) else $fatal(1, "RV64 requires PMP_G at least 1 to avoid checking for 8-byte accesses to 4-byte region");
+//    assert ((P.PMP_G >= $clog2(P.DCACHE_LINELENINBITS/8)-2) | !P.ZICCLSM_SUPPORTED | P.PMP_ENTRIES == 0) else $fatal(1, "Systems that support misaligned data with PMP must have grain size of at least one cache line so accesses that span grains will also cause spills");
+//    assert ((P.PMP_G >= $clog2(P.ICACHE_LINELENINBITS/8)-2) | !P.ZCA_SUPPORTED | (P.PMP_ENTRIES == 0) | !P.ICACHE_SUPPORTED) else $fatal(1, "Systems that support compressed instructions with PMP must have grain size of at least one cache line so fetches that span grains will also cause spills");
     assert (P.PMP_G < P.PA_BITS-2 | P.PMP_ENTRIES == 0) else $fatal(1, "PMP granularity must be less than the number of physical address bits");
     assert (P.IDIV_BITSPERCYCLE == 1 | P.IDIV_BITSPERCYCLE==2 | P.IDIV_BITSPERCYCLE==4) else $fatal(1, "Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4");
     assert (P.F_SUPPORTED | !P.D_SUPPORTED) else $fatal(1, "Can't support double fp (D) without supporting float (F)");