diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl
index 0f32854de..63dbc0b79 100644
--- a/fpga/generator/wally.tcl
+++ b/fpga/generator/wally.tcl
@@ -83,8 +83,7 @@ if {$board=="ArtyA7"} {
     source ../constraints/small-debug.xdc
 
 } else {
-    # *** RT: 16 June 2023 must add back in the debugger 
-    #source ../constraints/debug4.xdc
+    source ../constraints/debug4.xdc
 }
 
 
diff --git a/fpga/src/wallypipelinedsocwrapper.sv b/fpga/src/wallypipelinedsocwrapper.sv
index 80adff7cf..0ba69d167 100644
--- a/fpga/src/wallypipelinedsocwrapper.sv
+++ b/fpga/src/wallypipelinedsocwrapper.sv
@@ -64,7 +64,7 @@ module wallypipelinedsocwrapper (
 );
   `include "parameter-defs.vh"
 
-  wallypipelinedsoc  #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
+  wallypipelinedsoc  #(P) wallypipelinedsoc(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
     .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
     .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
     .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK);