From 1a77c08f6e614627c1570ab80662859b918049b6 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 16 Jan 2024 10:46:44 -0800 Subject: [PATCH] Fixed issues 575 and 477 about FPU tests failing when Zfh = 1. --- src/fpu/postproc/cvtshiftcalc.sv | 2 +- src/fpu/postproc/round.sv | 8 +-- testbench/tests.vh | 97 -------------------------------- 3 files changed, 5 insertions(+), 102 deletions(-) diff --git a/src/fpu/postproc/cvtshiftcalc.sv b/src/fpu/postproc/cvtshiftcalc.sv index 1150d4ecc..ff3d29b90 100644 --- a/src/fpu/postproc/cvtshiftcalc.sv +++ b/src/fpu/postproc/cvtshiftcalc.sv @@ -82,7 +82,7 @@ module cvtshiftcalc import cvw::*; #(parameter cvw_t P) ( P.FMT: ResNegNF = -($clog2(P.NF)+1)'(P.NF); P.FMT1: ResNegNF = -($clog2(P.NF)+1)'(P.NF1); P.FMT2: ResNegNF = -($clog2(P.NF)+1)'(P.NF2); - default: ResNegNF = 'x; + default: ResNegNF = 0; // Not used for floating-point so don't care, but convert to unsigned long has OutFmt = 11. endcase end else if (P.FPSIZES == 4) begin diff --git a/src/fpu/postproc/round.sv b/src/fpu/postproc/round.sv index e01ff376b..460786135 100644 --- a/src/fpu/postproc/round.sv +++ b/src/fpu/postproc/round.sv @@ -145,18 +145,18 @@ module round import cvw::*; #(parameter cvw_t P) ( end else if (P.FPSIZES == 3) begin // 1: XLEN > NF > NF1 - if (XLENPOS == 1) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF2-2:P.CORRSHIFTSZ-P.NF1-1]&FpRes&(OutFmt==P.FMT1)) | + if (XLENPOS == 1) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF2-2:P.CORRSHIFTSZ-P.NF1-1]&FpRes&(OutFmt==P.FMT2)) | (|Mf[P.CORRSHIFTSZ-P.NF1-2:P.CORRSHIFTSZ-P.NF-1]&FpRes&~(OutFmt==P.FMT)) | (|Mf[P.CORRSHIFTSZ-P.NF-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes) | (|Mf[P.CORRSHIFTSZ-P.XLEN-2:0]); // 2: NF > XLEN > NF1 - if (XLENPOS == 2) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF2-2:P.CORRSHIFTSZ-P.NF1-1]&FpRes&(OutFmt==P.FMT1)) | + if (XLENPOS == 2) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF2-2:P.CORRSHIFTSZ-P.NF1-1]&FpRes&(OutFmt==P.FMT2)) | (|Mf[P.CORRSHIFTSZ-P.NF1-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes&~(OutFmt==P.FMT)) | (|Mf[P.CORRSHIFTSZ-P.XLEN-2:P.CORRSHIFTSZ-P.NF-1]&(IntRes|~(OutFmt==P.FMT))) | (|Mf[P.CORRSHIFTSZ-P.NF-2:0]); // 3: NF > NF1 > XLEN - if (XLENPOS == 3) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF2-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes&(OutFmt==P.FMT1)) | - (|Mf[P.CORRSHIFTSZ-P.XLEN-2:P.CORRSHIFTSZ-P.NF1-1]&((OutFmt==P.FMT1)|IntRes)) | + if (XLENPOS == 3) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF2-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes&(OutFmt==P.FMT2)) | + (|Mf[P.CORRSHIFTSZ-P.XLEN-2:P.CORRSHIFTSZ-P.NF1-1]&((OutFmt==P.FMT2)|IntRes)) | (|Mf[P.CORRSHIFTSZ-P.NF1-2:P.CORRSHIFTSZ-P.NF-1]&(~(OutFmt==P.FMT)|IntRes)) | (|Mf[P.CORRSHIFTSZ-P.NF-2:0]); diff --git a/testbench/tests.vh b/testbench/tests.vh index 2eef6fc04..86f65eb14 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -1293,7 +1293,6 @@ string imperas32f[] = '{ string arch64zfh[] = '{ `RISCVARCHTEST, - "rv64i_m/Zfh/src/fmv.x.h_b1-01.S", "rv64i_m/Zfh/src/fadd_b10-01.S", "rv64i_m/Zfh/src/fadd_b1-01.S", "rv64i_m/Zfh/src/fadd_b11-01.S", @@ -1360,34 +1359,10 @@ string imperas32f[] = '{ "rv64i_m/Zfh/src/flt_b1-01.S", "rv64i_m/Zfh/src/flt_b19-01.S", "rv64i_m/Zfh/src/flh-align-01.S", -/* "rv64i_m/Zfh/src/fmadd_b1-01.S", - "rv64i_m/Zfh/src/fmadd_b14-01.S", - "rv64i_m/Zfh/src/fmadd_b16-01.S", - "rv64i_m/Zfh/src/fmadd_b17-01.S", - "rv64i_m/Zfh/src/fmadd_b18-01.S", - "rv64i_m/Zfh/src/fmadd_b2-01.S", - "rv64i_m/Zfh/src/fmadd_b3-01.S", - "rv64i_m/Zfh/src/fmadd_b4-01.S", - "rv64i_m/Zfh/src/fmadd_b5-01.S", - "rv64i_m/Zfh/src/fmadd_b6-01.S", - "rv64i_m/Zfh/src/fmadd_b7-01.S", - "rv64i_m/Zfh/src/fmadd_b8-01.S", */ "rv64i_m/Zfh/src/fmax_b1-01.S", "rv64i_m/Zfh/src/fmax_b19-01.S", "rv64i_m/Zfh/src/fmin_b1-01.S", "rv64i_m/Zfh/src/fmin_b19-01.S", -/* "rv64i_m/Zfh/src/fmsub_b1-01.S", - "rv64i_m/Zfh/src/fmsub_b14-01.S", - "rv64i_m/Zfh/src/fmsub_b16-01.S", - "rv64i_m/Zfh/src/fmsub_b17-01.S", - "rv64i_m/Zfh/src/fmsub_b18-01.S", - "rv64i_m/Zfh/src/fmsub_b2-01.S", - "rv64i_m/Zfh/src/fmsub_b3-01.S", - "rv64i_m/Zfh/src/fmsub_b4-01.S", - "rv64i_m/Zfh/src/fmsub_b5-01.S", - "rv64i_m/Zfh/src/fmsub_b6-01.S", - "rv64i_m/Zfh/src/fmsub_b7-01.S", - "rv64i_m/Zfh/src/fmsub_b8-01.S", */ "rv64i_m/Zfh/src/fmul_b1-01.S", "rv64i_m/Zfh/src/fmul_b2-01.S", "rv64i_m/Zfh/src/fmul_b3-01.S", @@ -1406,30 +1381,6 @@ string imperas32f[] = '{ "rv64i_m/Zfh/src/fmv.x.h_b27-01.S", "rv64i_m/Zfh/src/fmv.x.h_b28-01.S", "rv64i_m/Zfh/src/fmv.x.h_b29-01.S", -/* "rv64i_m/Zfh/src/fnmadd_b1-01.S", - "rv64i_m/Zfh/src/fnmadd_b14-01.S", - "rv64i_m/Zfh/src/fnmadd_b16-01.S", - "rv64i_m/Zfh/src/fnmadd_b17-01.S", - "rv64i_m/Zfh/src/fnmadd_b18-01.S", - "rv64i_m/Zfh/src/fnmadd_b2-01.S", - "rv64i_m/Zfh/src/fnmadd_b3-01.S", - "rv64i_m/Zfh/src/fnmadd_b4-01.S", - "rv64i_m/Zfh/src/fnmadd_b5-01.S", - "rv64i_m/Zfh/src/fnmadd_b6-01.S", - "rv64i_m/Zfh/src/fnmadd_b7-01.S", - "rv64i_m/Zfh/src/fnmadd_b8-01.S", - "rv64i_m/Zfh/src/fnmsub_b1-01.S", - "rv64i_m/Zfh/src/fnmsub_b14-01.S", - "rv64i_m/Zfh/src/fnmsub_b16-01.S", - "rv64i_m/Zfh/src/fnmsub_b17-01.S", - "rv64i_m/Zfh/src/fnmsub_b18-01.S", - "rv64i_m/Zfh/src/fnmsub_b2-01.S", - "rv64i_m/Zfh/src/fnmsub_b3-01.S", - "rv64i_m/Zfh/src/fnmsub_b4-01.S", - "rv64i_m/Zfh/src/fnmsub_b5-01.S", - "rv64i_m/Zfh/src/fnmsub_b6-01.S", - "rv64i_m/Zfh/src/fnmsub_b7-01.S", - "rv64i_m/Zfh/src/fnmsub_b8-01.S", */ "rv64i_m/Zfh/src/fsgnj_b1-01.S", "rv64i_m/Zfh/src/fsgnjn_b1-01.S", "rv64i_m/Zfh/src/fsgnjx_b1-01.S", @@ -1998,34 +1949,10 @@ string arch64zbs[] = '{ "rv32i_m/Zfh/src/flt_b1-01.S", "rv32i_m/Zfh/src/flt_b19-01.S", "rv32i_m/Zfh/src/flh-align-01.S", -/* "rv32i_m/Zfh/src/fmadd_b1-01.S", - "rv32i_m/Zfh/src/fmadd_b14-01.S", - "rv32i_m/Zfh/src/fmadd_b16-01.S", - "rv32i_m/Zfh/src/fmadd_b17-01.S", - "rv32i_m/Zfh/src/fmadd_b18-01.S", - "rv32i_m/Zfh/src/fmadd_b2-01.S", - "rv32i_m/Zfh/src/fmadd_b3-01.S", - "rv32i_m/Zfh/src/fmadd_b4-01.S", - "rv32i_m/Zfh/src/fmadd_b5-01.S", - "rv32i_m/Zfh/src/fmadd_b6-01.S", - "rv32i_m/Zfh/src/fmadd_b7-01.S", - "rv32i_m/Zfh/src/fmadd_b8-01.S", */ "rv32i_m/Zfh/src/fmax_b1-01.S", "rv32i_m/Zfh/src/fmax_b19-01.S", "rv32i_m/Zfh/src/fmin_b1-01.S", "rv32i_m/Zfh/src/fmin_b19-01.S", -/* "rv32i_m/Zfh/src/fmsub_b1-01.S", - "rv32i_m/Zfh/src/fmsub_b14-01.S", - "rv32i_m/Zfh/src/fmsub_b16-01.S", - "rv32i_m/Zfh/src/fmsub_b17-01.S", - "rv32i_m/Zfh/src/fmsub_b18-01.S", - "rv32i_m/Zfh/src/fmsub_b2-01.S", - "rv32i_m/Zfh/src/fmsub_b3-01.S", - "rv32i_m/Zfh/src/fmsub_b4-01.S", - "rv32i_m/Zfh/src/fmsub_b5-01.S", - "rv32i_m/Zfh/src/fmsub_b6-01.S", - "rv32i_m/Zfh/src/fmsub_b7-01.S", - "rv32i_m/Zfh/src/fmsub_b8-01.S", */ "rv32i_m/Zfh/src/fmul_b1-01.S", "rv32i_m/Zfh/src/fmul_b2-01.S", "rv32i_m/Zfh/src/fmul_b3-01.S", @@ -2044,30 +1971,6 @@ string arch64zbs[] = '{ "rv32i_m/Zfh/src/fmv.x.h_b27-01.S", "rv32i_m/Zfh/src/fmv.x.h_b28-01.S", "rv32i_m/Zfh/src/fmv.x.h_b29-01.S", -/* "rv32i_m/Zfh/src/fnmadd_b1-01.S", - "rv32i_m/Zfh/src/fnmadd_b14-01.S", - "rv32i_m/Zfh/src/fnmadd_b16-01.S", - "rv32i_m/Zfh/src/fnmadd_b17-01.S", - "rv32i_m/Zfh/src/fnmadd_b18-01.S", - "rv32i_m/Zfh/src/fnmadd_b2-01.S", - "rv32i_m/Zfh/src/fnmadd_b3-01.S", - "rv32i_m/Zfh/src/fnmadd_b4-01.S", - "rv32i_m/Zfh/src/fnmadd_b5-01.S", - "rv32i_m/Zfh/src/fnmadd_b6-01.S", - "rv32i_m/Zfh/src/fnmadd_b7-01.S", - "rv32i_m/Zfh/src/fnmadd_b8-01.S", - "rv32i_m/Zfh/src/fnmsub_b1-01.S", - "rv32i_m/Zfh/src/fnmsub_b14-01.S", - "rv32i_m/Zfh/src/fnmsub_b16-01.S", - "rv32i_m/Zfh/src/fnmsub_b17-01.S", - "rv32i_m/Zfh/src/fnmsub_b18-01.S", - "rv32i_m/Zfh/src/fnmsub_b2-01.S", - "rv32i_m/Zfh/src/fnmsub_b3-01.S", - "rv32i_m/Zfh/src/fnmsub_b4-01.S", - "rv32i_m/Zfh/src/fnmsub_b5-01.S", - "rv32i_m/Zfh/src/fnmsub_b6-01.S", - "rv32i_m/Zfh/src/fnmsub_b7-01.S", - "rv32i_m/Zfh/src/fnmsub_b8-01.S", */ "rv32i_m/Zfh/src/fsgnj_b1-01.S", "rv32i_m/Zfh/src/fsgnjn_b1-01.S", "rv32i_m/Zfh/src/fsgnjx_b1-01.S",