diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh
index e506015e7..3f885cd2d 100644
--- a/config/rv32gc/coverage.svh
+++ b/config/rv32gc/coverage.svh
@@ -17,6 +17,10 @@
 `define M_COVERAGE
 `define F_COVERAGE
 `define D_COVERAGE
+`define VX8_COVERAGE
+`define VX16_COVERAGE
+`define VX32_COVERAGE
+`define VX64_COVERAGE
 `define ZBA_COVERAGE
 `define ZBB_COVERAGE
 `define ZBC_COVERAGE
diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh
index 67ad14410..664e27087 100644
--- a/config/rv64gc/coverage.svh
+++ b/config/rv64gc/coverage.svh
@@ -17,6 +17,10 @@
 `define M_COVERAGE
 `define F_COVERAGE
 `define D_COVERAGE
+`define VX8_COVERAGE
+`define VX16_COVERAGE
+`define VX32_COVERAGE
+`define VX64_COVERAGE
 `define ZBA_COVERAGE
 `define ZBB_COVERAGE
 `define ZBC_COVERAGE
diff --git a/tests/riscof/sail_cSim/riscof_sail_cSim.py b/tests/riscof/sail_cSim/riscof_sail_cSim.py
index 3b21fd04b..a9e4fcc64 100644
--- a/tests/riscof/sail_cSim/riscof_sail_cSim.py
+++ b/tests/riscof/sail_cSim/riscof_sail_cSim.py
@@ -63,6 +63,8 @@ class sail_cSim(pluginTemplate):
             self.isa += 'd'
         if "Q" in ispec["ISA"]:
             self.isa += 'q'
+        if "V" in ispec["ISA"]:
+            self.isa += 'v'
         objdump = "riscv64-unknown-elf-objdump"
         if shutil.which(objdump) is None:
             logger.error(objdump+": executable not found. Please check environment setup.")
diff --git a/tests/riscof/sail_cSim/rv32gc.json b/tests/riscof/sail_cSim/rv32gc.json
index 13082b9bb..7f4463aad 100644
--- a/tests/riscof/sail_cSim/rv32gc.json
+++ b/tests/riscof/sail_cSim/rv32gc.json
@@ -56,7 +56,7 @@
       "supported": true
     },
     "V": {
-      "supported": false,
+      "supported": true,
       "vlen_exp": 9,
       "elen_exp": 6,
       "vl_use_ceil": false
diff --git a/tests/riscof/sail_cSim/rv64gc.json b/tests/riscof/sail_cSim/rv64gc.json
index 95df5d5f1..d7ad717ea 100644
--- a/tests/riscof/sail_cSim/rv64gc.json
+++ b/tests/riscof/sail_cSim/rv64gc.json
@@ -56,7 +56,7 @@
       "supported": true
     },
     "V": {
-      "supported": false,
+      "supported": true,
       "vlen_exp": 9,
       "elen_exp": 6,
       "vl_use_ceil": false
diff --git a/tests/riscof/spike/riscof_spike.py b/tests/riscof/spike/riscof_spike.py
index fcb07f900..474ac63ff 100644
--- a/tests/riscof/spike/riscof_spike.py
+++ b/tests/riscof/spike/riscof_spike.py
@@ -103,6 +103,8 @@ class spike(pluginTemplate):
           self.isa += 'q'
       if "C" in ispec["ISA"]:
           self.isa += 'c'
+      if "V" in ispec["ISA"]:
+          self.isa += 'v'
       if "Zicsr" in ispec["ISA"]:
           self.isa += '_Zicsr'
       if "Zicond" in ispec["ISA"]:
diff --git a/tests/riscof/spike/spike_rv32gc_isa.yaml b/tests/riscof/spike/spike_rv32gc_isa.yaml
index fc8ed99fc..85df658d1 100644
--- a/tests/riscof/spike/spike_rv32gc_isa.yaml
+++ b/tests/riscof/spike/spike_rv32gc_isa.yaml
@@ -1,11 +1,11 @@
 hart_ids: [0]
 hart0:
-  ISA: RV32IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zcd_Zcf_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
+  ISA: RV32IMAFDCVSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zcd_Zcf_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
   physical_addr_sz: 32
   User_Spec_Version: '2.3'
   supported_xlen: [32]
   misa:
-    reset-val: 0x4014112D
+    reset-val: 0x4034112D
     rv32:
       accessible: true
       mxl:
@@ -23,7 +23,7 @@ hart0:
           warl:
             dependency_fields: []
             legal:
-              - extensions[25:0] bitmask [0x014112D, 0x0000000]
+              - extensions[25:0] bitmask [0x034112D, 0x0000000]
             wr_illegal:
               - Unchanged
   PMP:
@@ -31,3 +31,4 @@ hart0:
     pmp-grain: 0
     pmp-count: 16
     pmp-writable: 12
+
diff --git a/tests/riscof/spike/spike_rv64gc_isa.yaml b/tests/riscof/spike/spike_rv64gc_isa.yaml
index b7ad5a045..59dd09653 100644
--- a/tests/riscof/spike/spike_rv64gc_isa.yaml
+++ b/tests/riscof/spike/spike_rv64gc_isa.yaml
@@ -1,11 +1,11 @@
 hart_ids: [0]
 hart0:
-  ISA: RV64IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zcd_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
+  ISA: RV64IMAFDCVSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zcd_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
   physical_addr_sz: 56
   User_Spec_Version: '2.3'
   supported_xlen: [64]
   misa:
-    reset-val: 0x800000000014112D
+    reset-val: 0x800000000034112D
     rv32:
       accessible: false
     rv64:
@@ -25,7 +25,7 @@ hart0:
           warl:
             dependency_fields: []
             legal:
-              - extensions[25:0] bitmask [0x015112D, 0x0000000]
+              - extensions[25:0] bitmask [0x035112D, 0x0000000]
             wr_illegal:
               - Unchanged
   PMP: