From 1df3e5239a56f8639b1539b7288f87e2384086af Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Thu, 30 May 2024 17:57:28 -0500
Subject: [PATCH] This is great.  The FPGA is able to send ethernet frames
 consisting of the RVVI data to the host computer. wireshark is able to
 capture the frames and they match the expected data!

---
 src/rvvi/packetizer.sv | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/rvvi/packetizer.sv b/src/rvvi/packetizer.sv
index 93390d03b..1040e8593 100644
--- a/src/rvvi/packetizer.sv
+++ b/src/rvvi/packetizer.sv
@@ -71,7 +71,8 @@ module packetizer import cvw::*; #(parameter cvw_t P,
     case(CurrState)
       STATE_RDY: if (TransReady & valid) NextState = STATE_TRANS;
       else if(~TransReady & valid) NextState = STATE_WAIT;
-      STATE_WAIT: if(TransReady) NextState = STATE_TRANS;
+      else                        NextState = STATE_RDY;
+      STATE_WAIT: if(TransReady)   NextState = STATE_TRANS;
       else NextState = STATE_WAIT;
       STATE_TRANS: if(BurstDone) NextState = STATE_RDY;
       else NextState = STATE_TRANS;