diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index 034c41512..25b0ad365 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -212,7 +212,7 @@ localparam PLIC_SPI_ID = 32'd6; localparam PLIC_SDC_ID = 32'd9; // Branch prediction -localparam logic BPRED_SUPPORTED = 1; +localparam logic BPRED_SUPPORTED = 0; localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; diff --git a/sim/questa/wave.do b/sim/questa/wave.do index 7896dcdb5..781dd2f83 100644 --- a/sim/questa/wave.do +++ b/sim/questa/wave.do @@ -18,6 +18,7 @@ add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ieu/c/MDUStallD add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/FetchBufferStallF add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM @@ -42,29 +43,57 @@ add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbe add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW +add wave -noupdate -expand -group HDU -expand -group Stall /testbench/dut/core/ifu/StallFBF +add wave -noupdate -expand -group HDU -expand -group Stall /testbench/dut/core/ifu/NoStallPCF add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/PendingIntsM add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/InstrValidM add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/ValidIntsM add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/hzu/WFIInterruptedM add wave -noupdate /testbench/dut/core/StallW -add wave -noupdate -expand -label {Contributors: StallW} -group {Contributors: sim:/testbench/dut/core/StallW} /testbench/dut/core/hzu/StallWCause add wave -noupdate /testbench/dut/core/hzu/StallWCause -add wave -noupdate -expand -label {Contributors: StallWCause} -group {Contributors: sim:/testbench/dut/core/hzu/StallWCause} /testbench/dut/core/hzu/ExternalStall -add wave -noupdate -expand -label {Contributors: StallWCause} -group {Contributors: sim:/testbench/dut/core/hzu/StallWCause} /testbench/dut/core/hzu/FlushDCause -add wave -noupdate -expand -label {Contributors: StallWCause} -group {Contributors: sim:/testbench/dut/core/hzu/StallWCause} /testbench/dut/core/hzu/FlushWCause -add wave -noupdate -expand -label {Contributors: StallWCause} -group {Contributors: sim:/testbench/dut/core/hzu/StallWCause} /testbench/dut/core/hzu/IFUStallF -add wave -noupdate -expand -label {Contributors: StallWCause} -group {Contributors: sim:/testbench/dut/core/hzu/StallWCause} /testbench/dut/core/hzu/LSUStallM add wave -noupdate /testbench/dut/core/hzu/IFUStallF -add wave -noupdate -expand -label {Contributors: IFUStallF} -group {Contributors: sim:/testbench/dut/core/hzu/IFUStallF} /testbench/dut/core/ifu/IFUCacheBusStallF -add wave -noupdate -expand -label {Contributors: IFUStallF} -group {Contributors: sim:/testbench/dut/core/hzu/IFUStallF} /testbench/dut/core/ifu/SelSpillNextF +add wave -noupdate -label {Contributors: IFUStallF} -group {Contributors: sim:/testbench/dut/core/hzu/IFUStallF} /testbench/dut/core/ifu/IFUCacheBusStallF +add wave -noupdate -label {Contributors: IFUStallF} -group {Contributors: sim:/testbench/dut/core/hzu/IFUStallF} /testbench/dut/core/ifu/SelSpillNextF add wave -noupdate /testbench/dut/core/ifu/IFUCacheBusStallF -add wave -noupdate -expand -label {Contributors: IFUCacheBusStallF} -group {Contributors: sim:/testbench/dut/core/ifu/IFUCacheBusStallF} /testbench/dut/core/ifu/BusStall -add wave -noupdate -expand -label {Contributors: IFUCacheBusStallF} -group {Contributors: sim:/testbench/dut/core/ifu/IFUCacheBusStallF} /testbench/dut/core/ifu/ICacheStallF -add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName -add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF -add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrD -add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrE -add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrM +add wave -noupdate -label {Contributors: IFUCacheBusStallF} -group {Contributors: sim:/testbench/dut/core/ifu/IFUCacheBusStallF} /testbench/dut/core/ifu/BusStall +add wave -noupdate -label {Contributors: IFUCacheBusStallF} -group {Contributors: sim:/testbench/dut/core/ifu/IFUCacheBusStallF} /testbench/dut/core/ifu/ICacheStallF +add wave -noupdate -group {instruction pipeline} /testbench/InstrFName +add wave -noupdate -group {instruction pipeline} {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/CacheTagMem/ce} +add wave -noupdate -group {instruction pipeline} {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/CacheTagMem/addr} +add wave -noupdate -group {instruction pipeline} {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/CacheTagMem/ram/addrd} +add wave -noupdate -group {instruction pipeline} -radix decimal {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/CacheSetTag} +add wave -noupdate -group {instruction pipeline} {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/ValidBits} +add wave -noupdate -group {instruction pipeline} {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/PAdr} +add wave -noupdate -group {instruction pipeline} {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/ReadTag} +add wave -noupdate -group {instruction pipeline} {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/InvalidateCacheDelay} +add wave -noupdate -group {instruction pipeline} {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/ValidWay} +add wave -noupdate -group {instruction pipeline} {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/HitWay} +add wave -noupdate -group {instruction pipeline} {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/FlushCache} +add wave -noupdate -group {instruction pipeline} {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/SelVictim} +add wave -noupdate -group {instruction pipeline} {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/SelectedWay} +add wave -noupdate -group {instruction pipeline} -expand /testbench/dut/core/ifu/bus/icache/icache/ReadDataLineWay +add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/bus/icache/icache/ReadDataLineCache +add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/bus/icache/icache/SelFetchBuffer +add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/bus/icache/icache/WordOffsetAddr +add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/bus/icache/icache/ReadDataLine +add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/ICacheInstrF +add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/SelIROM +add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/CacheableF +add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/Spill/spill/InstrRawF +add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/Spill/spill/SelSpillF +add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF +add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD +add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE +add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM +add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/CompressedF +add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCPlus2or4F +add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/BPWrongE +add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PC1NextF +add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/CSRWriteFenceM +add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PC2NextF +add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/RetM +add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/TrapM +add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/UnalignedPCNextF add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCNextF add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCF add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCD @@ -394,8 +423,8 @@ add wave -noupdate -expand -group FetchBuffer -label {PCFB[2]} {/testbench/dut/c add wave -noupdate -expand -group FetchBuffer -label {PCFB[1]} {/testbench/dut/core/ifu/fetchbuffer/PCFetchBuffer/fbEntries[1]/q} add wave -noupdate -expand -group FetchBuffer -label {PCFB[0]} {/testbench/dut/core/ifu/fetchbuffer/PCFetchBuffer/fbEntries[0]/q} TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{potential optimization} {2680 ns} 1} {{WHY IFU STALL?} {7010 ns} 1} -quietly wave cursor active 1 +WaveRestoreCursors {{potential optimization} {2680 ns} 1} {{WHY IFU STALL?} {7010 ns} 1} {{Cursor 3} {7010 ns} 1} {{Cursor 4} {2518 ns} 0} +quietly wave cursor active 4 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 configure wave -justifyvalue left @@ -410,4 +439,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {2630 ns} {2730 ns} +WaveRestoreZoom {2468 ns} {2577 ns} diff --git a/src/hazard/hazard.sv b/src/hazard/hazard.sv index 1ce32f765..29969dce7 100644 --- a/src/hazard/hazard.sv +++ b/src/hazard/hazard.sv @@ -43,7 +43,7 @@ module hazard ( input logic wfiM, IntPendingM, // Stall & flush outputs - output logic StallF, + output logic StallF, StallFBF, StallD, StallE, StallM, @@ -97,14 +97,17 @@ module hazard ( // The IFU and LSU stall the entire pipeline on a cache miss, bus access, or other long operation. // The IFU stalls the entire pipeline rather than just Fetch to avoid complications with instructions later in the pipeline causing Exceptions // A trap could be asserted at the start of a IFU/LSU stall, and should flush the memory operation - assign StallFCause = FetchBufferStallF | (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause); + + + assign StallFBF = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause); + assign StallFCause = StallFBF | FetchBufferStallF; assign StallDCause = (StructuralStallD | FPUStallD) & ~FlushDCause; // TODO: add stall if empty fetch buffer assign StallECause = (DivBusyE | FDivBusyE) & ~FlushECause; assign StallMCause = WFIStallM & ~FlushMCause; // Need to gate IFUStallF when the equivalent FlushFCause = FlushDCause = 1. // assign StallWCause = ((IFUStallF & ~FlushDCause) | LSUStallM) & ~FlushWCause; // Because FlushWCause is a strict subset of FlushDCause, FlushWCause is factored out. - assign StallWCause = (IFUStallF & ~FlushDCause) |(LSUStallM & ~FlushWCause) | ExternalStall; + assign StallWCause = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause) | ExternalStall; // Stall each stage for cause or if the next stage is stalled // coverage off: StallFCause is always 0 diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index 0e6a36cb8..534089ec2 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -28,7 +28,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( input logic clk, reset, - input logic StallF, StallD, StallE, StallM, StallW, + input logic StallF, StallD, StallE, StallM, StallW, StallFBF, input logic FlushD, FlushE, FlushM, FlushW, output logic IFUStallF, // IFU stalsl pipeline during a multicycle operation // Command from CPU @@ -303,9 +303,12 @@ module ifu import cvw::*; #(parameter cvw_t P) ( assign IFUStallF = IFUCacheBusStallF | SelSpillNextF; assign GatedStallD = StallD & ~SelSpillNextF; + logic NoStallPCF; if (P.FETCHBUFFER_ENTRIES != 0) begin : fetchbuffer fetchbuffer #(P) fetchbuff(.clk, .reset, .StallF, .StallD, .FlushD, .nop, .WriteData(PostSpillInstrRawF), .ReadData(InstrRawD), .FetchBufferStallF); - logic PCFetchBufferStallD; + logic PCFetchBufferStallD, FetchBufferStallFDelay; + flop #(1) flop1 (clk, FetchBufferStallF, FetchBufferStallFDelay); + assign NoStallPCF = ~FetchBufferStallFDelay & FetchBufferStallF; fetchbuffer #(P, P.XLEN) PCFetchBuffer(.clk, .reset, .StallF, .StallD, .FlushD, .nop({{1'b1},{(P.XLEN-1){1'b0}}}), .WriteData(PCF), .ReadData(PCD), .FetchBufferStallF(PCFetchBufferStallD)); end else begin flopenl #(32) AlignedInstrRawDFlop(clk, reset | FlushD, ~StallD, PostSpillInstrRawF, nop, InstrRawD); @@ -323,7 +326,9 @@ module ifu import cvw::*; #(parameter cvw_t P) ( mux3 #(P.XLEN) pcmux3(PC2NextF, EPCM, TrapVectorM, {TrapM, RetM}, UnalignedPCNextF); mux2 #(P.XLEN) pcresetmux({UnalignedPCNextF[P.XLEN-1:1], 1'b0}, P.RESET_VECTOR[P.XLEN-1:0], reset, PCNextF); - flopen #(P.XLEN) pcreg(clk, ~StallF | reset, PCNextF, PCF); + logic PCEnable; + assign PCEnable = NoStallPCF | ~StallF | reset; + flopen #(P.XLEN) pcreg(clk, PCEnable, PCNextF, PCF); //* make this NoStallPCF // pcadder // add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32 diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index 967f65eb8..cf4826ad2 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -48,7 +48,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( input logic ExternalStall ); - logic StallF, StallD, StallE, StallM, StallW; + logic StallF, StallD, StallE, StallM, StallW, StallFBF; logic FlushD, FlushE, FlushM, FlushW; logic TrapM, RetM; @@ -175,7 +175,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( // instruction fetch unit: PC, branch prediction, instruction cache ifu #(P) ifu(.clk, .reset, - .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, + .StallF, .StallD, .StallE, .StallM, .StallW, .StallFBF, .FlushD, .FlushE, .FlushM, .FlushW, .InstrValidE, .InstrValidD, .BranchD, .BranchE, .JumpD, .JumpE, .ICacheStallF, // Fetch @@ -282,7 +282,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .DivBusyE, .FDivBusyE, .wfiM, .IntPendingM, // Stall & flush outputs - .StallF, .StallD, .StallE, .StallM, .StallW, + .StallF, .StallD, .StallE, .StallM, .StallW, .StallFBF, .FlushD, .FlushE, .FlushM, .FlushW); // privileged unit diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 4749b26ab..385291fd7 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -751,7 +751,7 @@ end .CMP_CSR (1) ) idv_trace2api(rvvi); - `include "RV_Assertions.sv" + // `include "RV_Assertions.sv" string filename; initial begin