From 1f57df7f8b378cea00e66cd82d962df5af8d4d20 Mon Sep 17 00:00:00 2001
From: David Harris <David_Harris@hmc.edu>
Date: Thu, 23 Nov 2023 20:29:10 -0800
Subject: [PATCH] Fixed reference to deleted atomic signal in cache

---
 src/lsu/lsu.sv              | 4 ++--
 testbench/common/loggers.sv | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv
index 396fa1515..5c21d7ecd 100644
--- a/src/lsu/lsu.sv
+++ b/src/lsu/lsu.sv
@@ -196,8 +196,8 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
     assign PreLSURWM = MemRWM; 
     assign IHAdrM = IEUAdrExtM;
     assign LSUFunct3M = Funct3M;
-  assign LSUFunct7M = Funct7M; 
-  assign LSUAtomicM = AtomicM;
+    assign LSUFunct7M = Funct7M; 
+    assign LSUAtomicM = AtomicM;
     assign IHWriteDataM = WriteDataM;
     assign LoadAccessFaultM = LSULoadAccessFaultM;
     assign StoreAmoAccessFaultM = LSUStoreAmoAccessFaultM;   
diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv
index 1cf719085..e1cc1795f 100644
--- a/testbench/common/loggers.sv
+++ b/testbench/common/loggers.sv
@@ -182,7 +182,7 @@ module loggers import cvw::*; #(parameter cvw_t P,
                       (!dut.core.lsu.bus.dcache.dcache.vict.cacheLRU.AllValid) ? "M" :
                       dut.core.lsu.bus.dcache.dcache.LineDirty ? "D" : "E";
       AccessTypeString = dut.core.lsu.bus.dcache.FlushDCache ? "F" :
-                         dut.core.lsu.bus.dcache.CacheAtomicM[1] ? "A" :
+                         dut.core.lsu.LSUAtomicM[1] ? "A" :
                          dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" : 
                          dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" :
                          "NULL";