diff --git a/fpga/zsbl/boot.c b/fpga/zsbl/boot.c
index 96bde4205..786879c49 100644
--- a/fpga/zsbl/boot.c
+++ b/fpga/zsbl/boot.c
@@ -46,9 +46,9 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) {
   crc = crc7(crc, sector & 0xff);
   crc = crc | 1;
   
-  if (sd_cmd(18, sector &, crc) != 0x00) {
+  if (sd_cmd(18, sector & 0xffffffff, crc) != 0x00) {
     print_uart("disk_read: CMD18 failed. r = ");
-    print_byte(r & 0xff);
+    print_uart_byte(r & 0xff);
     return -1;
   }
 
@@ -60,7 +60,7 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) {
     r = spi_readbyte();
     if (r != SD_DATA_TOKEN) {
       print_uart("Didn't receive data token first thing. Shoot: ");
-      print_byte(r & 0xff);
+      print_uart_byte(r & 0xff);
       return -1;
     }
 
@@ -76,7 +76,7 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) {
 
     if (crc != crc_exp) {
       print_uart("Stinking CRC16 didn't match on block ");
-      print_int(i);
+      print_uart_int(i);
       print_uart("\r\n");
       return -1;
     }
@@ -104,5 +104,5 @@ void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) {
   // Intialize the SD card
   init_sd();
   
-  ret = gpt_load_partitions(card_type);
+  ret = gpt_load_partitions();
 }
diff --git a/fpga/zsbl/boot.h b/fpga/zsbl/boot.h
index cb0f4e7f3..2048ca47c 100644
--- a/fpga/zsbl/boot.h
+++ b/fpga/zsbl/boot.h
@@ -30,7 +30,7 @@ typedef QWORD LBA_t;
 "     \\___/\\___/ /___/    \\___\\|_______||_______| |___|\n\n"
 
 // Export disk_read
-int disk_read(BYTE * buf, LBA_t sector, UINT count, BYTE card_type);
+int disk_read(BYTE * buf, LBA_t sector, UINT count);
 
 #endif // WALLYBOOT
 
diff --git a/fpga/zsbl/sd.c b/fpga/zsbl/sd.c
index 87e78e7fe..585b98281 100644
--- a/fpga/zsbl/sd.c
+++ b/fpga/zsbl/sd.c
@@ -129,7 +129,7 @@ uint64_t sd_read64(uint16_t * crc) {
 // This first initializes the SPI peripheral then initializes the SD
 // card itself. We use the uart to display anything that goes wrong.
 void init_sd(){
-  init_spi();
+  spi_init();
 
   uint64_t r;
 
diff --git a/fpga/zsbl/spi.c b/fpga/zsbl/spi.c
index 76985a350..cbb9fa2eb 100644
--- a/fpga/zsbl/spi.c
+++ b/fpga/zsbl/spi.c
@@ -30,33 +30,29 @@
 #include "spi.h"
 
 // Write to a register
-inline void write_reg(uintptr_t addr, uint32_t value) {
-  volatile uint32_t * loc = (volatile uint32_t *) addr;
-  *loc = value;
-}
+/* inline void write_reg(uintptr_t addr, uint32_t value) { */
+/*   volatile uint32_t * loc = (volatile uint32_t *) addr; */
+/*   *loc = value; */
+/* } */
 
-// Read a register
-inline void read_reg(uintptr_t addr) {
-  return *(volatile uint32_t *) addr;
-}
+/* // Read a register */
+/* inline uint32_t read_reg(uintptr_t addr) { */
+/*   return *(volatile uint32_t *) addr; */
+/* } */
 
-// Queues a single byte in the transfer fifo
-inline void spi_sendbyte(uint8_t byte) {
-  // Write byte to transfer fifo
-  write_reg(SPI_TXDATA, byte);
-}
+/* // Queues a single byte in the transfer fifo */
+/* inline void spi_sendbyte(uint8_t byte) { */
+/*   // Write byte to transfer fifo */
+/*   write_reg(SPI_TXDATA, byte); */
+/* } */
 
-inline uint8_t spi_readbyte() {
-  return read_reg(SPI_RXDATA);
-}
+/* inline void waittx() { */
+/*   while(!(read_reg(SPI_IP) & 1)) {} */
+/* } */
 
-inline void waittx() {
-  while(!(read_reg(SPI_IP) & 1)) {}
-}
-
-inline void waitrx() {
-  while(read_reg(SPI_IP) & 2)) {}
-}
+/* inline void waitrx() { */
+/*   while(read_reg(SPI_IP) & 2) {} */
+/* } */
 
 uint8_t spi_txrx(uint8_t byte) {
   spi_sendbyte(0xFF);
@@ -64,6 +60,10 @@ uint8_t spi_txrx(uint8_t byte) {
   return spi_readbyte();
 }
 
+/* inline uint8_t spi_readbyte() { */
+/*   return read_reg(SPI_RXDATA); */
+/* } */
+
 uint64_t spi_read64() {
   uint64_t r;
   uint8_t rbyte;
diff --git a/fpga/zsbl/spi.h b/fpga/zsbl/spi.h
index e91bcc0ea..bc85c768f 100644
--- a/fpga/zsbl/spi.h
+++ b/fpga/zsbl/spi.h
@@ -28,15 +28,15 @@
 #define SPI_IP                SPI_BASE + 0x74 /* Interrupt Pendings Register */
 
 /* delay0 bits */
-#define SIFIVE_SPI_DELAY0_CSSCK(x)       ((u32)(x))
+#define SIFIVE_SPI_DELAY0_CSSCK(x)       ((uint32_t)(x))
 #define SIFIVE_SPI_DELAY0_CSSCK_MASK     0xffU
-#define SIFIVE_SPI_DELAY0_SCKCS(x)       ((u32)(x) << 16)
+#define SIFIVE_SPI_DELAY0_SCKCS(x)       ((uint32_t)(x) << 16)
 #define SIFIVE_SPI_DELAY0_SCKCS_MASK     (0xffU << 16)
 
 /* delay1 bits */
-#define SIFIVE_SPI_DELAY1_INTERCS(x)     ((u32)(x))
+#define SIFIVE_SPI_DELAY1_INTERCS(x)     ((uint32_t)(x))
 #define SIFIVE_SPI_DELAY1_INTERCS_MASK   0xffU
-#define SIFIVE_SPI_DELAY1_INTERXFR(x)    ((u32)(x) << 16)
+#define SIFIVE_SPI_DELAY1_INTERXFR(x)    ((uint32_t)(x) << 16)
 #define SIFIVE_SPI_DELAY1_INTERXFR_MASK  (0xffU << 16)
 
 /* csmode bits */
@@ -48,14 +48,42 @@
 #define WAITTX while(!(read_reg(SPI_IP) & 1) {}
 #define WAITRX while(read_reg(SPI_IP) & 2) {}
 
-inline void write_reg(uintptr_t addr, uint32_t value);
-inline uint32_t read_reg(uintptr_t addr);
-inline void spi_sendbyte(uint8_t byte);
-inline void waittx();
-inline void waitrx();
+// inline void write_reg(uintptr_t addr, uint32_t value);
+//inline uint32_t read_reg(uintptr_t addr);
+//inline void spi_sendbyte(uint8_t byte);
+//inline void waittx();
+//inline void waitrx();
 uint8_t spi_txrx(uint8_t byte);
-inline uint8_t spi_readbyte();
+//inline uint8_t spi_readbyte();
 uint64_t spi_read64();
 void spi_init();
 
+static inline void write_reg(uintptr_t addr, uint32_t value) {
+  volatile uint32_t * loc = (volatile uint32_t *) addr;
+  *loc = value;
+}
+
+// Read a register
+static inline uint32_t read_reg(uintptr_t addr) {
+  return *(volatile uint32_t *) addr;
+}
+
+// Queues a single byte in the transfer fifo
+static inline void spi_sendbyte(uint8_t byte) {
+  // Write byte to transfer fifo
+  write_reg(SPI_TXDATA, byte);
+}
+
+static inline void waittx() {
+  while(!(read_reg(SPI_IP) & 1)) {}
+}
+
+static inline void waitrx() {
+  while(read_reg(SPI_IP) & 2) {}
+}
+
+static inline uint8_t spi_readbyte() {
+  return read_reg(SPI_RXDATA);
+}
+
 #endif
diff --git a/fpga/zsbl/uart.c b/fpga/zsbl/uart.c
index a08690069..be3270e28 100644
--- a/fpga/zsbl/uart.c
+++ b/fpga/zsbl/uart.c
@@ -14,12 +14,12 @@ uint8_t read_reg_u8(uintptr_t addr)
 
 int is_transmit_empty()
 {
-    return read_reg_u8(UART_LINE_STATUS) & 0x20;
+    return read_reg_u8(UART_LSR) & 0x20;
 }
 
 int is_receive_empty()
 {
-    return !(read_reg_u8(UART_LINE_STATUS) & 0x1);
+    return !(read_reg_u8(UART_LSR) & 0x1);
 }
 
 void write_serial(char a)