diff --git a/sim/questa/wally.do b/sim/questa/wally.do
index ffb66d8bc..6be1610d2 100644
--- a/sim/questa/wally.do
+++ b/sim/questa/wally.do
@@ -192,7 +192,7 @@ if {$DEBUG > 0} {
 # suppress spurious warnngs about
 # "Extra checking for conflicts with always_comb done at vopt time"
 # because vsim will run vopt
-set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 +incdir+${FCRVVI}"
+set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 +incdir+${FCRVVI}/common +incdir+${FCRVVI}"
 set SOURCES "${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv"
 vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${FCdefineCOVER_EXTS} {*}${lockstepvlog} ${FCdefineRVVI_COVERAGE} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286
 
diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv
index f8818032d..d6ba31083 100644
--- a/testbench/common/wallyTracer.sv
+++ b/testbench/common/wallyTracer.sv
@@ -80,16 +80,6 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   assign InstrValidE    = testbench.dut.core.ieu.c.InstrValidE;
   assign InstrValidM    = testbench.dut.core.ieu.InstrValidM;
   assign InstrRawD      = testbench.dut.core.ifu.InstrRawD;
-  assign VAdrIM         = testbench.dut.core.ifu.immu.immu.tlb.tlb.VAdr;
-  assign VAdrDM         = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.VAdr;
-  assign PAIM           = testbench.dut.core.ifu.immu.immu.PhysicalAddress;
-  assign PADM           = testbench.dut.core.lsu.dmmu.dmmu.PhysicalAddress;
-  assign ReadAccessM    = testbench.dut.core.lsu.dmmu.dmmu.ReadAccessM;
-  assign WriteAccessM   = testbench.dut.core.lsu.dmmu.dmmu.WriteAccessM;
-  assign ExecuteAccessF = testbench.dut.core.ifu.immu.immu.ExecuteAccessF;
-  assign PTE_iM         = testbench.dut.core.ifu.immu.immu.PTE;
-  assign PTE_dM         = testbench.dut.core.lsu.dmmu.dmmu.PTE;
-  assign PPN_iM         = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN;
   assign PPN_dM         = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; 
   assign PCNextF        = testbench.dut.core.ifu.PCNextF;
   assign PCF            = testbench.dut.core.ifu.PCF;
@@ -113,6 +103,18 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   assign STATUS_UXL     = testbench.dut.core.priv.priv.csr.csrsr.STATUS_UXL;
   assign wfiM           = testbench.dut.core.priv.priv.wfiM;
   assign InterruptM     = testbench.dut.core.priv.priv.InterruptM;
+
+  //FOr VM Verification
+  assign VAdrIM         = testbench.dut.core.ifu.immu.immu.tlb.tlb.VAdr;
+  assign VAdrDM         = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.VAdr;
+  assign PAIM           = testbench.dut.core.ifu.immu.immu.PhysicalAddress;
+  assign PADM           = testbench.dut.core.lsu.dmmu.dmmu.PhysicalAddress;
+  assign ReadAccessM    = testbench.dut.core.lsu.dmmu.dmmu.ReadAccessM;
+  assign WriteAccessM   = testbench.dut.core.lsu.dmmu.dmmu.WriteAccessM;
+  assign ExecuteAccessF = testbench.dut.core.ifu.immu.immu.ExecuteAccessF;
+  assign PTE_iM         = testbench.dut.core.ifu.immu.immu.PTE;
+  assign PTE_dM         = testbench.dut.core.lsu.dmmu.dmmu.PTE;
+  assign PPN_iM         = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN;
   
 
   logic valid;