From 26fb09c86817e4408e555bdbe7a36da1a69d5566 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 9 Jan 2022 17:10:57 -0600 Subject: [PATCH] Added additional fsm to ILA. --- fpga/constraints/debug2.xdc | 14 ++++---------- pipelined/src/lsu/interlockfsm.sv | 2 +- 2 files changed, 5 insertions(+), 11 deletions(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 4c4aabe6e..8f4077b80 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -574,26 +574,20 @@ connect_debug_port u_ila_0/probe122 [get_nets [list {wallypipelinedsoc/hart/ifu/ create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe123] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe123] -connect_debug_port u_ila_0/probe123 [get_nets [list {wallypipelinedsoc/hart/ifu/busfsm/BusCurrState[0]} -{wallypipelinedsoc/hart/ifu/busfsm/BusCurrState[1]} -{wallypipelinedsoc/hart/ifu/busfsm/BusCurrState[2]} ]] +connect_debug_port u_ila_0/probe123 [get_nets [list {wallypipelinedsoc/hart/ifu/busfsm/BusCurrState[0]} {wallypipelinedsoc/hart/ifu/busfsm/BusCurrState[1]} {wallypipelinedsoc/hart/ifu/busfsm/BusCurrState[2]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe124] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe124] -connect_debug_port u_ila_0/probe124 [get_nets [list wallypipelinedsoc/hart/ifu/CurrState ]] +connect_debug_port u_ila_0/probe124 [get_nets [list wallypipelinedsoc/hart/ifu/SpillSupport.CurrState[0] ]] create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe125] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe125] -connect_debug_port u_ila_0/probe125 [get_nets [list {wallypipelinedsoc/hart/lsu/busfsm/BusCurrState[0]} -{wallypipelinedsoc/hart/lsu/busfsm/BusCurrState[1]} -{wallypipelinedsoc/hart/lsu/busfsm/BusCurrState[2]} ]] +connect_debug_port u_ila_0/probe125 [get_nets [list {wallypipelinedsoc/hart/lsu/busfsm/BusCurrState[0]} {wallypipelinedsoc/hart/lsu/busfsm/BusCurrState[1]} {wallypipelinedsoc/hart/lsu/busfsm/BusCurrState[2]} ]] create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe126] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe126] -connect_debug_port u_ila_0/probe126 [get_nets [list {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[0]} -{wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[1]} -{wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[2]} ]] +connect_debug_port u_ila_0/probe126 [get_nets [list {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[0]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[1]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[2]} ]] diff --git a/pipelined/src/lsu/interlockfsm.sv b/pipelined/src/lsu/interlockfsm.sv index abc5feef8..dd41a840e 100644 --- a/pipelined/src/lsu/interlockfsm.sv +++ b/pipelined/src/lsu/interlockfsm.sv @@ -55,7 +55,7 @@ module interlockfsm STATE_T5_ITLB_MISS, STATE_T7_DITLB_MISS} statetype; - statetype InterlockCurrState, InterlockNextState; +(* mark_debug = "true" *) statetype InterlockCurrState, InterlockNextState; always_ff @(posedge clk)