From 2752e5de4c61dc001231b75ed3260ba7adc2f051 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 19 Jul 2023 17:08:16 -0500 Subject: [PATCH] Fixed a bunch of timing constraints for the arty a7 board. --- fpga/constraints/constraints-ArtyA7.xdc | 28 +++---- fpga/constraints/small-debug.xdc | 84 +-------------------- fpga/generator/xlnx_mmcm.tcl | 2 +- fpga/src/fpgaTopArtyA7.v | 97 +++++++++++++------------ fpga/src/wallypipelinedsocwrapper.sv | 6 +- 5 files changed, 69 insertions(+), 148 deletions(-) diff --git a/fpga/constraints/constraints-ArtyA7.xdc b/fpga/constraints/constraints-ArtyA7.xdc index 8d8b991cd..b757107d9 100644 --- a/fpga/constraints/constraints-ArtyA7.xdc +++ b/fpga/constraints/constraints-ArtyA7.xdc @@ -3,7 +3,7 @@ # mmcm_clkout0 is the clock output of the DDR3 memory interface / 4. # This clock is not used by wally or the AHB Bus. However it is used by the AXI BUS on the DD3 IP. -create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O] +#create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O] ##### clock ##### set_property PACKAGE_PIN E3 [get_ports {default_100mhz_clk}] @@ -34,8 +34,8 @@ set_property IOSTANDARD LVCMOS33 [get_ports {GPO[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {GPO[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {GPO[0]}] set_max_delay -to [get_ports {GPO[*]}] 10.000 -set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 0.000 [get_ports {GPO[*]}] -set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [get_ports {GPO[*]}] +set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay -5.000 [get_ports {GPO[*]}] +set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay -5.000 [get_ports {GPO[*]}] ##### UART ##### @@ -94,17 +94,19 @@ set_property PULLUP true [get_ports {SDCDat[0]}] set_property PULLUP true [get_ports {SDCCmd}] -set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}] -set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 21.000 [get_ports {SDCDat[*]}] +set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.500 [get_ports {SDCDat[*]}] +set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 21.000 [get_ports {SDCDat[*]}] -set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCCmd}] -set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 14.000 [get_ports {SDCCmd}] +set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.500 [get_ports {SDCCmd}] +set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 14.000 [get_ports {SDCCmd}] -set_output_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.000 [get_ports {SDCCmd}] -set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_ports {SDCCmd}] +set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [get_ports {SDCCmd}] +set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 6.000 [get_ports {SDCCmd}] -set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK] +set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] 0.000 [get_ports SDCCLK] + +set_multicycle_path -from [get_pins xlnx_ddr3_c0/u_xlnx_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/init_calib_complete_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10 # ********************************* #set_property DCI_CASCADE {64} [get_iobanks 65] @@ -211,9 +213,3 @@ set_properity PACKAGE_PIN N5 [get_ports ddr3_cke[0]] set_properity PACKAGE_PIN R5 [get_ports ddr3_odt[0]] set_properity PACKAGE_PIN U8 [get_ports ddr3_cs_n[0]] - -# **** may have to bring this one back -#set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 20.000 - - -set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets wallypipelinedsoc/uncore.uncore/sdc.SDC/clockgater/CLK] diff --git a/fpga/constraints/small-debug.xdc b/fpga/constraints/small-debug.xdc index 2938c3ec0..28b7e69d5 100644 --- a/fpga/constraints/small-debug.xdc +++ b/fpga/constraints/small-debug.xdc @@ -49,89 +49,9 @@ set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] connect_debug_port u_ila_0/probe5 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHREADY ]] create_debug_port u_ila_0 probe -set_property port_width 28 [get_debug_ports u_ila_0/probe6] +set_property port_width 64 [get_debug_ports u_ila_0/probe6] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] -connect_debug_port u_ila_0/probe6 [get_nets [list {m_axi_araddr[0]} {m_axi_araddr[1]} {m_axi_araddr[2]} {m_axi_araddr[3]} {m_axi_araddr[4]} {m_axi_araddr[5]} {m_axi_araddr[6]} {m_axi_araddr[7]} {m_axi_araddr[8]} {m_axi_araddr[9]} {m_axi_araddr[10]} {m_axi_araddr[11]} {m_axi_araddr[12]} {m_axi_araddr[13]} {m_axi_araddr[14]} {m_axi_araddr[15]} {m_axi_araddr[16]} {m_axi_araddr[17]} {m_axi_araddr[18]} {m_axi_araddr[19]} {m_axi_araddr[20]} {m_axi_araddr[21]} {m_axi_araddr[22]} {m_axi_araddr[23]} {m_axi_araddr[24]} {m_axi_araddr[25]} {m_axi_araddr[26]} {m_axi_araddr[27]} ]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe7] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] -connect_debug_port u_ila_0/probe7 [get_nets [list {m_axi_arready}]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe8] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] -connect_debug_port u_ila_0/probe8 [get_nets [list {m_axi_arvalid}]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe9] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] -connect_debug_port u_ila_0/probe9 [get_nets [list {c0_init_calib_complete}]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe10] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] -connect_debug_port u_ila_0/probe10 [get_nets [list {ui_clk_sync_rst}]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe11] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] -connect_debug_port u_ila_0/probe11 [get_nets [list {mmcm_locked}]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe12] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] -connect_debug_port u_ila_0/probe12 [get_nets [list {m_axi_awvalid}]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe13] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] -connect_debug_port u_ila_0/probe13 [get_nets [list {m_axi_awready}]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe14] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] -connect_debug_port u_ila_0/probe14 [get_nets [list {BUS_axi_arvalid}]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe15] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] -connect_debug_port u_ila_0/probe15 [get_nets [list {BUS_axi_awready}]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe16] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] -connect_debug_port u_ila_0/probe16 [get_nets [list {BUS_axi_arvalid}]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe17] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] -connect_debug_port u_ila_0/probe17 [get_nets [list {BUS_axi_arready}]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe18] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] -connect_debug_port u_ila_0/probe18 [get_nets [list {BUS_axi_rvalid}]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe19] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19] -connect_debug_port u_ila_0/probe19 [get_nets [list {BUS_axi_rready}]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe20] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] -connect_debug_port u_ila_0/probe20 [get_nets [list {BUS_axi_wready}]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe21] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21] -connect_debug_port u_ila_0/probe21 [get_nets [list {BUS_axi_wvalid}]] - -create_debug_port u_ila_0 probe -set_property port_width 64 [get_debug_ports u_ila_0/probe22] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] -connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]] +connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]] # the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock. #connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk] diff --git a/fpga/generator/xlnx_mmcm.tcl b/fpga/generator/xlnx_mmcm.tcl index 0d1398470..66958c954 100644 --- a/fpga/generator/xlnx_mmcm.tcl +++ b/fpga/generator/xlnx_mmcm.tcl @@ -15,7 +15,7 @@ set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \ CONFIG.CLKOUT4_USED {false} \ CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \ CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \ - CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {15} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {17} \ CONFIG.CLKIN1_JITTER_PS {10.0} \ ] [get_ips $ipName] diff --git a/fpga/src/fpgaTopArtyA7.v b/fpga/src/fpgaTopArtyA7.v index 9b269455e..077b80952 100644 --- a/fpga/src/fpgaTopArtyA7.v +++ b/fpga/src/fpgaTopArtyA7.v @@ -70,8 +70,9 @@ module fpgaTop wire HREADYEXT; wire HRESPEXT; wire HSELEXT; - wire [31:0] HADDR; + wire [55:0] HADDR; wire [63:0] HWDATA; + wire [64/8-1:0] HWSTRB; wire HWRITE; wire [2:0] HSIZE; wire [2:0] HBURST; @@ -86,41 +87,41 @@ module fpgaTop wire SDCCmdOE; wire SDCCmdOut; -(* mark_debug = "true" *) wire [3:0] m_axi_awid; -(* mark_debug = "true" *) wire [7:0] m_axi_awlen; -(* mark_debug = "true" *) wire [2:0] m_axi_awsize; -(* mark_debug = "true" *) wire [1:0] m_axi_awburst; -(* mark_debug = "true" *) wire [3:0] m_axi_awcache; -(* mark_debug = "true" *) wire [31:0] m_axi_awaddr; -(* mark_debug = "true" *) wire [2:0] m_axi_awprot; -(* mark_debug = "true" *) wire m_axi_awvalid; -(* mark_debug = "true" *) wire m_axi_awready; -(* mark_debug = "true" *) wire m_axi_awlock; -(* mark_debug = "true" *) wire [63:0] m_axi_wdata; -(* mark_debug = "true" *) wire [7:0] m_axi_wstrb; -(* mark_debug = "true" *) wire m_axi_wlast; -(* mark_debug = "true" *) wire m_axi_wvalid; -(* mark_debug = "true" *) wire m_axi_wready; -(* mark_debug = "true" *) wire [3:0] m_axi_bid; -(* mark_debug = "true" *) wire [1:0] m_axi_bresp; -(* mark_debug = "true" *) wire m_axi_bvalid; -(* mark_debug = "true" *) wire m_axi_bready; -(* mark_debug = "true" *) wire [3:0] m_axi_arid; -(* mark_debug = "true" *) wire [7:0] m_axi_arlen; -(* mark_debug = "true" *) wire [2:0] m_axi_arsize; -(* mark_debug = "true" *) wire [1:0] m_axi_arburst; -(* mark_debug = "true" *) wire [2:0] m_axi_arprot; -(* mark_debug = "true" *) wire [3:0] m_axi_arcache; -(* mark_debug = "true" *) wire m_axi_arvalid; -(* mark_debug = "true" *) wire [31:0] m_axi_araddr; -(* mark_debug = "true" *) wire m_axi_arlock; -(* mark_debug = "true" *) wire m_axi_arready; -(* mark_debug = "true" *) wire [3:0] m_axi_rid; -(* mark_debug = "true" *) wire [63:0] m_axi_rdata; -(* mark_debug = "true" *) wire [1:0] m_axi_rresp; -(* mark_debug = "true" *) wire m_axi_rvalid; -(* mark_debug = "true" *) wire m_axi_rlast; -(* mark_debug = "true" *) wire m_axi_rready; + wire [3:0] m_axi_awid; + wire [7:0] m_axi_awlen; + wire [2:0] m_axi_awsize; + wire [1:0] m_axi_awburst; + wire [3:0] m_axi_awcache; + wire [31:0] m_axi_awaddr; + wire [2:0] m_axi_awprot; + wire m_axi_awvalid; + wire m_axi_awready; + wire m_axi_awlock; + wire [63:0] m_axi_wdata; + wire [7:0] m_axi_wstrb; + wire m_axi_wlast; + wire m_axi_wvalid; + wire m_axi_wready; + wire [3:0] m_axi_bid; + wire [1:0] m_axi_bresp; + wire m_axi_bvalid; + wire m_axi_bready; + wire [3:0] m_axi_arid; + wire [7:0] m_axi_arlen; + wire [2:0] m_axi_arsize; + wire [1:0] m_axi_arburst; + wire [2:0] m_axi_arprot; + wire [3:0] m_axi_arcache; + wire m_axi_arvalid; + wire [31:0] m_axi_araddr; + wire m_axi_arlock; + wire m_axi_arready; + wire [3:0] m_axi_rid; + wire [63:0] m_axi_rdata; + wire [1:0] m_axi_rresp; + wire m_axi_rvalid; + wire m_axi_rlast; + wire m_axi_rready; wire [3:0] BUS_axi_arregion; wire [3:0] BUS_axi_arqos; @@ -134,14 +135,14 @@ module fpgaTop wire [3:0] BUS_axi_awcache; wire [30:0] BUS_axi_awaddr; wire [2:0] BUS_axi_awprot; - (* mark_debug = "true" *) wire BUS_axi_awvalid; - (* mark_debug = "true" *) wire BUS_axi_awready; + wire BUS_axi_awvalid; + wire BUS_axi_awready; wire BUS_axi_awlock; wire [63:0] BUS_axi_wdata; wire [7:0] BUS_axi_wstrb; wire BUS_axi_wlast; - (* mark_debug = "true" *) wire BUS_axi_wvalid; - (* mark_debug = "true" *) wire BUS_axi_wready; + wire BUS_axi_wvalid; + wire BUS_axi_wready; wire [3:0] BUS_axi_bid; wire [1:0] BUS_axi_bresp; wire BUS_axi_bvalid; @@ -152,16 +153,16 @@ module fpgaTop wire [1:0] BUS_axi_arburst; wire [2:0] BUS_axi_arprot; wire [3:0] BUS_axi_arcache; - (* mark_debug = "true" *) wire BUS_axi_arvalid; + wire BUS_axi_arvalid; wire [30:0] BUS_axi_araddr; wire BUS_axi_arlock; - (* mark_debug = "true" *) wire BUS_axi_arready; + wire BUS_axi_arready; wire [3:0] BUS_axi_rid; wire [63:0] BUS_axi_rdata; - (* mark_debug = "true" *) wire [1:0] BUS_axi_rresp; - (* mark_debug = "true" *) wire BUS_axi_rvalid; + wire [1:0] BUS_axi_rresp; + wire BUS_axi_rvalid; wire BUS_axi_rlast; - (* mark_debug = "true" *) wire BUS_axi_rready; + wire BUS_axi_rready; wire BUSCLK; @@ -226,6 +227,7 @@ module fpgaTop wallypipelinedsocwrapper wallypipelinedsocwrapper (.clk(CPUCLK), .reset_ext(bus_struct_reset), + .reset(), // bus interface .HRDATAEXT(HRDATAEXT), .HREADYEXT(HREADYEXT), @@ -235,6 +237,7 @@ module fpgaTop .HRESETn(HRESETnOpen), // open .HADDR(HADDR), .HWDATA(HWDATA), + .HWSTRB(HWSTRB), .HWRITE(HWRITE), .HSIZE(HSIZE), .HBURST(HBURST), @@ -242,6 +245,8 @@ module fpgaTop .HTRANS(HTRANS), .HMASTLOCK(HMASTLOCK), .HREADY(HREADY), + // MTIME + .TIMECLK(1'b0), // GPIO .GPIOIN(GPIOIN), .GPIOOUT(GPIOOUT), @@ -261,7 +266,7 @@ module fpgaTop (.s_ahb_hclk(CPUCLK), .s_ahb_hresetn(peripheral_aresetn), .s_ahb_hsel(HSELEXT), - .s_ahb_haddr(HADDR), + .s_ahb_haddr(HADDR[31:0]), .s_ahb_hprot(HPROT), .s_ahb_htrans(HTRANS), .s_ahb_hsize(HSIZE), diff --git a/fpga/src/wallypipelinedsocwrapper.sv b/fpga/src/wallypipelinedsocwrapper.sv index f62a9bdbd..d34e3bc87 100644 --- a/fpga/src/wallypipelinedsocwrapper.sv +++ b/fpga/src/wallypipelinedsocwrapper.sv @@ -40,9 +40,9 @@ module wallypipelinedsocwrapper ( output logic HSELEXT, // outputs to external memory, shared with uncore memory output logic HCLK, HRESETn, - output logic [64-1:0] HADDR, - output logic [64-1:0] HWDATA, - output logic [64/8-1:0] HWSTRB, + output logic [55:0] HADDR, + output logic [64-1:0] HWDATA, + output logic [64/8-1:0] HWSTRB, output logic HWRITE, output logic [2:0] HSIZE, output logic [2:0] HBURST,