From 293cc88bd9467b42d63f86d9da7a6005c4fc82f2 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Mon, 23 Jan 2023 17:00:24 -0600 Subject: [PATCH] Added extra core signal to mark_debug.txt. Modified wally.tcl --- fpga/constraints/marked_debug.txt | 1 + fpga/generator/wally.tcl | 5 ++++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/fpga/constraints/marked_debug.txt b/fpga/constraints/marked_debug.txt index 97ac1ead3..ff0fb325c 100644 --- a/fpga/constraints/marked_debug.txt +++ b/fpga/constraints/marked_debug.txt @@ -30,6 +30,7 @@ wally/wallypipelinedcore.sv: logic MemRWM wally/wallypipelinedcore.sv: logic InstrValidM wally/wallypipelinedcore.sv: logic WriteDataM wally/wallypipelinedcore.sv: logic IEUAdrM +wally/wallypipelinedcore.sv: logic HRDATA ifu/spill.sv: statetype CurrState ifu/ifu.sv: logic IFUStallF ifu/ifu.sv: logic IFUHADDR diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index 5cac00f5a..e0de591b7 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -19,7 +19,7 @@ read_ip IP/xlnx_axi_crossbar.srcs/sources_1/ip/xlnx_axi_crossbar/xlnx_axi_crossb read_ip IP/xlnx_axi_dwidth_conv_32to64.srcs/sources_1/ip/xlnx_axi_dwidth_conv_32to64/xlnx_axi_dwidth_conv_32to64.xci read_ip IP/xlnx_axi_dwidth_conv_64to32.srcs/sources_1/ip/xlnx_axi_dwidth_conv_64to32/xlnx_axi_dwidth_conv_64to32.xci -read_verilog -sv [glob -type f ../../pipelined/src/*/*.sv ../../pipelined/src/*/*/*.sv] +# read_verilog -sv [glob -type f ../../pipelined/src/*/*.sv ../../pipelined/src/*/*/*.sv] read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv] read_verilog [glob -type f ../../pipelined/src/uncore/newsdc/*.v] read_verilog {../src/fpgaTop.v} @@ -47,6 +47,9 @@ synth_design -rtl -name rtl_1 report_clocks -file reports/clocks.rpt +# Temp +set_param messaging.defaultLimit 100000 + # this does synthesis? wtf? launch_runs synth_1 -jobs 4