diff --git a/fpga/constraints/debug4.xdc b/fpga/constraints/debug4.xdc
index f26ce6c91..e8a7e061f 100644
--- a/fpga/constraints/debug4.xdc
+++ b/fpga/constraints/debug4.xdc
@@ -107,9 +107,9 @@ connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsocwrapper/wal
 
 
 create_debug_port u_ila_0 probe
-set_property port_width 63 [get_debug_ports u_ila_0/probe20]
+set_property port_width 64 [get_debug_ports u_ila_0/probe20]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
-connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[63]} ]]
+connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[63]} ]]
 
 
 create_debug_port u_ila_0 probe
diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile
index f481e2c81..2a1d4a60e 100644
--- a/fpga/generator/Makefile
+++ b/fpga/generator/Makefile
@@ -6,20 +6,20 @@ dst := IP
 #export board := vcu118
 
 # vcu108
-#export XILINX_PART := xcvu095-ffva2104-2-e
-#export XILINX_BOARD := xilinx.com:vcu108:part0:1.2
-#export board := vcu108
+export XILINX_PART := xcvu095-ffva2104-2-e
+export XILINX_BOARD := xilinx.com:vcu108:part0:1.2
+export board := vcu108
 
 # Arty A7
-export XILINX_PART := xc7a100tcsg324-1
-export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
-export board := ArtyA7
+# export XILINX_PART := xc7a100tcsg324-1
+# export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
+# export board := ArtyA7
 
 # for Arty A7 and S7 boards
-all: FPGA_Arty
+# all: FPGA_Arty
 
 # VCU 108 and VCU 118 boards
-#all: FPGA_VCU
+all: FPGA_VCU
 
 FPGA_Arty: PreProcessFiles IP_Arty
 	vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl
index 32baade79..f28825fae 100644
--- a/fpga/generator/wally.tcl
+++ b/fpga/generator/wally.tcl
@@ -96,7 +96,7 @@ if {$board=="ArtyA7"} {
     source ../constraints/small-debug.xdc
 
 } else {
-    #source ../constraints/vcu-small-debug.xdc
+    # source ../constraints/vcu-small-debug.xdc
     source ../constraints/debug4.xdc
 }
 
diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v
index 43cbb1a8b..6038bb677 100644
--- a/fpga/src/fpgaTop.v
+++ b/fpga/src/fpgaTop.v
@@ -95,41 +95,41 @@ module fpgaTop
   // wire 			   SDCCmdOE;
   // wire 			   SDCCmdOut;
 
- wire [3:0] 	   m_axi_awid;
- wire [7:0] 	   m_axi_awlen;
- wire [2:0] 	   m_axi_awsize;
- wire [1:0] 	   m_axi_awburst;
- wire [3:0] 	   m_axi_awcache;
- wire [31:0] 	   m_axi_awaddr;
- wire [2:0] 	   m_axi_awprot;
- wire 		   m_axi_awvalid;
- wire 		   m_axi_awready;
- wire 		   m_axi_awlock;
- wire [63:0] 	   m_axi_wdata;
- wire [7:0] 	   m_axi_wstrb;
- wire 		   m_axi_wlast;
- wire 		   m_axi_wvalid;
- wire 		   m_axi_wready;
- wire [3:0] 	   m_axi_bid;
- wire [1:0] 	   m_axi_bresp;
- wire 		   m_axi_bvalid;
- wire 		   m_axi_bready;
- wire [3:0] 	   m_axi_arid;
- wire [7:0] 	   m_axi_arlen;
- wire [2:0] 	   m_axi_arsize;
- wire [1:0] 	   m_axi_arburst;
- wire [2:0] 	   m_axi_arprot;
- wire [3:0] 	   m_axi_arcache;
- wire 		   m_axi_arvalid;
- wire [31:0] 	   m_axi_araddr;
- wire 			   m_axi_arlock;
- wire 		   m_axi_arready;
- wire [3:0] 	   m_axi_rid;
- wire [63:0] 	   m_axi_rdata;
- wire [1:0] 	   m_axi_rresp;
- wire 		   m_axi_rvalid;
- wire 		   m_axi_rlast;
- wire 		   m_axi_rready;
+ (* mark_debug = "true" *)wire [3:0] 	   m_axi_awid;
+ (* mark_debug = "true" *)wire [7:0] 	   m_axi_awlen;
+ (* mark_debug = "true" *)wire [2:0] 	   m_axi_awsize;
+ (* mark_debug = "true" *)wire [1:0] 	   m_axi_awburst;
+ (* mark_debug = "true" *)wire [3:0] 	   m_axi_awcache;
+ (* mark_debug = "true" *)wire [31:0] 	   m_axi_awaddr;
+ (* mark_debug = "true" *)wire [2:0] 	   m_axi_awprot;
+ (* mark_debug = "true" *)wire 		   m_axi_awvalid;
+ (* mark_debug = "true" *)wire 		   m_axi_awready;
+ (* mark_debug = "true" *)wire 		   m_axi_awlock;
+ (* mark_debug = "true" *)wire [63:0] 	   m_axi_wdata;
+ (* mark_debug = "true" *)wire [7:0] 	   m_axi_wstrb;
+ (* mark_debug = "true" *)wire 		   m_axi_wlast;
+ (* mark_debug = "true" *)wire 		   m_axi_wvalid;
+ (* mark_debug = "true" *)wire 		   m_axi_wready;
+ (* mark_debug = "true" *)wire [3:0] 	   m_axi_bid;
+ (* mark_debug = "true" *)wire [1:0] 	   m_axi_bresp;
+ (* mark_debug = "true" *)wire 		   m_axi_bvalid;
+ (* mark_debug = "true" *)wire 		   m_axi_bready;
+ (* mark_debug = "true" *)wire [3:0] 	   m_axi_arid;
+ (* mark_debug = "true" *)wire [7:0] 	   m_axi_arlen;
+ (* mark_debug = "true" *)wire [2:0] 	   m_axi_arsize;
+ (* mark_debug = "true" *)wire [1:0] 	   m_axi_arburst;
+ (* mark_debug = "true" *)wire [2:0] 	   m_axi_arprot;
+ (* mark_debug = "true" *)wire [3:0] 	   m_axi_arcache;
+ (* mark_debug = "true" *)wire 		   m_axi_arvalid;
+ (* mark_debug = "true" *)wire [31:0] 	   m_axi_araddr;
+ (* mark_debug = "true" *)wire 			   m_axi_arlock;
+ (* mark_debug = "true" *)wire 		   m_axi_arready;
+ (* mark_debug = "true" *)wire [3:0] 	   m_axi_rid;
+ (* mark_debug = "true" *)wire [63:0] 	   m_axi_rdata;
+ (* mark_debug = "true" *)wire [1:0] 	   m_axi_rresp;
+ (* mark_debug = "true" *)wire 		   m_axi_rvalid;
+ (* mark_debug = "true" *)wire 		   m_axi_rlast;
+ (* mark_debug = "true" *)wire 		   m_axi_rready;
 
   // Extra Bus signals
   wire [3:0] 	   BUS_axi_arregion;
diff --git a/linux/buildroot-scripts/Makefile b/linux/buildroot-scripts/Makefile
index d8da7092f..6cb7f8f37 100644
--- a/linux/buildroot-scripts/Makefile
+++ b/linux/buildroot-scripts/Makefile
@@ -1,4 +1,4 @@
-BUILDROOT := ${RISCV}/buildroot
+BUILDROOT := ${RISCV}/buildroot2023
 IMAGES := ${BUILDROOT}/output/images
 DIS := ${IMAGES}/disassembly
 
diff --git a/linux/sdcard/flash-sd.sh b/linux/sdcard/flash-sd.sh
index d57347698..c1dd360da 100755
--- a/linux/sdcard/flash-sd.sh
+++ b/linux/sdcard/flash-sd.sh
@@ -24,7 +24,14 @@ DEVICE_TREE=$IMAGES/wally-vcu108.dtb
 MNT_DIR=wallyimg
 
 # Usage function
-usage() { echo "Usage: $0 [-z] [-b <path/to/buildroot>] <device>" 1>&2; exit 1; }
+usage() { echo "Usage: $0 [-zh] [-b <path/to/buildroot>] <device>" 1>&2; exit 1; }
+
+help() {
+    echo "Usage: $0 [OPTIONS] <device>"
+    echo "  -z                          wipes card with zeros"
+    echo "  -b <path/to/buildroot>      get images from given buildroot"
+    exit 0;
+}
 
 # Process options and arguments. The following code grabs the single
 # sdcard device argument no matter where it is in the positional
@@ -33,7 +40,7 @@ ARGS=()
 while [ $OPTIND -le "$#" ] ; do
     if getopts "hzb:" arg ; then
         case "${arg}" in
-            h) usage
+            h) help
                ;;
             z) WIPECARD=y
                ;;
diff --git a/linux/sdcard/make-img.sh b/linux/sdcard/make-img.sh
index a635d04db..12a9084d4 100755
--- a/linux/sdcard/make-img.sh
+++ b/linux/sdcard/make-img.sh
@@ -68,12 +68,19 @@ if [ ! -e $1 ] ; then
     #      --new=3:$FS_START:-0 --change-name=3:'filesystem' \
     #      $1
 
+    # echo -e "$NAME: Creating GUID Partition Table"
+    # sudo sgdisk -g --clear --set-alignment=1 \
+    #      --new=1:34:+$DST_SIZE: --change-name=1:'fdt' \
+    #      --new=2:$FW_JUMP_START:+$FW_JUMP_SIZE --change-name=2:'opensbi' --typecode=1:2E54B353-1271-4842-806F-E436D6AF6985 \
+    #      --new=3:$KERNEL_START:+$KERNEL_SIZE --change-name=3:'kernel' \
+    #      --new=4:$FS_START:-0 --change-name=4:'filesystem' \
+    #      $1
+
     echo -e "$NAME: Creating GUID Partition Table"
     sudo sgdisk -g --clear --set-alignment=1 \
          --new=1:34:+$DST_SIZE: --change-name=1:'fdt' \
          --new=2:$FW_JUMP_START:+$FW_JUMP_SIZE --change-name=2:'opensbi' --typecode=1:2E54B353-1271-4842-806F-E436D6AF6985 \
          --new=3:$KERNEL_START:+$KERNEL_SIZE --change-name=3:'kernel' \
-         --new=4:$FS_START:-0 --change-name=4:'filesystem' \
          $1
 
     LOOPDEVICE=$(sudo losetup -f)
@@ -94,14 +101,14 @@ if [ ! -e $1 ] ; then
     echo -e "$NAME: Copying Kernel"
     sudo dd if=$LINUX_KERNEL of="$LOOPDEVICE"p3 $DD_FLAGS
 
-    sudo mkfs.ext4 "$LOOPDEVICE"p4
-    sudo mkdir /mnt/$MNT_DIR
+    # sudo mkfs.ext4 "$LOOPDEVICE"p4
+    # sudo mkdir /mnt/$MNT_DIR
 
-    sudo mount -v "$LOOPDEVICE"p4 /mnt/$MNT_DIR 
+    # sudo mount -v "$LOOPDEVICE"p4 /mnt/$MNT_DIR 
 
-    sudo umount -v /mnt/$MNT_DIR
+    # sudo umount -v /mnt/$MNT_DIR
 
-    sudo rmdir /mnt/$MNT_DIR
+    # sudo rmdir /mnt/$MNT_DIR
     sudo losetup -d $LOOPDEVICE
 fi
 
diff --git a/linux/testvector-generation/genInitMem.sh b/linux/testvector-generation/genInitMem.sh
index b48a64896..c78485958 100755
--- a/linux/testvector-generation/genInitMem.sh
+++ b/linux/testvector-generation/genInitMem.sh
@@ -1,6 +1,6 @@
 #!/bin/bash
 tcpPort=1235
-imageDir=/home/ross/repos/buildroot/output/images
+imageDir=/home/jpease/repos/buildroot3/output/images
 tvDir=linux-testvectors
 rawRamFile="$tvDir/ramGDB.bin"
 ramFile="$tvDir/ram.bin"
@@ -36,7 +36,7 @@ then
 
     echo "Launching QEMU in replay mode!"
     (qemu-system-riscv64 \
-    -M virt -dtb /home/ross/repos/buildroot/output/images/wally-artya7.dtb \
+    -M virt -dtb /home/jpease/repos/buildroot3/output/images/wally-artya7.dtb \
     -nographic \
     -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \
     -gdb tcp::$tcpPort -S) \