From 017b3e987237a35fe5d0fa573a4c8d46769c9217 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 13 Nov 2024 17:01:01 -0800 Subject: [PATCH 01/42] Fix 32 bit CSRs in wallyTracer --- testbench/common/wallyTracer.sv | 31 +++++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 83eeacf5f..991f6719e 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -158,7 +158,6 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); end CSRArray[12'h300] = testbench.dut.core.priv.priv.csr.csrm.MSTATUS_REGW; - CSRArray[12'h310] = testbench.dut.core.priv.priv.csr.csrm.MSTATUSH_REGW; CSRArray[12'h305] = testbench.dut.core.priv.priv.csr.csrm.MTVEC_REGW; CSRArray[12'h341] = testbench.dut.core.priv.priv.csr.csrm.MEPC_REGW; CSRArray[12'h306] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW; @@ -215,7 +214,6 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); CSRArray[csrid] = CSRArrayOld[csrid]; CSRArray[12'h300] = CSRArrayOld[12'h300]; - CSRArray[12'h310] = CSRArrayOld[12'h310]; CSRArray[12'h305] = CSRArrayOld[12'h305]; CSRArray[12'h341] = CSRArrayOld[12'h341]; CSRArray[12'h306] = CSRArrayOld[12'h306]; @@ -255,6 +253,11 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); CSRArray[12'h001] = CSRArrayOld[12'h001]; CSRArray[12'h002] = CSRArrayOld[12'h002]; CSRArray[12'h003] = CSRArrayOld[12'h003]; + if (P.XLEN == 32) begin + CSRArray[12'h310] = CSRArrayOld[12'h310]; + CSRArray[12'h31A] = CSRArrayOld[12'h31A]; + CSRArray[12'h15D] = CSRArrayOld[12'h15D]; + end end end @@ -347,7 +350,6 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); integer index4; always_ff @(posedge clk) begin CSRArrayOld[12'h300] = CSRArray[12'h300]; - CSRArrayOld[12'h310] = CSRArray[12'h310]; CSRArrayOld[12'h305] = CSRArray[12'h305]; CSRArrayOld[12'h341] = CSRArray[12'h341]; CSRArrayOld[12'h306] = CSRArray[12'h306]; @@ -387,6 +389,11 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); CSRArrayOld[12'h001] = CSRArray[12'h001]; CSRArrayOld[12'h002] = CSRArray[12'h002]; CSRArrayOld[12'h003] = CSRArray[12'h003]; + if (P.XLEN == 32) begin + CSRArrayOld[12'h310] = CSRArray[12'h310]; + CSRArrayOld[12'h31A] = CSRArray[12'h31A]; + CSRArrayOld[12'h15D] = CSRArray[12'h15D]; + end // PMP CFG 3A0 to 3AF for(index4='h3A0; index4<='h3AF; index4++) @@ -399,7 +406,6 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); // check for csr value change. assign CSR_W[12'h300] = (CSRArrayOld[12'h300] != CSRArray[12'h300]) ? 1 : 0; - assign CSR_W[12'h310] = (CSRArrayOld[12'h310] != CSRArray[12'h310]) ? 1 : 0; assign CSR_W[12'h305] = (CSRArrayOld[12'h305] != CSRArray[12'h305]) ? 1 : 0; assign CSR_W[12'h341] = (CSRArrayOld[12'h341] != CSRArray[12'h341]) ? 1 : 0; assign CSR_W[12'h306] = (CSRArrayOld[12'h306] != CSRArray[12'h306]) ? 1 : 0; @@ -436,9 +442,13 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign CSR_W[12'h001] = (CSRArrayOld[12'h001] != CSRArray[12'h001]) ? 1 : 0; assign CSR_W[12'h002] = (CSRArrayOld[12'h002] != CSRArray[12'h002]) ? 1 : 0; assign CSR_W[12'h003] = (CSRArrayOld[12'h003] != CSRArray[12'h003]) ? 1 : 0; + if (P.XLEN == 32) begin + assign CSR_W[12'h310] = (CSRArrayOld[12'h310] != CSRArray[12'h310]) ? 1 : 0; + assign CSR_W[12'h31A] = (CSRArrayOld[12'h31A] != CSRArray[12'h31A]) ? 1 : 0; + assign CSR_W[12'h15D] = (CSRArrayOld[12'h15D] != CSRArray[12'h15D]) ? 1 : 0; + end assign rvvi.csr_wb[0][0][12'h300] = CSR_W[12'h300]; - assign rvvi.csr_wb[0][0][12'h310] = CSR_W[12'h310]; assign rvvi.csr_wb[0][0][12'h305] = CSR_W[12'h305]; assign rvvi.csr_wb[0][0][12'h341] = CSR_W[12'h341]; assign rvvi.csr_wb[0][0][12'h306] = CSR_W[12'h306]; @@ -475,9 +485,13 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign rvvi.csr_wb[0][0][12'h001] = CSR_W[12'h001]; assign rvvi.csr_wb[0][0][12'h002] = CSR_W[12'h002]; assign rvvi.csr_wb[0][0][12'h003] = CSR_W[12'h003]; + if (P.XLEN == 32) begin + assign rvvi.csr_wb[0][0][12'h310] = CSR_W[12'h310]; + assign rvvi.csr_wb[0][0][12'h31A] = CSR_W[12'h31A]; + assign rvvi.csr_wb[0][0][12'h15D] = CSR_W[12'h15D]; + end assign rvvi.csr[0][0][12'h300] = CSRArray[12'h300]; - assign rvvi.csr[0][0][12'h310] = CSRArray[12'h310]; assign rvvi.csr[0][0][12'h305] = CSRArray[12'h305]; assign rvvi.csr[0][0][12'h341] = CSRArray[12'h341]; assign rvvi.csr[0][0][12'h306] = CSRArray[12'h306]; @@ -514,6 +528,11 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign rvvi.csr[0][0][12'h001] = CSRArray[12'h001]; assign rvvi.csr[0][0][12'h002] = CSRArray[12'h002]; assign rvvi.csr[0][0][12'h003] = CSRArray[12'h003]; + if (P.XLEN == 32) begin + assign rvvi.csr[0][0][12'h310] = CSRArray[12'h310]; + assign rvvi.csr[0][0][12'h31A] = CSRArray[12'h31A]; + assign rvvi.csr[0][0][12'h15D] = CSRArray[12'h15D]; + end // PMP CFG 3A0 to 3AF for(index='h3A0; index<='h3AF; index++) begin From d666a0dd7b1c2faa7b02664049d9200ed9f8bb03 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 13 Nov 2024 18:26:53 -0800 Subject: [PATCH 02/42] Update formatting in an attempt to understand what's happening in this file --- testbench/common/wallyTracer.sv | 388 ++++++++++++++++---------------- 1 file changed, 193 insertions(+), 195 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 991f6719e..b4089f70b 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -35,37 +35,36 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); localparam NUMREGS = P.E_SUPPORTED ? 16 : 32; // wally specific signals - logic reset; - logic clk; - logic InstrValidD, InstrValidE; - logic StallF, StallD; - logic STATUS_SXL, STATUS_UXL; - logic [P.XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, PCW; - logic [31:0] InstrRawD, InstrRawE, InstrRawM, InstrRawW; - logic InstrValidM, InstrValidW; - logic StallE, StallM, StallW; - logic FlushD, FlushE, FlushM, FlushW; - logic TrapM, TrapW; - logic HaltM, HaltW; - logic [1:0] PrivilegeModeW; - logic [P.XLEN-1:0] rf[NUMREGS]; - logic [NUMREGS-1:0] rf_wb; - logic [4:0] rf_a3; - logic rf_we3; - logic [P.FLEN-1:0] frf[32]; - logic [`NUM_REGS-1:0] frf_wb; - logic [4:0] frf_a4; - logic frf_we4; - logic [P.XLEN-1:0] CSRArray [4095:0]; - logic [P.XLEN-1:0] CSRArrayOld [4095:0]; - logic [`NUM_CSRS-1:0] CSR_W; - logic CSRWriteM, CSRWriteW; - logic [11:0] CSRAdrM, CSRAdrW; - logic wfiM; - logic InterruptM, InterruptW; + logic reset; + logic clk; + logic InstrValidD, InstrValidE; + logic StallF, StallD; + logic STATUS_SXL, STATUS_UXL; + logic [P.XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, PCW; + logic [31:0] InstrRawD, InstrRawE, InstrRawM, InstrRawW; + logic InstrValidM, InstrValidW; + logic StallE, StallM, StallW; + logic FlushD, FlushE, FlushM, FlushW; + logic TrapM, TrapW; + logic HaltM, HaltW; + logic [1:0] PrivilegeModeW; + logic [P.XLEN-1:0] rf[NUMREGS]; + logic [NUMREGS-1:0] rf_wb; + logic [4:0] rf_a3; + logic rf_we3; + logic [P.FLEN-1:0] frf[32]; + logic [`NUM_REGS-1:0] frf_wb; + logic [4:0] frf_a4; + logic frf_we4; + logic [P.XLEN-1:0] CSRArray [4095:0]; + logic [P.XLEN-1:0] CSRArrayOld [4095:0]; + logic [`NUM_CSRS-1:0] CSR_W; + logic CSRWriteM, CSRWriteW; + logic [11:0] CSRAdrM, CSRAdrW; + logic wfiM; + logic InterruptM, InterruptW; //For VM Verification - logic [(P.XLEN-1):0] VAdrIM,VAdrDM,VAdrIW,VAdrDW; logic [(P.XLEN-1):0] PTE_iM,PTE_dM,PTE_iW,PTE_dW; logic [(P.PA_BITS-1):0] PAIM,PADM,PAIW,PADW; @@ -73,7 +72,6 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); logic ReadAccessM,WriteAccessM,ReadAccessW,WriteAccessW; logic ExecuteAccessF,ExecuteAccessD,ExecuteAccessE,ExecuteAccessM,ExecuteAccessW; - assign clk = testbench.dut.clk; // assign InstrValidF = testbench.dut.core.ieu.InstrValidF; // not needed yet assign InstrValidD = testbench.dut.core.ieu.c.InstrValidD; @@ -103,7 +101,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign wfiM = testbench.dut.core.priv.priv.wfiM; assign InterruptM = testbench.dut.core.priv.priv.InterruptM; - //FOr VM Verification + //For VM Verification assign VAdrIM = testbench.dut.core.ifu.immu.immu.tlb.tlb.VAdr; assign VAdrDM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.VAdr; assign PAIM = testbench.dut.core.ifu.immu.immu.PhysicalAddress; @@ -116,21 +114,17 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign PPN_iM = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN; assign PPN_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; - - logic valid; int csrid; always_comb begin - // Since we are detected the CSR change by comparing the old value we need to - // ensure the CSR is detected when the pipeline's Writeback stage is not - // stalled. If it is stalled we want CSRArray to hold the old value. - if(valid) begin - // machine CSRs - // *** missing PMP and performance counters. - + // Since we are detected the CSR change by comparing the old value we need to + // ensure the CSR is detected when the pipeline's Writeback stage is not + // stalled. If it is stalled we want CSRArray to hold the old value. + if(valid) begin + // machine CSRs // PMPCFG space is 0-15 3a0 - 3af - int i, i4, i8, csrid; + int i, i4, i8, csrid; logic [P.XLEN-1:0] pmp; for (i=0; i Date: Wed, 13 Nov 2024 22:12:11 -0800 Subject: [PATCH 03/42] pmps working for RVVI in RV32 --- testbench/common/wallyTracer.sv | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index b4089f70b..b4bf68a36 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -124,11 +124,13 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); if(valid) begin // machine CSRs // PMPCFG space is 0-15 3a0 - 3af + int inc = P.XLEN == 32 ? 4 : 8; int i, i4, i8, csrid; logic [P.XLEN-1:0] pmp; - for (i=0; i Date: Thu, 14 Nov 2024 06:26:28 -0800 Subject: [PATCH 04/42] incorportated Zicsr to run in Imperas --- config/rv32gc/coverage.svh | 1 + config/rv64gc/coverage.svh | 1 + 2 files changed, 2 insertions(+) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index 39e174412..776f8ef9f 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -26,6 +26,7 @@ `include "RV32ZcbZbb_coverage.svh" `include "RV32Zcf_coverage.svh" `include "RV32Zcd_coverage.svh" +`include "RV32Zicsr_coverage.svh" // Privileged extensions `include "ZicsrM_coverage.svh" diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index 0ab6f76a7..b7c83483a 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -26,6 +26,7 @@ `include "RV64ZcbZbb_coverage.svh" `include "RV64ZcbZba_coverage.svh" `include "RV64Zcd_coverage.svh" +`include "RV64Zicsr_coverage.svh" // Privileged extensions `include "RV64VM_coverage.svh" From 61c5d035e9cf3f6e6bebb24598867e767a993a2c Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 14 Nov 2024 15:03:13 -0800 Subject: [PATCH 05/42] Add mseccfg shell to wallyTracer and reformat CSRs --- testbench/common/wallyTracer.sv | 453 ++++++++++++++++++++------------ 1 file changed, 290 insertions(+), 163 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index b4bf68a36..7f8e43cdd 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -122,8 +122,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); // ensure the CSR is detected when the pipeline's Writeback stage is not // stalled. If it is stalled we want CSRArray to hold the old value. if(valid) begin - // machine CSRs - // PMPCFG space is 0-15 3a0 - 3af + // PMPCFG CSRs (space is 0-15 3a0 - 3af) int inc = P.XLEN == 32 ? 4 : 8; int i, i4, i8, csrid; logic [P.XLEN-1:0] pmp; @@ -145,7 +144,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); CSRArray[csrid] = pmp; end - // PMPADDR space is 0-63 3b0 - 3ef + // PMPADDR CSRs (space is 0-63 3b0 - 3ef) for (i=0; i Date: Thu, 14 Nov 2024 15:31:10 -0800 Subject: [PATCH 06/42] Fix wallyTracer bug --- testbench/common/wallyTracer.sv | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 21c72fec9..e2be8c7df 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -525,6 +525,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); end + // M-mode trap CSRs assign rvvi.csr_wb[0][0][12'h300] = CSR_W[12'h300]; assign rvvi.csr_wb[0][0][12'h302] = CSR_W[12'h302]; @@ -593,7 +594,6 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); - // M-mode trap CSRs assign rvvi.csr[0][0][12'h300] = CSRArray[12'h300]; assign rvvi.csr[0][0][12'h302] = CSRArray[12'h302]; @@ -660,7 +660,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign rvvi.csr[0][0][12'h15D] = CSRArray[12'h15D]; end - + // PMP CFG 3A0 to 3AF for(index='h3A0; index<='h3AF; index++) begin assign CSR_W[index] = (CSRArrayOld[index] != CSRArray[index]) ? 1 : 0; @@ -735,11 +735,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); end end end - end if(HaltW) $finish; end - - - endmodule From b2789f304a2af62c56000520fa270f6b3ce0b964 Mon Sep 17 00:00:00 2001 From: Huda-10xe Date: Fri, 15 Nov 2024 00:39:16 -0800 Subject: [PATCH 07/42] Removing old code (not in use anymore) --- testbench/testbench.sv | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 5b053c763..b2dda03ab 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -33,12 +33,6 @@ `include "idv/idv.svh" `endif -`ifdef RVVI_COVERAGE - `include "RISCV_trace_data.svh" - `include "rvvicov.svh" - `include "wrapper.sv" -`endif - import cvw::*; module testbench; @@ -973,12 +967,6 @@ test_pmp_coverage #(P) pmp_inst(clk); /* verilator lint_on WIDTHTRUNC */ /* verilator lint_on WIDTHEXPAND */ -`ifdef RVVI_COVERAGE - rvviTrace #(.XLEN(P.XLEN), .FLEN(P.FLEN)) rvvi(); - wallyTracer #(P) wallyTracer(rvvi); - wrapper #(P) wrap(clk); -`endif - endmodule /* verilator lint_on STMTDLY */ From c02a649c3b12ca3020c0f8e3df834f2061cfa66a Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 15 Nov 2024 05:33:16 -0800 Subject: [PATCH 08/42] Fixed warnings related to tracer variables --- testbench/common/wallyTracer.sv | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index e2be8c7df..4dd4fd29d 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -115,21 +115,21 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign PPN_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; logic valid; - int csrid; - + always_comb begin // Since we are detected the CSR change by comparing the old value we need to // ensure the CSR is detected when the pipeline's Writeback stage is not // stalled. If it is stalled we want CSRArray to hold the old value. if(valid) begin // PMPCFG CSRs (space is 0-15 3a0 - 3af) - int inc = P.XLEN == 32 ? 4 : 8; + localparam inc = P.XLEN == 32 ? 4 : 8; int i, i4, i8, csrid; logic [P.XLEN-1:0] pmp; for (i=0; i Date: Fri, 15 Nov 2024 05:58:30 -0800 Subject: [PATCH 09/42] Removed fcovimp support --- .gitignore | 3 --- bin/wsim | 13 ++----------- sim/questa/wally.do | 20 -------------------- 3 files changed, 2 insertions(+), 34 deletions(-) diff --git a/.gitignore b/.gitignore index 31db4f885..64fbbbf23 100644 --- a/.gitignore +++ b/.gitignore @@ -105,9 +105,6 @@ sim/questa/wkdir sim/questa/ucdb sim/questa/cov sim/questa/fcov -sim/questa/fcovrvvi -sim/questa/fcovrvvi_logs -sim/questa/fcovrvvi_ucdb sim/questa/fcov_logs sim/questa/fcov_ucdb sim/questa/riscv.ucdb diff --git a/bin/wsim b/bin/wsim index 72ec81a22..2b3849ecc 100755 --- a/bin/wsim +++ b/bin/wsim @@ -27,7 +27,6 @@ parser.add_argument("--sim", "-s", help="Simulator", choices=["questa", "verilat parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench") parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true") parser.add_argument("--ccov", "-c", help="Code Coverage", action="store_true") -parser.add_argument("--fcovimp", "-f2", help="Functional Coverage with Imperas licensed riscvISACOV, implies lockstep", action="store_true") parser.add_argument("--fcov", "-f", help="Functional Coverage with cvw-arch-verif, implies lockstep", action="store_true") parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="") parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="") @@ -70,7 +69,7 @@ if(args.lockstep and not args.testsuite.endswith('.elf') and not args.testsuite exit(1) # Validate arguments -if (args.gui or args.ccov or args.fcov or args.fcovimp or args.lockstep or args.lockstepverbose): +if (args.gui or args.ccov or args.fcov or args.lockstep or args.lockstepverbose): if args.sim not in ["questa", "vcs"]: print("Option only supported for Questa and VCS") exit(1) @@ -88,7 +87,7 @@ if (args.tb == "testbench_fp"): if(int(args.locksteplog) >= 1): EnableLog = 1 else: EnableLog = 0 prefix = "" -if (args.lockstep or args.lockstepverbose or args.fcov or args.fcovimp): +if (args.lockstep or args.lockstepverbose or args.fcov): if (args.sim == "questa" or args.sim == "vcs"): imperasicPath = os.path.join(WALLY, "config", args.config, "imperas.ic") if not os.path.isfile(imperasicPath): # If config is a derivative, look for imperas.ic in derivative configs @@ -101,12 +100,6 @@ if (args.sim == "questa"): if (args.lockstep or args.lockstepverbose): if(args.locksteplog != 0): ImperasPlusArgs = " +IDV_TRACE2LOG=" + str(EnableLog) + " +IDV_TRACE2LOG_AFTER=" + str(args.locksteplog) else: ImperasPlusArgs = "" - if(args.fcovimp): - CovEnableStr = "1" if int(args.covlog) > 0 else "0" - if(args.covlog >= 1): EnableLog = 1 - else: EnableLog = 0 - ImperasPlusArgs = " +IDV_TRACE2COV=" + str(EnableLog) + " +TRACE2LOG_AFTER=" + str(args.covlog) + " +TRACE2COV_ENABLE=" + CovEnableStr - suffix = "" if(args.fcov): CovEnableStr = "1" if int(args.covlog) > 0 else "0"; if(args.covlog >= 1): EnableLog = 1 @@ -130,8 +123,6 @@ if (args.ccov): flags += " --ccov" if (args.fcov): flags += " --fcov" -if (args.fcovimp): - flags += " --fcovimp" # create the output sub-directories. regressionDir = WALLY + '/sim/' diff --git a/sim/questa/wally.do b/sim/questa/wally.do index c692b06e1..6f613c404 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -103,26 +103,6 @@ if {[lcheck lst "--ccov"]} { set CoverageVsimArg "-coverage" } -# if --fcovimp found set flag and remove from list -if {[lcheck lst "--fcovimp"]} { - set FunctCoverage 1 - set FCvlog "+define+INCLUDE_TRACE2COV \ - +define+IDV_INCLUDE_TRACE2COV \ - +define+COVER_BASE_RV64I \ - +define+COVER_LEVEL_DV_PR_EXT \ - +incdir+${IMPERAS_HOME}/ImpProprietary/source/host/riscvISACOV/source" - set FCvopt "+TRACE2COV_ENABLE=1 +IDV_TRACE2COV=1" - # Uncomment various cover statements below to control which extensions get functional coverage - lappend FCdefineCOVER_EXTS "+define+COVER_RV64I" - #lappend FCdefineCOVER_EXTS "+define+COVER_RV64M" - #lappend FCdefineCOVER_EXTS "+define+COVER_RV64A" - #lappend FCdefineCOVER_EXTS "+define+COVER_RV64F" - #lappend FCdefineCOVER_EXTS "+define+COVER_RV64D" - #lappend FCdefineCOVER_EXTS "+define+COVER_RV64ZICSR" - #lappend FCdefineCOVER_EXTS "+define+COVER_RV64C" - -} - # if --fcov found set flag and remove from list if {[lcheck lst "--fcov"]} { set FunctCoverage 1 From 3596be433c44ba8afff66783eacc4a8d58f2b2b4 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Fri, 15 Nov 2024 08:31:19 -0600 Subject: [PATCH 10/42] Fixed the tracer so that traps don't clear the instruction or PC bits. --- testbench/common/wallyTracer.sv | 47 +++++++++++++++++---------------- 1 file changed, 24 insertions(+), 23 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 4dd4fd29d..bdf325b1e 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -24,7 +24,7 @@ `define NUM_CSRS 4096 `define STD_LOG 1 -`define PRINT_PC_INSTR 0 +`define PRINT_PC_INSTR 1 `define PRINT_MOST 0 `define PRINT_ALL 0 `define PRINT_CSRS 0 @@ -325,9 +325,9 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); // pipeline to writeback stage flopenrc #(32) InstrRawEReg (clk, reset, FlushE, ~StallE, InstrRawD, InstrRawE); flopenrc #(32) InstrRawMReg (clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM); - flopenrc #(32) InstrRawWReg (clk, reset, FlushW, ~StallW, InstrRawM, InstrRawW); - flopenrc #(P.XLEN)PCWReg (clk, reset, FlushW, ~StallW, PCM, PCW); - flopenrc #(1) InstrValidMReg (clk, reset, FlushW, ~StallW, InstrValidM, InstrValidW); + flopenrc #(32) InstrRawWReg (clk, reset, FlushW & ~TrapM, ~StallW, InstrRawM, InstrRawW); + flopenrc #(P.XLEN)PCWReg (clk, reset, FlushW & ~TrapM, ~StallW, PCM, PCW); + flopenrc #(1) InstrValidMReg (clk, reset, FlushW & ~TrapM, ~StallW, InstrValidM, InstrValidW); flopenrc #(1) TrapWReg (clk, reset, 1'b0, ~StallW, TrapM, TrapW); flopenrc #(1) InterruptWReg (clk, reset, 1'b0, ~StallW, InterruptM, InterruptW); flopenrc #(1) HaltWReg (clk, reset, 1'b0, ~StallW, HaltM, HaltW); @@ -346,6 +346,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, FlushW, ~StallW, PPN_dM, PPN_dW); flopenrc #(1) ReadAccessWReg (clk, reset, FlushW, ~StallW, ReadAccessM, ReadAccessW); flopenrc #(1) WriteAccessWReg (clk, reset, FlushW, ~StallW, WriteAccessM, WriteAccessW); + // *** what is this used for? flopenrc #(1) ExecuteAccessDReg (clk, reset, FlushE, ~StallE, ExecuteAccessF, ExecuteAccessD); flopenrc #(1) ExecuteAccessEReg (clk, reset, FlushE, ~StallE, ExecuteAccessD, ExecuteAccessE); flopenrc #(1) ExecuteAccessMReg (clk, reset, FlushM, ~StallM, ExecuteAccessE, ExecuteAccessM); @@ -712,26 +713,26 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); end end $fwrite(file, "\n"); - end - if(`PRINT_PC_INSTR & !(`PRINT_ALL | `PRINT_MOST)) - $display("order = %08d, PC = %08x, insn = %08x", rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0]); - else if(`PRINT_MOST & !`PRINT_ALL) - $display("order = %08d, PC = %010x, insn = %08x, trap = %1d, halt = %1d, intr = %1d, mode = %1x, ixl = %1x, pc_wdata = %010x, x%02d = %016x, f%02d = %016x, csr%03x = %016x", - rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0], rvvi.trap[0][0], rvvi.halt[0][0], rvvi.intr[0][0], rvvi.mode[0][0], rvvi.ixl[0][0], rvvi.pc_wdata[0][0], rf_a3, rvvi.x_wdata[0][0][rf_a3], frf_a4, rvvi.f_wdata[0][0][frf_a4], CSRAdrW, rvvi.csr[0][0][CSRAdrW]); - else if(`PRINT_ALL) begin - $display("order = %08d, PC = %08x, insn = %08x, trap = %1d, halt = %1d, intr = %1d, mode = %1x, ixl = %1x, pc_wdata = %08x", - rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0], rvvi.trap[0][0], rvvi.halt[0][0], rvvi.intr[0][0], rvvi.mode[0][0], rvvi.ixl[0][0], rvvi.pc_wdata[0][0]); - for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin - $display("x%02d = %08x", index2, rvvi.x_wdata[0][0][index2]); + if(`PRINT_PC_INSTR & !(`PRINT_ALL | `PRINT_MOST)) + $display("order = %08d, PC = %08x, insn = %08x", rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0]); + else if(`PRINT_MOST & !`PRINT_ALL) + $display("order = %08d, PC = %010x, insn = %08x, trap = %1d, halt = %1d, intr = %1d, mode = %1x, ixl = %1x, pc_wdata = %010x, x%02d = %016x, f%02d = %016x, csr%03x = %016x", + rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0], rvvi.trap[0][0], rvvi.halt[0][0], rvvi.intr[0][0], rvvi.mode[0][0], rvvi.ixl[0][0], rvvi.pc_wdata[0][0], rf_a3, rvvi.x_wdata[0][0][rf_a3], frf_a4, rvvi.f_wdata[0][0][frf_a4], CSRAdrW, rvvi.csr[0][0][CSRAdrW]); + else if(`PRINT_ALL) begin + $display("order = %08d, PC = %08x, insn = %08x, trap = %1d, halt = %1d, intr = %1d, mode = %1x, ixl = %1x, pc_wdata = %08x", + rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0], rvvi.trap[0][0], rvvi.halt[0][0], rvvi.intr[0][0], rvvi.mode[0][0], rvvi.ixl[0][0], rvvi.pc_wdata[0][0]); + for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin + $display("x%02d = %08x", index2, rvvi.x_wdata[0][0][index2]); + end + for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin + $display("f%02d = %08x", index2, rvvi.f_wdata[0][0][index2]); + end end - for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin - $display("f%02d = %08x", index2, rvvi.f_wdata[0][0][index2]); - end - end - if (`PRINT_CSRS) begin - for(index2 = 0; index2 < `NUM_CSRS; index2 += 1) begin - if(CSR_W[index2]) begin - $display("%t: CSR %03x = %x", $time(), index2, CSRArray[index2]); + if (`PRINT_CSRS) begin + for(index2 = 0; index2 < `NUM_CSRS; index2 += 1) begin + if(CSR_W[index2]) begin + $display("%t: CSR %03x = %x", $time(), index2, CSRArray[index2]); + end end end end From fcf4ca1417236b763a80c22400548c30f6326fd0 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Fri, 15 Nov 2024 08:32:43 -0600 Subject: [PATCH 11/42] Disabled tracer print. --- testbench/common/wallyTracer.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index bdf325b1e..a32417737 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -24,7 +24,7 @@ `define NUM_CSRS 4096 `define STD_LOG 1 -`define PRINT_PC_INSTR 1 +`define PRINT_PC_INSTR 0 `define PRINT_MOST 0 `define PRINT_ALL 0 `define PRINT_CSRS 0 From 234e47a7c5226bf04c23f7708057d7298687d864 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 15 Nov 2024 15:37:25 -0800 Subject: [PATCH 12/42] MTIMECMP should reset to maximum value for RV32, not just for RV64 --- src/uncore/clint_apb.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/uncore/clint_apb.sv b/src/uncore/clint_apb.sv index 76735aaa6..e03745194 100644 --- a/src/uncore/clint_apb.sv +++ b/src/uncore/clint_apb.sv @@ -115,7 +115,7 @@ module clint_apb import cvw::*; #(parameter cvw_t P) ( always_ff @(posedge PCLK) if (~PRESETn) begin MSIP <= 1'b0; - MTIMECMP <= '0; + MTIMECMP <= 64'hFFFFFFFFFFFFFFFF; // Spec says MTIMECMP is not reset, but we reset to maximum value to prevent spurious timer interrupts end else if (memwrite) begin if (entry == 16'h0000) MSIP <= PWDATA[0]; if (entry == 16'h4000) From c9267929417926746258ac5f414af751e2f3b3d3 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 15 Nov 2024 20:24:03 -0800 Subject: [PATCH 13/42] Update riscv-arch-test --- addins/riscv-arch-test | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index 3843c736e..cd94912fe 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit 3843c736e427a2b52a0d06e6220b073afa4be401 +Subproject commit cd94912fed2aab75d7d5f115b441da0813fdce8d From 2b57633217b9f1669ee16fff908d0f578803980a Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 15 Nov 2024 22:52:21 -0800 Subject: [PATCH 14/42] Switch to out of tree riscv-arch-test with VM tests + add pmp & vm tests to testbench --- addins/riscv-arch-test | 2 +- testbench/testbench.sv | 3 + testbench/tests.vh | 115 +++++++++++++++++++++ tests/riscof/sail_cSim/riscof_sail_cSim.py | 6 +- tests/riscof/spike/spike_rv32gc_isa.yaml | 2 +- 5 files changed, 122 insertions(+), 6 deletions(-) diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index cd94912fe..a079bb263 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit cd94912fed2aab75d7d5f115b441da0813fdce8d +Subproject commit a079bb263b04dde4028efee134f3a4e42799a5ca diff --git a/testbench/testbench.sv b/testbench/testbench.sv index b2dda03ab..69cf926f5 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -175,6 +175,7 @@ module testbench; "arch64zknd": if (P.ZKND_SUPPORTED) tests = arch64zknd; "arch64zkne": if (P.ZKNE_SUPPORTED) tests = arch64zkne; "arch64zknh": if (P.ZKNH_SUPPORTED) tests = arch64zknh; + "arch64pmp": if (P.PMP_ENTRIES > 0) tests = arch64pmp; endcase end else begin // RV32 case (TEST) @@ -217,6 +218,8 @@ module testbench; "arch32zknd": if (P.ZKND_SUPPORTED) tests = arch32zknd; "arch32zkne": if (P.ZKNE_SUPPORTED) tests = arch32zkne; "arch32zknh": if (P.ZKNH_SUPPORTED) tests = arch32zknh; + "arch32pmp": if (P.PMP_ENTRIES > 0) tests = arch32pmp; + "arch32vm_sv32": if (P.VIRTMEM_SUPPORTED) tests = arch32vm_sv32; endcase end if (tests.size() == 0 & ElfFile == "none") begin diff --git a/testbench/tests.vh b/testbench/tests.vh index 2b8d3a2ec..59cd84437 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -149,6 +149,121 @@ string wally32a_lrsc[] = '{ "rv32i_m/privilege/src/WALLY-lrsc-01.S" }; +string arch32pmp[] = '{ + `RISCVARCHTEST, + "rv32i_m/pmp32/src/pmp-CFG-reg.S", + "rv32i_m/pmp32/src/pmp-CSR-access.S", + "rv32i_m/pmp32/src/pmp-NA4-R-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-NA4-R-priority.S", + "rv32i_m/pmp32/src/pmp-NA4-R.S", + "rv32i_m/pmp32/src/pmp-NA4-RW-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-NA4-RW-priority.S", + "rv32i_m/pmp32/src/pmp-NA4-RW.S", + "rv32i_m/pmp32/src/pmp-NA4-RWX.S", + "rv32i_m/pmp32/src/pmp-NA4-RX-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-NA4-RX-priority.S", + "rv32i_m/pmp32/src/pmp-NA4-RX.S", + "rv32i_m/pmp32/src/pmp-NA4-X-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-NA4-X-priority.S", + "rv32i_m/pmp32/src/pmp-NA4-X.S", + "rv32i_m/pmp32/src/pmp-NAPOT-R-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-NAPOT-R-priority.S", + "rv32i_m/pmp32/src/pmp-NAPOT-R.S", + "rv32i_m/pmp32/src/pmp-NAPOT-RW-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-NAPOT-RW-priority.S", + "rv32i_m/pmp32/src/pmp-NAPOT-RW.S", + "rv32i_m/pmp32/src/pmp-NAPOT-RWX.S", + "rv32i_m/pmp32/src/pmp-NAPOT-RX-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-NAPOT-RX-priority.S", + "rv32i_m/pmp32/src/pmp-NAPOT-RX.S", + "rv32i_m/pmp32/src/pmp-NAPOT-X-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-NAPOT-X-priority.S", + "rv32i_m/pmp32/src/pmp-NAPOT-X.S", + "rv32i_m/pmp32/src/pmp-TOR-R-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-TOR-R-priority.S", + "rv32i_m/pmp32/src/pmp-TOR-R.S", + "rv32i_m/pmp32/src/pmp-TOR-RW-priority-level-2..S", + "rv32i_m/pmp32/src/pmp-TOR-RW-priority.S", + "rv32i_m/pmp32/src/pmp-TOR-RW.S", + "rv32i_m/pmp32/src/pmp-TOR-RWX.S", + "rv32i_m/pmp32/src/pmp-TOR-RX-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-TOR-RX-priority.S", + "rv32i_m/pmp32/src/pmp-TOR-RX.S", + "rv32i_m/pmp32/src/pmp-TOR-X-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-TOR-X-priority.S", + "rv32i_m/pmp32/src/pmp-TOR-X.S" +}; + +string arch64pmp[] = '{ + `RISCVARCHTEST, + "rv64i_m/pmp64/pmp64-CFG-reg.S", + "rv64i_m/pmp64/pmp64-CSR-access.S", + "rv64i_m/pmp64/pmp64-NA4-R-priority-level-2.S", + "rv64i_m/pmp64/pmp64-NA4-R-priority.S", + "rv64i_m/pmp64/pmp64-NA4-R.S", + "rv64i_m/pmp64/pmp64-NA4-RW-priority-level-2.S", + "rv64i_m/pmp64/pmp64-NA4-RW-priority.S", + "rv64i_m/pmp64/pmp64-NA4-RW.S", + "rv64i_m/pmp64/pmp64-NA4-RWX.S", + "rv64i_m/pmp64/pmp64-NA4-RX-priority-level-2.S", + "rv64i_m/pmp64/pmp64-NA4-RX-priority.S", + "rv64i_m/pmp64/pmp64-NA4-RX.S", + "rv64i_m/pmp64/pmp64-NA4-X-priority-level-2.S", + "rv64i_m/pmp64/pmp64-NA4-X-priority.S", + "rv64i_m/pmp64/pmp64-NA4-X.S", + "rv64i_m/pmp64/pmp64-NAPOT-R-priority-level-2.S", + "rv64i_m/pmp64/pmp64-NAPOT-R-priority.S", + "rv64i_m/pmp64/pmp64-NAPOT-R.S", + "rv64i_m/pmp64/pmp64-NAPOT-RW-priority-level-2.S", + "rv64i_m/pmp64/pmp64-NAPOT-RW-priority.S", + "rv64i_m/pmp64/pmp64-NAPOT-RW.S", + "rv64i_m/pmp64/pmp64-NAPOT-RWX.S", + "rv64i_m/pmp64/pmp64-NAPOT-RX-priority-level-2.S", + "rv64i_m/pmp64/pmp64-NAPOT-RX-priority.S", + "rv64i_m/pmp64/pmp64-NAPOT-RX.S", + "rv64i_m/pmp64/pmp64-NAPOT-X-priority-level-2.S", + "rv64i_m/pmp64/pmp64-NAPOT-X-priority.S", + "rv64i_m/pmp64/pmp64-NAPOT-X.S", + "rv64i_m/pmp64/pmp64-TOR-R-priority-level-2.S", + "rv64i_m/pmp64/pmp64-TOR-R-priority.S", + "rv64i_m/pmp64/pmp64-TOR-R.S", + "rv64i_m/pmp64/pmp64-TOR-RW-priority-level-2..S", + "rv64i_m/pmp64/pmp64-TOR-RW-priority.S", + "rv64i_m/pmp64/pmp64-TOR-RW.S", + "rv64i_m/pmp64/pmp64-TOR-RWX.S", + "rv64i_m/pmp64/pmp64-TOR-RX-priority-level-2.S", + "rv64i_m/pmp64/pmp64-TOR-RX-priority.S", + "rv64i_m/pmp64/pmp64-TOR-RX.S", + "rv64i_m/pmp64/pmp64-TOR-X-priority-level-2.S", + "rv64i_m/pmp64/pmp64-TOR-X-priority.S", + "rv64i_m/pmp64/pmp64-TOR-X.S" +}; + +string arch32vm_sv32[] = '{ + `RISCVARCHTEST, + "rv32i_m/vm_sv32/src/pmp_check_on_pa_S_mode.S", + "rv32i_m/vm_sv32/src/pmp_check_on_pa_U_mode.S", + "rv32i_m/vm_sv32/src/pmp_check_on_pte_S_mode.S", + "rv32i_m/vm_sv32/src/pmp_check_on_pte_U_mode.S", + "rv32i_m/vm_sv32/src/vm_A_and_D_S_mode.S", + "rv32i_m/vm_sv32/src/vm_A_and_D_U_mode.S", + "rv32i_m/vm_sv32/src/vm_invalid_pte_S_mode.S", + "rv32i_m/vm_sv32/src/vm_invalid_pte_U_mode.S", + "rv32i_m/vm_sv32/src/vm_misaligned_S_mode.S", + "rv32i_m/vm_sv32/src/vm_misaligned_U_mode.S", + "rv32i_m/vm_sv32/src/vm_mxr_S_mode.S", + "rv32i_m/vm_sv32/src/vm_mxr_U_mode.S", + "rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_S_mode.S", + "rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_U_mode.S", + "rv32i_m/vm_sv32/src/vm_reserved_pte_S_mode.S", + "rv32i_m/vm_sv32/src/vm_reserved_pte_U_mode.S", + "rv32i_m/vm_sv32/src/vm_sum_set_S_mode.S", + "rv32i_m/vm_sv32/src/vm_sum_unset_S_mode.S", + "rv32i_m/vm_sv32/src/vm_U_Bit_set_U_mode.S", + "rv32i_m/vm_sv32/src/vm_U_Bit_unset_S_mode.S", + "rv32i_m/vm_sv32/src/vm_U_Bit_unset_U_mode.S" +}; + string arch64priv[] = '{ `RISCVARCHTEST, "rv64i_m/privilege/src/ebreak.S", diff --git a/tests/riscof/sail_cSim/riscof_sail_cSim.py b/tests/riscof/sail_cSim/riscof_sail_cSim.py index 9abe67040..557d1af04 100644 --- a/tests/riscof/sail_cSim/riscof_sail_cSim.py +++ b/tests/riscof/sail_cSim/riscof_sail_cSim.py @@ -52,7 +52,7 @@ class sail_cSim(pluginTemplate): ispec = utils.load_yaml(isa_yaml)['hart0'] self.xlen = ('64' if 64 in ispec['supported_xlen'] else '32') self.isa = 'rv' + self.xlen - self.sailargs = ' ' + self.sailargs = ' --pmp-count=16 --pmp-grain=0 ' # Hardcode pmp-count and pmp-grain for now. Make configurable later once Sail has easier configuration self.compile_cmd = self.compile_cmd+' -mabi='+('lp64 ' if 64 in ispec['supported_xlen'] else ('ilp32e ' if "E" in ispec["ISA"] else 'ilp32 ')) if "I" in ispec["ISA"]: self.isa += 'i' @@ -103,7 +103,6 @@ class sail_cSim(pluginTemplate): execute = "@cd "+testentry['work_dir']+";" -# cmd = self.compile_cmd.format(testentry['isa'].lower().replace('zicsr', ' ', 1), self.xlen) + ' ' + test + ' -o ' + elf cmd = self.compile_cmd.format(testentry['isa'].lower(), self.xlen) + ' ' + test + ' -o ' + elf compile_cmd = cmd + ' -D' + " -D".join(testentry['macros']) execute+=compile_cmd+";" @@ -117,8 +116,7 @@ class sail_cSim(pluginTemplate): reference_output = re.sub("/src/","/references/", re.sub(".S",".reference_output", test)) execute += 'cut -c-{0:g} {1} > {2}'.format(8, reference_output, sig_file) #use cut to remove comments when copying else: - execute += self.sail_exe[self.xlen] + ' -z268435455 -i ' + self.sailargs + ' --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name) -# execute += self.sail_exe[self.xlen] + ' -z268435455 -i --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name) + execute += self.sail_exe[self.xlen] + ' -z268435455 -i --trace=step ' + self.sailargs + ' --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name) cov_str = ' ' for label in testentry['coverage_labels']: diff --git a/tests/riscof/spike/spike_rv32gc_isa.yaml b/tests/riscof/spike/spike_rv32gc_isa.yaml index 3fde70700..0b07212cc 100644 --- a/tests/riscof/spike/spike_rv32gc_isa.yaml +++ b/tests/riscof/spike/spike_rv32gc_isa.yaml @@ -26,4 +26,4 @@ hart0: legal: - extensions[25:0] bitmask [0x000112D, 0x0000000] wr_illegal: - - Unchangedcd \ No newline at end of file + - Unchanged \ No newline at end of file From a462b9a2e66dd43effed4f173118b50ba2749cbb Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 15 Nov 2024 23:52:50 -0800 Subject: [PATCH 15/42] Clean up verilator lint off commands and remove unnecessay ones --- config/shared/config-shared.vh | 6 ------ config/shared/parameter-defs.vh | 4 ---- src/fpu/fdivsqrt/fdivsqrtiter.sv | 2 -- src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtstage2.sv | 2 -- src/fpu/fround.sv | 4 ++-- src/generic/prioritythermometer.sv | 2 -- src/lsu/lsu.sv | 2 -- src/mdu/divstep.sv | 4 ---- src/privileged/csrm.sv | 2 ++ src/uncore/spi_apb.sv | 4 ++-- src/uncore/uartPC16550D.sv | 4 ++-- 12 files changed, 9 insertions(+), 29 deletions(-) diff --git a/config/shared/config-shared.vh b/config/shared/config-shared.vh index 91e1d4100..4ccb24bf2 100644 --- a/config/shared/config-shared.vh +++ b/config/shared/config-shared.vh @@ -122,9 +122,3 @@ localparam FMALEN = 3*NF + 6; localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1), (DIVb + 1 + NF + 1)), (FMALEN + 2)); localparam LOGNORMSHIFTSZ = ($clog2(NORMSHIFTSZ)); // log_2(NORMSHIFTSZ) - -// Disable spurious Verilator warnings - -/* verilator lint_off STMTDLY */ -/* verilator lint_off ASSIGNDLY */ -/* verilator lint_off PINCONNECTEMPTY */ diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh index c80b00232..88de34afc 100644 --- a/config/shared/parameter-defs.vh +++ b/config/shared/parameter-defs.vh @@ -95,11 +95,7 @@ localparam cvw_t P = '{ PLIC_SPI_ID : PLIC_SPI_ID, PLIC_SDC_ID : PLIC_SDC_ID, BPRED_SUPPORTED : BPRED_SUPPORTED, - /* verilator lint_off ENUMVALUE */ - // *** definitely need to fix this. - // it thinks we are casting from the enum type to BPRED_TYPE. BPRED_TYPE : BPRED_TYPE, - /* verilator lint_on ENUMVALUE */ BPRED_SIZE : BPRED_SIZE, BPRED_NUM_LHR : BPRED_NUM_LHR, BTB_SIZE : BTB_SIZE, diff --git a/src/fpu/fdivsqrt/fdivsqrtiter.sv b/src/fpu/fdivsqrt/fdivsqrtiter.sv index 39de58855..ff03d29ec 100644 --- a/src/fpu/fdivsqrt/fdivsqrtiter.sv +++ b/src/fpu/fdivsqrt/fdivsqrtiter.sv @@ -38,7 +38,6 @@ module fdivsqrtiter import cvw::*; #(parameter cvw_t P) ( output logic [P.DIVb+3:0] FirstWS, FirstWC // Q4.DIVb ); - /* verilator lint_off UNOPTFLAT */ logic [P.DIVb+3:0] WSNext[P.DIVCOPIES-1:0]; // Q4.DIVb logic [P.DIVb+3:0] WCNext[P.DIVCOPIES-1:0]; // Q4.DIVb logic [P.DIVb+3:0] WS[P.DIVCOPIES:0]; // Q4.DIVb @@ -56,7 +55,6 @@ module fdivsqrtiter import cvw::*; #(parameter cvw_t P) ( logic [P.DIVb+1:0] NextC; // Q2.DIVb logic [P.DIVb:0] UMux, UMMux; // U1.DIVb logic [P.DIVb:0] initU, initUM; // U1.DIVb - /* verilator lint_on UNOPTFLAT */ // Top Muxes and Registers // When start is asserted, the inputs are loaded into the divider. diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index 737d9089a..a399e4a4f 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -136,7 +136,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( // calculate right shift amount RightShiftX to complete in discrete number of steps if (P.RK > 1) begin // more than 1 bit per cycle logic [$clog2(P.RK)-1:0] RightShiftX; - /* verilator lint_offf WIDTH */ + /* verilator lint_off WIDTH */ assign RightShiftX = P.RK - 1 - ((IntResultBitsE - 1) % P.RK); // Right shift amount assign DivXShifted = DivX >> RightShiftX; // shift X by up to R*K-1 to complete in n steps /* verilator lint_on WIDTH */ diff --git a/src/fpu/fdivsqrt/fdivsqrtstage2.sv b/src/fpu/fdivsqrt/fdivsqrtstage2.sv index fa13cadeb..06ac4ec82 100644 --- a/src/fpu/fdivsqrt/fdivsqrtstage2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtstage2.sv @@ -28,7 +28,6 @@ //////////////////////////////////////////////////////////////////////////////////////////////// -/* verilator lint_off UNOPTFLAT */ module fdivsqrtstage2 import cvw::*; #(parameter cvw_t P) ( input logic [P.DIVb+3:0] D, DBar, // Q4.DIVb input logic [P.DIVb:0] U, UM, // U1.DIVb @@ -40,7 +39,6 @@ module fdivsqrtstage2 import cvw::*; #(parameter cvw_t P) ( output logic [P.DIVb:0] UNext, UMNext, // U1.DIVb output logic [P.DIVb+3:0] WSNext, WCNext // Q4.DIVb ); - /* verilator lint_on UNOPTFLAT */ logic [P.DIVb+3:0] Dsel; // Q4.DIVb logic up, uz; diff --git a/src/fpu/fround.sv b/src/fpu/fround.sv index 2814c766b..519d55096 100644 --- a/src/fpu/fround.sv +++ b/src/fpu/fround.sv @@ -115,9 +115,9 @@ module fround import cvw::*; #(parameter cvw_t P) ( /////////////////////////// // Exact logic - // verilator lint_off WIDTHEXPAND + /* verilator lint_off WIDTHEXPAND */ assign EgeNf = (E >= Nf) & Xe[P.NE-1]; // Check if E >= Nf. Also check that Xe is positive to avoid wraparound problems - // verilator lint_on WIDTHEXPAND + /* verilator lint_on WIDTHEXPAND */ // Rounding logic: determine whether to round up in magnitude always_comb begin diff --git a/src/generic/prioritythermometer.sv b/src/generic/prioritythermometer.sv index 23acfcfb3..ecf37e80e 100644 --- a/src/generic/prioritythermometer.sv +++ b/src/generic/prioritythermometer.sv @@ -39,11 +39,9 @@ module prioritythermometer #(parameter N = 8) ( // Rather than linear. // create thermometer code mask - /* verilator lint_off UNOPTFLAT */ genvar i; assign y[0] = ~a[0]; for (i=1; i= rxfifotail) ? (rxfifohead-rxfifotail) : (rxfifohead + 16 - rxfifotail); - // verilator lint_on WIDTH + /* verilator lint_on WIDTH */ assign rxfifotriggered = rxfifoentries >= rxfifotriggerlevel; assign rxfifotimeout = rxtimeoutcnt == {rxbitsexpected, 6'b0}; // time out after 4 character periods; probably not right yet //assign rxfifotimeout = 0; // disabled pending fix From 98f2ec6d6629dbd51c02ef7244f46003695e28e3 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 16 Nov 2024 09:58:04 -0800 Subject: [PATCH 16/42] Updated regression-wally --fcov to run privileged tests in lockstep --- bin/regression-wally | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index cc0588bf6..f4c3cc023 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -301,7 +301,8 @@ def addLockstepTestsByDir(dir, config, sim, fcovMode): for dirpath, dirnames, filenames in os.walk(os.path.abspath(dir)): for file in filenames: # fcov lockstep only runs on WALLY-COV-ALL.elf files; other lockstep runs on all files - if (file.endswith(".elf") and fcovMode == 0 or file.endswith("ALL.elf") and fcovMode == 1): + if ((file.endswith(".elf") and (fcovMode == 0 or "tests/priv" in dir)) or + (file.endswith("ALL.elf") and fcovMode == 1)): fullfile = os.path.join(dirpath, file) fields = fullfile.rsplit('/', 3) if (fields[2] == "ref"): @@ -419,9 +420,11 @@ if (args.ccov): # only run RV64GC tests on Questa in code coverage mode addTests(tests64gc_nofp, coveragesim) if (args.fp): addTests(tests64gc_fp, coveragesim) -elif (args.fcov): # only run RV64GC tests on Questa in lockstep in functional coverage mode +elif (args.fcov): # run tests in lockstep in functional coverage mode addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv32/", "rv32gc", coveragesim, 1) addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim, 1) + addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv32/", "rv32gc", coveragesim, 1) + addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv64/", "rv64gc", coveragesim, 1) #addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege/src/", "rv64gc", coveragesim, 0) else: From 45f6cb055dd9723d79c300bd5a833e8a391057c0 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 16 Nov 2024 11:47:45 -0800 Subject: [PATCH 17/42] Changed reservation set size to one word to fix RV32GC lrsc privileged test failure Issue #1092 --- config/rv32gc/imperas.ic | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/config/rv32gc/imperas.ic b/config/rv32gc/imperas.ic index 46d0d31c3..2ba3c1280 100644 --- a/config/rv32gc/imperas.ic +++ b/config/rv32gc/imperas.ic @@ -36,7 +36,7 @@ --override cpu/Zicboz=T --override cmomp_bytes=64 # Zic64b --override cmoz_bytes=64 # Zic64b ---override lr_sc_grain=8 # Za64rs requires <=64; we use native word size +--override lr_sc_grain=4 # Za64rs requires <=64; we use native word size # 64 KiB continuous huge pages supported #--override cpu/Svpbmt=F From 1675e4cb7d10827515ffb42c772f216ca5c8a067 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 16 Nov 2024 11:53:05 -0800 Subject: [PATCH 18/42] Add rv32 wally-riscv-arch-test lockstep to nightly --- bin/regression-wally | 1 + 1 file changed, 1 insertion(+) diff --git a/bin/regression-wally b/bin/regression-wally index f4c3cc023..2a2466dfa 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -439,6 +439,7 @@ else: if (args.nightly): addLockstepTestsByDir(WALLY+"/tests/coverage", "rv64gc", lockstepsim, 0) addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m", "rv64gc", lockstepsim, 0) + addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv32i_m", "rv32gc", lockstepsim, 0) addTests(derivconfigtests, defaultsim) # addTests(bpredtests, defaultsim) # This is currently broken in regression due to something related to the new wsim script. From f6b0805fd4fe2697f292802db62f2709bf16b2c2 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 16 Nov 2024 12:35:37 -0800 Subject: [PATCH 19/42] More lint cleanup: remove unused params --- bin/lint-wally | 2 +- src/cache/cache.sv | 18 +++++------------- src/cache/cacheLRU.sv | 2 +- src/cache/cachefsm.sv | 3 +-- src/cache/cacheway.sv | 9 +-------- src/hazard/hazard.sv | 2 +- src/ifu/ifu.sv | 2 +- src/lsu/lsu.sv | 2 +- src/privileged/csrs.sv | 2 -- src/uncore/ram_ahb.sv | 2 +- src/uncore/rom_ahb.sv | 2 +- src/uncore/uncore.sv | 4 ++-- src/wally/wallypipelinedcore.sv | 2 +- 13 files changed, 17 insertions(+), 35 deletions(-) diff --git a/bin/lint-wally b/bin/lint-wally index d4fcd8767..ef79a6a00 100755 --- a/bin/lint-wally +++ b/bin/lint-wally @@ -30,7 +30,7 @@ for config in ${configs[@]}; do if !($verilator --lint-only --quiet --top-module wallywrapper \ "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" \ $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv \ - -Wall -Wno-UNUSEDSIGNAL -Wno-UNUSEDPARAM -Wno-VARHIDDEN -Wno-GENUNNAMED -Wno-PINCONNECTEMPTY); then + -Wall -Wno-UNUSEDSIGNAL -Wno-VARHIDDEN -Wno-GENUNNAMED -Wno-PINCONNECTEMPTY); then if [ "$1" == "-nightly" ]; then echo -e "${RED}$config failed lint${NC}" fails=$((fails+1)) diff --git a/src/cache/cache.sv b/src/cache/cache.sv index 7307c233e..b74ecdcff 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -29,7 +29,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module cache import cvw::*; #(parameter cvw_t P, - parameter PA_BITS, XLEN, LINELEN, NUMSETS, NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, READ_ONLY_CACHE) ( + parameter PA_BITS, LINELEN, NUMSETS, NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, READ_ONLY_CACHE) ( input logic clk, input logic reset, input logic Stall, // Stall the cache, preventing new accesses. In-flight access finished but does not return to READY @@ -66,11 +66,7 @@ module cache import cvw::*; #(parameter cvw_t P, localparam SETLEN = $clog2(NUMSETS); // Number of set bits localparam SETTOP = SETLEN+OFFSETLEN; // Number of set plus offset bits localparam TAGLEN = PA_BITS - SETTOP; // Number of tag bits - localparam CACHEWORDSPERLINE = LINELEN/WORDLEN;// Number of words in cache line - localparam LOGCWPL = $clog2(CACHEWORDSPERLINE);// Log2 of ^ localparam FLUSHADRTHRESHOLD = NUMSETS - 1; // Used to determine when flush is complete - localparam LOGLLENBYTES = $clog2(WORDLEN/8); // Number of bits to address a word - logic SelAdrData; logic SelAdrTag; @@ -122,14 +118,14 @@ module cache import cvw::*; #(parameter cvw_t P, AdrSelMuxSelLRU, CacheSetLRU); // Array of cache ways, along with victim, hit, dirty, and read merging logic - cacheway #(P, PA_BITS, XLEN, NUMSETS, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0]( + cacheway #(P, PA_BITS, NUMSETS, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0]( .clk, .reset, .CacheEn, .CacheSetData, .CacheSetTag, .PAdr, .LineWriteData, .LineByteMask, .SelVictim, .SetValid, .ClearValid, .SetDirty, .ClearDirty, .VictimWay, .FlushWay, .FlushCache, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .HitDirtyWay, .TagWay, .FlushStage, .InvalidateCache); // Select victim way for associative caches if(NUMWAYS > 1) begin:vict - cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMSETS) cacheLRU( + cacheLRU #(NUMWAYS, SETLEN, NUMSETS) cacheLRU( .clk, .reset, .FlushStage, .CacheEn, .HitWay, .ValidWay, .VictimWay, .CacheSetLRU, .LRUWriteEn, .SetValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache); end else @@ -172,11 +168,7 @@ module cache import cvw::*; #(parameter cvw_t P, if(!READ_ONLY_CACHE) begin:WriteSelLogic logic [LINELEN/8-1:0] DemuxedByteMask, FetchBufferByteSel; - // Adjust byte mask from word to cache line - - localparam CACHEMUXINVERALPERLINE = LINELEN/MUXINTERVAL;// Number of words in cache line - localparam LOGMIPL = $clog2(CACHEMUXINVERALPERLINE);// Log2 of ^ - + // Adjust byte mask from word to cache line logic [LINELEN/8-1:0] BlankByteMask; assign BlankByteMask[WORDLEN/8-1:0] = ByteMask; assign BlankByteMask[LINELEN/8-1:WORDLEN/8] = 0; @@ -231,7 +223,7 @@ module cache import cvw::*; #(parameter cvw_t P, // Cache FSM ///////////////////////////////////////////////////////////////////////////////////////////// - cachefsm #(P, READ_ONLY_CACHE) cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck, + cachefsm #(READ_ONLY_CACHE) cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck, .FlushStage, .CacheRW, .Stall, .Hit, .LineDirty, .HitLineDirty, .CacheStall, .CacheCommitted, .CacheMiss, .CacheAccess, .SelAdrData, .SelAdrTag, .SelVictim, diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv index a91e7232c..2ab3bac8d 100644 --- a/src/cache/cacheLRU.sv +++ b/src/cache/cacheLRU.sv @@ -29,7 +29,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module cacheLRU - #(parameter NUMWAYS = 4, SETLEN = 9, OFFSETLEN = 5, NUMSETS = 128) ( + #(parameter NUMWAYS = 4, SETLEN = 9, NUMSETS = 128) ( input logic clk, input logic reset, input logic FlushStage, diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 5f42c7690..91aa5c97b 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -28,8 +28,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module cachefsm import cvw::*; #(parameter cvw_t P, - parameter READ_ONLY_CACHE = 0) ( +module cachefsm #(parameter READ_ONLY_CACHE = 0) ( input logic clk, input logic reset, // hazard and privilege unit diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 575934727..e2db5a46c 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -29,7 +29,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module cacheway import cvw::*; #(parameter cvw_t P, - parameter PA_BITS, XLEN, NUMSETS=512, LINELEN = 256, TAGLEN = 26, + parameter PA_BITS, NUMSETS=512, LINELEN = 256, TAGLEN = 26, OFFSETLEN = 5, INDEXLEN = 9, READ_ONLY_CACHE = 0) ( input logic clk, input logic reset, @@ -57,12 +57,6 @@ module cacheway import cvw::*; #(parameter cvw_t P, output logic DirtyWay , // The selected way is dirty output logic [TAGLEN-1:0] TagWay); // This way's tag if valid - localparam WORDSPERLINE = LINELEN/XLEN; - localparam BYTESPERLINE = LINELEN/8; - localparam LOGWPL = $clog2(WORDSPERLINE); - localparam LOGXLENBYTES = $clog2(XLEN/8); - localparam BYTESPERWORD = XLEN/8; - logic [NUMSETS-1:0] ValidBits; logic [NUMSETS-1:0] DirtyBits; logic [LINELEN-1:0] ReadDataLine; @@ -131,7 +125,6 @@ module cacheway import cvw::*; #(parameter cvw_t P, localparam NUMSRAM = LINELEN/P.CACHE_SRAMLEN; localparam SRAMLENINBYTES = P.CACHE_SRAMLEN/8; - localparam LOGNUMSRAM = $clog2(NUMSRAM); for(words = 0; words < NUMSRAM; words++) begin: word if (READ_ONLY_CACHE) begin:wordram // no byte-enable needed for i$. diff --git a/src/hazard/hazard.sv b/src/hazard/hazard.sv index 895a6e92f..63b31001c 100644 --- a/src/hazard/hazard.sv +++ b/src/hazard/hazard.sv @@ -27,7 +27,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module hazard import cvw::*; #(parameter cvw_t P) ( +module hazard ( input logic BPWrongE, CSRWriteFenceM, RetM, TrapM, input logic StructuralStallD, input logic LSUStallM, IFUStallF, diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index 695603758..a90483533 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -236,7 +236,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( assign BusRW = ~ITLBMissF & ~CacheableF & ~SelIROM ? IFURWF : '0; assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : '0; - cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.ICACHE_LINELENINBITS), + cache #(.P(P), .PA_BITS(P.PA_BITS), .LINELEN(P.ICACHE_LINELENINBITS), .NUMSETS(P.ICACHE_WAYSIZEINBYTES*8/P.ICACHE_LINELENINBITS), .NUMWAYS(P.ICACHE_NUMWAYS), .LOGBWPL(AHBWLOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .READ_ONLY_CACHE(1)) icache(.clk, .reset, .FlushStage(FlushD), .Stall(GatedStallD), diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 9f5d460f7..f6a215a27 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -324,7 +324,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign CacheRWM = (CacheableM & ~SelDTIM) ? LSURWM : '0; assign FlushDCache = FlushDCacheM & ~(SelHPTW); - cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMSETS(P.DCACHE_WAYSIZEINBYTES*8/LINELEN), + cache #(.P(P), .PA_BITS(P.PA_BITS), .LINELEN(P.DCACHE_LINELENINBITS), .NUMSETS(P.DCACHE_WAYSIZEINBYTES*8/LINELEN), .NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(CACHEWORDLEN), .MUXINTERVAL(P.LLEN), .READ_ONLY_CACHE(0)) dcache( .clk, .reset, .Stall(GatedStallW & ~SelSpillE), .SelBusBeat, .FlushStage(LSUFlushW), .CacheRW(CacheRWM), diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index a2a21c2ee..c30f78e14 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -67,8 +67,6 @@ module csrs import cvw::*; #(parameter cvw_t P) ( localparam STIMECMPH = 12'h15D; localparam SATP = 12'h180; // Constants - localparam ZERO = {(P.XLEN){1'b0}}; - localparam SEDELEG_MASK = ~(ZERO | {{P.XLEN-3{1'b0}}, 3'b111} << 9); logic WriteSTVECM; logic WriteSSCRATCHM, WriteSEPCM; diff --git a/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv index 0b4e777e4..60c870138 100644 --- a/src/uncore/ram_ahb.sv +++ b/src/uncore/ram_ahb.sv @@ -28,7 +28,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module ram_ahb import cvw::*; #(parameter cvw_t P, - parameter BASE=0, RANGE = 65535, PRELOAD = 0) ( + parameter RANGE = 65535, PRELOAD = 0) ( input logic HCLK, HRESETn, input logic HSELRam, input logic [P.PA_BITS-1:0] HADDR, diff --git a/src/uncore/rom_ahb.sv b/src/uncore/rom_ahb.sv index d20ef64da..63f6e9716 100644 --- a/src/uncore/rom_ahb.sv +++ b/src/uncore/rom_ahb.sv @@ -28,7 +28,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module rom_ahb import cvw::*; #(parameter cvw_t P, - parameter BASE=0, RANGE = 65535, PRELOAD = 0) ( + parameter RANGE = 65535, PRELOAD = 0) ( input logic HCLK, HRESETn, input logic HSELRom, input logic [P.PA_BITS-1:0] HADDR, diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index 21dd956ed..f17fc67fe 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -109,13 +109,13 @@ module uncore import cvw::*; #(parameter cvw_t P)( // on-chip RAM if (P.UNCORE_RAM_SUPPORTED) begin : ram - ram_ahb #(.P(P), .BASE(P.UNCORE_RAM_BASE), .RANGE(P.UNCORE_RAM_RANGE), .PRELOAD(P.UNCORE_RAM_PRELOAD)) ram ( + ram_ahb #(.P(P), .RANGE(P.UNCORE_RAM_RANGE), .PRELOAD(P.UNCORE_RAM_PRELOAD)) ram ( .HCLK, .HRESETn, .HSELRam, .HADDR, .HWRITE, .HREADY, .HTRANS, .HWDATA, .HWSTRB, .HREADRam, .HRESPRam, .HREADYRam); end else assign {HREADRam, HRESPRam, HREADYRam} = '0; if (P.BOOTROM_SUPPORTED) begin : bootrom - rom_ahb #(.P(P), .BASE(P.BOOTROM_BASE), .RANGE(P.BOOTROM_RANGE), .PRELOAD(P.BOOTROM_PRELOAD)) + rom_ahb #(.P(P), .RANGE(P.BOOTROM_RANGE), .PRELOAD(P.BOOTROM_PRELOAD)) bootrom(.HCLK, .HRESETn, .HSELRom(HSELBootRom), .HADDR, .HREADY, .HTRANS, .HREADRom(HREADBootRom), .HRESPRom(HRESPBootRom), .HREADYRom(HREADYBootRom)); end else assign {HREADBootRom, HRESPBootRom, HREADYBootRom} = '0; diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index 8158a1cfb..b5a80a24b 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -271,7 +271,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( end // global stall and flush control - hazard #(P) hzu( + hazard hzu( .BPWrongE, .CSRWriteFenceM, .RetM, .TrapM, .StructuralStallD, .LSUStallM, .IFUStallF, From 00d02e5656f92fd8888b5ce9245834440b96479e Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 16 Nov 2024 12:53:10 -0800 Subject: [PATCH 20/42] fix testbench --- testbench/testbench.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index b2dda03ab..7c28ebfe6 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -564,7 +564,7 @@ module testbench; assign SPIIn = 1'b0; if(P.EXT_MEM_SUPPORTED) begin - ram_ahb #(.P(P), .BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE)) + ram_ahb #(.P(P), .RANGE(P.EXT_MEM_RANGE)) ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT), .HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB); end else begin From def3b46afacf3a1142462a37b383240e7c618cad Mon Sep 17 00:00:00 2001 From: Corey Hickson Date: Sat, 16 Nov 2024 14:13:54 -0800 Subject: [PATCH 21/42] Add ZicsrU to fcov --- config/rv32gc/coverage.svh | 1 + config/rv64gc/coverage.svh | 1 + 2 files changed, 2 insertions(+) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index ba876f6b7..afd34306e 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -33,5 +33,6 @@ // Privileged extensions `include "ZicsrM_coverage.svh" `include "ZicsrF_coverage.svh" +`include "ZicsrU_coverage.svh" `include "RV32VM_coverage.svh" `include "RV32VM_PMP_coverage.svh" diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index 901616311..6108376f9 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -34,6 +34,7 @@ `include "RV64VM_coverage.svh" `include "ZicsrM_coverage.svh" `include "ZicsrF_coverage.svh" +`include "ZicsrU_coverage.svh" // `include "RV64VM_PMP_coverage.svh" // `include "RV64CBO_VM_coverage.svh" // `include "RV64CBO_PMP_coverage.svh" From 205db4348c1e362eaf55b4608cf38d89129213ff Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 16 Nov 2024 18:31:02 -0800 Subject: [PATCH 22/42] Fixed cause_m_time_interrupt most significant byte --- .../riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h | 2 +- .../riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h index 654c13568..f34ca6363 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h @@ -133,8 +133,8 @@ cause_m_time_interrupt: add t3, t2, t3 // add desired offset to the current time bgtu t3, t2, nowrap_m // check new time exceeds current time (no wraparound) addi t6, t6, 1 // if wrap, increment most significant word - sw t6,4(t4) // store into most significant word of MTIMECMP nowrap_m: + sw t6,4(t4) // store into most significant word of MTIMECMP sw t3, 0(t4) // store into least significant word of MTIMECMP time_loop_m: addi a3, a3, -1 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index d939c130e..5f6d14ecd 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -136,8 +136,8 @@ cause_m_time_interrupt: add t3, t2, t3 // add desired offset to the current time bgtu t3, t2, nowrap_m // check new time exceeds current time (no wraparound) addi t6, t6, 1 // if wrap, increment most significant word - sw t6,4(t4) // store into most significant word of MTIMECMP nowrap_m: + sw t6,4(t4) // store into most significant word of MTIMECMP sw t3, 0(t4) // store into least significant word of MTIMECMP time_loop_m: addi a3, a3, -1 From 99e5b295fb07880ebd2e50c6bf74c872a134f96f Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 16 Nov 2024 21:08:03 -0800 Subject: [PATCH 23/42] Update regression-wally fcov to work with new Makefile --- bin/regression-wally | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/regression-wally b/bin/regression-wally index cc0588bf6..c5b9c8f33 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -552,7 +552,7 @@ def main(): if args.ccov: os.system('make QuestaCodeCoverage') if args.fcov: - os.system('make -f '+WALLY+'/addins/cvw-arch-verif/Makefile merge') + os.system('make -C '+WALLY+'/addins/cvw-arch-verif merge') # Count the number of failures if num_fail: print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail) From 147f62d9a589fa54037c9b19347e24f28527036c Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 17 Nov 2024 06:43:13 -0800 Subject: [PATCH 24/42] Fixed timer offset in RV32 WALLY-wfi; simplified in RV64 WALLY-wfi --- .../rv32i_m/privilege/src/WALLY-wfi-01.S | 22 ++++++------ .../rv64i_m/privilege/src/WALLY-wfi-01.S | 36 ++++++++----------- 2 files changed, 26 insertions(+), 32 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-wfi-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-wfi-01.S index 61d73a4f7..65f564a1e 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-wfi-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-wfi-01.S @@ -36,20 +36,20 @@ WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources // Code copied from test library to cause m time interrupt, with time loop replaced with wfi. -/* Note: the following line might cause problems in the future. If more than 0x50 cycles are needed before the wfi +/* Note: the following line might cause problems in the future. If more than 0x100 cycles are needed before the wfi instruction begins, then the program might fall into a loop and run forever*/ -li x28, 0x50 // Desired offset from the present time -mv a3, x28 // copy value in to know to stop waiting for interrupt after this many cycles -la x29, 0x02004000 // MTIMECMP register in CLINT -la x30, 0x0200BFF8 // MTIME register in CLINT -lw x7, 0(x30) // low word of MTIME -lw x31, 4(x30) // high word of MTIME -add x28, x7, x28 // add desired offset to the current time -bgtu x28, x7, nowrap // check new time exceeds current time (no wraparound) -addi x31, x31, 1 // if wrap, increment most significant word -sw x31,4(x29) // store into most significant word of MTIMECMP + li x28, 0x100 // Desired offset from the present time + mv a3, x28 // copy value in to know to stop waiting for interrupt after this many cycles + la x29, 0x02004000 // MTIMECMP register in CLINT + la x30, 0x0200BFF8 // MTIME register in CLINT + lw x7, 0(x30) // low word of MTIME + lw x31, 4(x30) // high word of MTIME + add x28, x7, x28 // add desired offset to the current time + bgtu x28, x7, nowrap // check new time exceeds current time (no wraparound) + addi x31, x31, 1 // if wrap, increment most significant word nowrap: + sw x31,4(x29) // store into most significant word of MTIMECMP sw x28, 0(x29) // store into least significant word of MTIMECMP auipc ra, 0x0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-wfi-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-wfi-01.S index 6430f2078..3611f99ef 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-wfi-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-wfi-01.S @@ -35,30 +35,24 @@ WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources // Code copied from test library to cause m time interrupt, with time loop replaced with wfi. -li x28, 0x60 // Desired offset from the present time -mv a3, x28 // copy value in to know to stop waiting for interrupt after this many cycles -la x29, 0x02004000 // MTIMECMP register in CLINT -la x30, 0x0200BFF8 // MTIME register in CLINT -lw x7, 0(x30) // low word of MTIME -lw x31, 4(x30) // high word of MTIME -add x28, x7, x28 // add desired offset to the current time -bgtu x28, x7, nowrap // check new time exceeds current time (no wraparound) -addi x31, x31, 1 // if wrap, increment most significant word -sw x31,4(x29) // store into most significant word of MTIMECMP + li x28, 0x60 // Desired offset from the present time + mv a3, x28 // copy value in to know to stop waiting for interrupt after this many cycles + la x29, 0x02004000 // MTIMECMP register in CLINT + la x30, 0x0200BFF8 // MTIME register in CLINT + ld x7, 0(x30) // read MTIME + add x28, x7, x28 // add offset + sw x28, 0(x29) // MTIMECMP = MTIME + offset -nowrap: - sw x28, 0(x29) // store into least significant word of MTIMECMP + auipc ra, 0x0 + addi ra, ra, 0xC // load address after wfi into ra so we return to the right place after handling the time interrupt -auipc ra, 0x0 -addi ra, ra, 0xC // load address after wfi into ra so we return to the right place after handling the time interrupt + wfi // test wfi until trap goes off -wfi // test wfi until trap goes off - -li x28, 0x600d111 // magic number "good 111" to write to output after interrupt goes off. -// this tests whether wfi is a nop or not since we should get the output for the interrupt before this one -sd x28, 0(x6) -addi x6, x6, 8 -addi x16, x16, 8 + li x28, 0x600d111 // magic number "good 111" to write to output after interrupt goes off. + // this tests whether wfi is a nop or not since we should get the output for the interrupt before this one + sd x28, 0(x6) + addi x6, x6, 8 + addi x16, x16, 8 END_TESTS From 405ce4e6523bc1e264651030a02129b07328e680 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 17 Nov 2024 07:12:32 -0800 Subject: [PATCH 25/42] Updated IMPERAS_HOME to reflect their distribution --- site-setup.csh | 2 +- site-setup.sh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/site-setup.csh b/site-setup.csh index 867485a8d..63f1260be 100644 --- a/site-setup.csh +++ b/site-setup.csh @@ -49,7 +49,7 @@ setenv SPIKE_PATH $RISCV/bin # Change this for your path to riscv-isa-s setenv IDV $RISCV/ImperasDV-OpenHW if ($?IDV) then # echo "Imperas exists" - setenv IMPERAS_HOME $IDV/Imperas + setenv IMPERAS_HOME $IDV setenv IMPERAS_PERSONALITY CPUMAN_DV_ASYNC setenv ROOTDIR ~/ source ${IMPERAS_HOME}/bin/setup.sh diff --git a/site-setup.sh b/site-setup.sh index 8c03a2a36..34fe1eb42 100755 --- a/site-setup.sh +++ b/site-setup.sh @@ -66,7 +66,7 @@ export SPIKE_PATH=$RISCV/bin # Copy this as it is export IDV=$RISCV/ImperasDV-OpenHW if [ -e "$IDV" ]; then # echo "Imperas exists" - export IMPERAS_HOME=$IDV/Imperas + export IMPERAS_HOME=$IDV export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC export ROOTDIR=~/ source "${IMPERAS_HOME}"/bin/setup.sh From 6f45dcd22c921fcfc5d07d88ec905a4291a63fa5 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Sun, 17 Nov 2024 13:01:06 -0800 Subject: [PATCH 26/42] Updated nightly instructions in readme to use curl --- README.md | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index 40dc08d51..e302e33f6 100644 --- a/README.md +++ b/README.md @@ -196,12 +196,13 @@ Startups can expect to spend more than $1 million on CAD tools to get a chip to # Adding Cron Job for nightly builds If you want to add a cronjob you can do the following: -1) Set up the email client `mutt` for your distribution +1) Set up the email client `mutt` to send emails through the command line 2) Enter `crontab -e` into a terminal -3) add this code to test building CVW and then running `regression-wally --nightly` at 9:30 PM each day +3) add this code to test cloning CVW, making CVW's tests, then running `regression-wally --nightly --buildroot` every day at 21:30 in your local time ```bash -30 21 * * * bash -l -c "source ~/PATH/TO/CVW/setup.sh; PATH_TO_CVW/cvw/bin/wrapper_nightly_runs.sh --path {PATH_TO_TEST_LOCATION} --target all --tests nightly --send_email harris@hmc.edu,kaitlin.verilog@gmail.com" +30 21 * * * curl -L https://raw.githubusercontent.com/openhwgroup/cvw/refs/heads/main/bin/nightly_build.py | python - --path {PATH_FOR_NIGHTLY_RUNS} --target all --tests all --send_email harris@hmc.edu,rose@rosethompson.net ``` +This utility will take up approximately 100 GB on your hard drive. You can also run the script directly from `bin/nightly_build.py`. # Example wsim commands From 38acf24d831571eebc421d27399950cc3b979e95 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 20 Nov 2024 19:06:41 -0800 Subject: [PATCH 27/42] Reset code coverage when running regression --- bin/regression-wally | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/regression-wally b/bin/regression-wally index 9a2d29201..6f609ffa0 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -519,7 +519,7 @@ def main(): pass if args.ccov: TIMEOUT_DUR = 20*60 # seconds - os.system('rm -f questa/cov/*.ucdb') + os.system('rm -f questa/ucdb/* questa/cov/*') elif args.fcov: TIMEOUT_DUR = 8*60 os.system('rm -f questa/fcov_ucdb/* questa/fcov_logs/* questa/fcov/*') From fb59d8e32fc1c173f8cdff7a0a8fb6816205f194 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 20 Nov 2024 19:23:46 -0800 Subject: [PATCH 28/42] More imperas lics --- bin/regression-wally | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/regression-wally b/bin/regression-wally index 6f609ffa0..f53940d89 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -536,7 +536,7 @@ def main(): # max out at a limited number of concurrent processes to not overwhelm the system # right now fcov, ccov, nightly all use Imperas if (args.ccov or args.fcov or args.nightly): - ImperasDVLicenseCount = 8 # limit number of concurrent processes to avoid overloading ImperasDV licenses + ImperasDVLicenseCount = 16 # limit number of concurrent processes to avoid overloading ImperasDV licenses else: ImperasDVLicenseCount = 10000 # effectively no license limit for non-lockstep tests with Pool(processes=min(len(configs),multiprocessing.cpu_count(), ImperasDVLicenseCount)) as pool: From 0923fb918f2f79c92fe8aa9e7b999d44bb38acb4 Mon Sep 17 00:00:00 2001 From: Corey Hickson Date: Wed, 20 Nov 2024 23:51:29 -0800 Subject: [PATCH 29/42] Add Endian covergroups to fcov --- config/rv32gc/coverage.svh | 3 +++ config/rv64gc/coverage.svh | 3 +++ 2 files changed, 6 insertions(+) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index 93be70707..614cd5c3d 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -37,3 +37,6 @@ `include "ZicsrU_coverage.svh" `include "RV32VM_coverage.svh" `include "RV32VM_PMP_coverage.svh" +`include "EndianU_coverage.svh" +`include "EndianM_coverage.svh" +`include "EndianS_coverage.svh" \ No newline at end of file diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index 057e79898..07561b1de 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -36,6 +36,9 @@ `include "ZicsrM_coverage.svh" `include "ZicsrF_coverage.svh" `include "ZicsrU_coverage.svh" +`include "EndianU_coverage.svh" +`include "EndianM_coverage.svh" +`include "EndianS_coverage.svh" // `include "RV64VM_PMP_coverage.svh" // `include "RV64CBO_VM_coverage.svh" // `include "RV64CBO_PMP_coverage.svh" From 6ce4a030f22e34660e205852a9c758f8ff7b6951 Mon Sep 17 00:00:00 2001 From: Corey Hickson Date: Thu, 21 Nov 2024 03:20:13 -0800 Subject: [PATCH 30/42] Add ExceptionM to fcov --- config/rv32gc/coverage.svh | 5 +++++ config/rv64gc/coverage.svh | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index 93be70707..4b23573e1 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -8,6 +8,10 @@ // Define XLEN, used in covergroups `define XLEN32 1 +// Define relevant addresses +`define CLINT_BASE 64'h02000000 +`define ACCESS_FAULT_ADDRESS 32'h0000 + // Unprivileged extensions `include "RV32I_coverage.svh" `include "RV32M_coverage.svh" @@ -37,3 +41,4 @@ `include "ZicsrU_coverage.svh" `include "RV32VM_coverage.svh" `include "RV32VM_PMP_coverage.svh" +`include "ExceptionM_coverage.svh" diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index 057e79898..1756ec6a4 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -8,6 +8,10 @@ // Define XLEN, used in covergroups `define XLEN64 1 +// Define relevant addresses +`define CLINT_BASE 64'h02000000 +`define ACCESS_FAULT_ADDRESS 64'h00000000 + // Unprivileged extensions `include "RV64I_coverage.svh" `include "RV64M_coverage.svh" @@ -36,6 +40,7 @@ `include "ZicsrM_coverage.svh" `include "ZicsrF_coverage.svh" `include "ZicsrU_coverage.svh" +`include "ExceptionM_coverage.svh" // `include "RV64VM_PMP_coverage.svh" // `include "RV64CBO_VM_coverage.svh" // `include "RV64CBO_PMP_coverage.svh" From 34063f9fb66ae08a57974b52c767ced8d0b570c1 Mon Sep 17 00:00:00 2001 From: David Harris <74973295+davidharrishmc@users.noreply.github.com> Date: Thu, 21 Nov 2024 07:01:31 -0800 Subject: [PATCH 31/42] Revert "Add ExceptionM to fcov" --- config/rv32gc/coverage.svh | 5 ----- config/rv64gc/coverage.svh | 5 ----- 2 files changed, 10 deletions(-) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index 4b23573e1..93be70707 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -8,10 +8,6 @@ // Define XLEN, used in covergroups `define XLEN32 1 -// Define relevant addresses -`define CLINT_BASE 64'h02000000 -`define ACCESS_FAULT_ADDRESS 32'h0000 - // Unprivileged extensions `include "RV32I_coverage.svh" `include "RV32M_coverage.svh" @@ -41,4 +37,3 @@ `include "ZicsrU_coverage.svh" `include "RV32VM_coverage.svh" `include "RV32VM_PMP_coverage.svh" -`include "ExceptionM_coverage.svh" diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index 1756ec6a4..057e79898 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -8,10 +8,6 @@ // Define XLEN, used in covergroups `define XLEN64 1 -// Define relevant addresses -`define CLINT_BASE 64'h02000000 -`define ACCESS_FAULT_ADDRESS 64'h00000000 - // Unprivileged extensions `include "RV64I_coverage.svh" `include "RV64M_coverage.svh" @@ -40,7 +36,6 @@ `include "ZicsrM_coverage.svh" `include "ZicsrF_coverage.svh" `include "ZicsrU_coverage.svh" -`include "ExceptionM_coverage.svh" // `include "RV64VM_PMP_coverage.svh" // `include "RV64CBO_VM_coverage.svh" // `include "RV64CBO_PMP_coverage.svh" From 75ce5c8c99bae25dad53929095ebb8010001ca75 Mon Sep 17 00:00:00 2001 From: Georgia Tai Date: Thu, 21 Nov 2024 16:18:44 -0800 Subject: [PATCH 32/42] Code Coverage on Decompress unit --- tests/coverage/ifu.S | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/tests/coverage/ifu.S b/tests/coverage/ifu.S index eaceb71ce..054f4f336 100644 --- a/tests/coverage/ifu.S +++ b/tests/coverage/ifu.S @@ -50,6 +50,11 @@ main: c.sb s1, 0(s0) // exercise c.sb c.sh s1, 0(s0) // exercise c.sh + .hword 0x2005 // line 110 + .hword 0x6101 // line 114 + .hword 0x6201 // line 115 + .hword 0x0202 // Illegal compressed instruction with op = 10, Instr[15:13] = 000, c.slli x4, 0. Line 151 illegal instruction + .hword 0x4002 // Illegal compressed instruction with op = 10, Instr[15:13] = 010, c.lwsp zero, 0. Line 158 illegal instruction .hword 0x8C44 // Illegal compressed instruction with op = 00, Instr[15:10] = 100011, Instr[6] = 1 and 0's everywhere else. Line 119 illegal instruction .hword 0x9C00 // Illegal compressed instruction with op = 00, Instr[15:10] = 100111, and 0's everywhere else. Line 119 illegal instruction From cb09ff6bb6d4ab9c0f011a3eb1fc42fb4d9f7794 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 22 Nov 2024 11:32:56 -0800 Subject: [PATCH 33/42] Fix crt0 --- tests/custom/crt0/pre_main.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/custom/crt0/pre_main.c b/tests/custom/crt0/pre_main.c index fce61ffdf..3a5166558 100644 --- a/tests/custom/crt0/pre_main.c +++ b/tests/custom/crt0/pre_main.c @@ -2,6 +2,8 @@ #include "pcnt_driver.h" +extern int main(int argc, char *argv[]); + int pre_main(int argc, char *argv[]) { long int bpmp0, brcnt0, bpmp1, brcnt1; long int bpmp_diff, brcnt_diff; From 48ac38fb35e90aa70d6af835fdf3e948f2ec08c8 Mon Sep 17 00:00:00 2001 From: Corey Hickson Date: Sun, 24 Nov 2024 03:43:57 -0800 Subject: [PATCH 34/42] Add exceptionsM to fcov --- config/rv32gc/coverage.svh | 7 ++++++- config/rv64gc/coverage.svh | 5 +++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index 614cd5c3d..d3953b916 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -8,6 +8,10 @@ // Define XLEN, used in covergroups `define XLEN32 1 +// Define relevant addresses +`define CLINT_BASE 64'h02000000 +`define ACCESS_FAULT_ADDRESS 32'h0000 + // Unprivileged extensions `include "RV32I_coverage.svh" `include "RV32M_coverage.svh" @@ -39,4 +43,5 @@ `include "RV32VM_PMP_coverage.svh" `include "EndianU_coverage.svh" `include "EndianM_coverage.svh" -`include "EndianS_coverage.svh" \ No newline at end of file +`include "EndianS_coverage.svh" +`include "ExceptionsM_coverage.svh" \ No newline at end of file diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index 07561b1de..3974d7f96 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -8,6 +8,10 @@ // Define XLEN, used in covergroups `define XLEN64 1 +// Define relevant addresses +`define CLINT_BASE 64'h02000000 +`define ACCESS_FAULT_ADDRESS 64'h00000000 + // Unprivileged extensions `include "RV64I_coverage.svh" `include "RV64M_coverage.svh" @@ -39,6 +43,7 @@ `include "EndianU_coverage.svh" `include "EndianM_coverage.svh" `include "EndianS_coverage.svh" +`include "ExceptionsM_coverage.svh" // `include "RV64VM_PMP_coverage.svh" // `include "RV64CBO_VM_coverage.svh" // `include "RV64CBO_PMP_coverage.svh" From 034624523397179fc4ce5c85daff0979cfb8e7ce Mon Sep 17 00:00:00 2001 From: Corey Hickson Date: Sun, 24 Nov 2024 16:36:59 -0800 Subject: [PATCH 35/42] removed unused and redundant clint base variable --- config/rv32gc/coverage.svh | 1 - config/rv64gc/coverage.svh | 1 - 2 files changed, 2 deletions(-) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index d3953b916..b05362f8d 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -9,7 +9,6 @@ `define XLEN32 1 // Define relevant addresses -`define CLINT_BASE 64'h02000000 `define ACCESS_FAULT_ADDRESS 32'h0000 // Unprivileged extensions diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index 3974d7f96..85abee104 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -9,7 +9,6 @@ `define XLEN64 1 // Define relevant addresses -`define CLINT_BASE 64'h02000000 `define ACCESS_FAULT_ADDRESS 64'h00000000 // Unprivileged extensions From c105c4c720e945570311ca2f804219346cdc5826 Mon Sep 17 00:00:00 2001 From: Corey Hickson Date: Sun, 24 Nov 2024 17:04:12 -0800 Subject: [PATCH 36/42] restored clint base for interrupt tests --- config/rv32gc/coverage.svh | 1 + config/rv64gc/coverage.svh | 1 + 2 files changed, 2 insertions(+) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index b05362f8d..0403b7e4b 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -10,6 +10,7 @@ // Define relevant addresses `define ACCESS_FAULT_ADDRESS 32'h0000 +`define CLINT_BASE 64'h02000000 // Unprivileged extensions `include "RV32I_coverage.svh" diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index 85abee104..e7c574020 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -10,6 +10,7 @@ // Define relevant addresses `define ACCESS_FAULT_ADDRESS 64'h00000000 +`define CLINT_BASE 64'h02000000 // Unprivileged extensions `include "RV64I_coverage.svh" From 7be6311f51807104317d81705603a4f21de2c826 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 25 Nov 2024 08:11:50 -0800 Subject: [PATCH 37/42] Update cvw-arch-verif submodule --- addins/cvw-arch-verif | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/cvw-arch-verif b/addins/cvw-arch-verif index 6d658b7b4..812f30af7 160000 --- a/addins/cvw-arch-verif +++ b/addins/cvw-arch-verif @@ -1 +1 @@ -Subproject commit 6d658b7b42c83fd584008d72964cc75d0876b769 +Subproject commit 812f30af765c0a692c506e42493f494278c00fe0 From 55fb7e07b3dca67557d6131c62eeae87cc8c5163 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 25 Nov 2024 08:12:52 -0800 Subject: [PATCH 38/42] Add cvw-arch-verif to main Makefile --- Makefile | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 323b18b1d..52513a812 100644 --- a/Makefile +++ b/Makefile @@ -6,9 +6,9 @@ MAKEFLAGS += --output-sync --no-print-directory SIM = ${WALLY}/sim -.PHONY: all riscof testfloat combined_IF_vectors zsbl benchmarks coremark embench coverage clean +.PHONY: all riscof testfloat combined_IF_vectors zsbl benchmarks coremark embench coverage cvw-arch-verif clean -all: riscof testfloat combined_IF_vectors zsbl coverage # benchmarks +all: riscof testfloat combined_IF_vectors zsbl coverage cvw-arch-verif # benchmarks # riscof builds the riscv-arch-test and wally-riscv-arch-test suites riscof: @@ -36,6 +36,10 @@ embench: coverage: $(MAKE) -C tests/coverage +cvw-arch-verif: + $(MAKE) -C ${WALLY}/addins/cvw-arch-verif + clean: $(MAKE) clean -C sim $(MAKE) clean -C ${WALLY}/tests/fp + $(MAKE) clean -C ${WALLY}/addins/cvw-arch-verif From 53fe1c2598ff186c3b413ea0e0343807f4ac9118 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 17 Nov 2024 00:00:40 -0800 Subject: [PATCH 39/42] Add dependabot file --- .github/dependabot.yml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 .github/dependabot.yml diff --git a/.github/dependabot.yml b/.github/dependabot.yml new file mode 100644 index 000000000..a91ebaf1d --- /dev/null +++ b/.github/dependabot.yml @@ -0,0 +1,17 @@ +# To get started with Dependabot version updates, you'll need to specify which +# package ecosystems to update and where the package manifests are located. +# Please see the documentation for all configuration options: +# https://docs.github.com/code-security/dependabot/dependabot-version-updates/configuration-options-for-the-dependabot.yml-file + +version: 2 +updates: + # Update git submodules to latest version + - package-ecosystem: "gitsubmodule" + directory: "/" + schedule: + interval: "weekly" + # Update actions in the GitHub Actions workflow files + - package-ecosystem: "github-actions" + directory: "/" + schedule: + interval: "weekly" From aa72ed1c19d49db60420322857884416ffc6073e Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Mon, 25 Nov 2024 16:36:14 +0000 Subject: [PATCH 40/42] Bump addins/verilog-ethernet from `c180b22` to `6f5ea41` Bumps [addins/verilog-ethernet](https://github.com/rosethompson/verilog-ethernet) from `c180b22` to `6f5ea41`. - [Commits](https://github.com/rosethompson/verilog-ethernet/compare/c180b22ed5f4112d0ef35b2c5ac1acc45f9ebb5d...6f5ea41584c49543e63415e37356ebb24b07d89d) --- updated-dependencies: - dependency-name: addins/verilog-ethernet dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- addins/verilog-ethernet | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/verilog-ethernet b/addins/verilog-ethernet index c180b22ed..6f5ea4158 160000 --- a/addins/verilog-ethernet +++ b/addins/verilog-ethernet @@ -1 +1 @@ -Subproject commit c180b22ed5f4112d0ef35b2c5ac1acc45f9ebb5d +Subproject commit 6f5ea41584c49543e63415e37356ebb24b07d89d From 7d80a8992a535710eed2702106ce8359b5a45aa0 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 25 Nov 2024 08:55:46 -0800 Subject: [PATCH 41/42] Remove FreeRTOS --- .gitmodules | 3 --- addins/FreeRTOS-Kernel | 1 - 2 files changed, 4 deletions(-) delete mode 160000 addins/FreeRTOS-Kernel diff --git a/.gitmodules b/.gitmodules index 34a374174..5a1e8d4dc 100644 --- a/.gitmodules +++ b/.gitmodules @@ -8,9 +8,6 @@ [submodule "addins/coremark"] path = addins/coremark url = https://github.com/eembc/coremark -[submodule "addins/FreeRTOS-Kernel"] - path = addins/FreeRTOS-Kernel - url = https://github.com/FreeRTOS/FreeRTOS-Kernel.git [submodule "addins/vivado-boards"] path = addins/vivado-boards url = https://github.com/Digilent/vivado-boards/ diff --git a/addins/FreeRTOS-Kernel b/addins/FreeRTOS-Kernel deleted file mode 160000 index 17a46c252..000000000 --- a/addins/FreeRTOS-Kernel +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 17a46c252f2f237e03a6768c5d15731215322f31 From 015b3f0d680f94a93720abf2434962d6b87c49d7 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Mon, 25 Nov 2024 16:59:13 +0000 Subject: [PATCH 42/42] Bump addins/vivado-boards from `e5f0728` to `8ed4f99` Bumps [addins/vivado-boards](https://github.com/Digilent/vivado-boards) from `e5f0728` to `8ed4f99`. - [Commits](https://github.com/Digilent/vivado-boards/compare/e5f0728cd284d10080ae8eb03fc86e7b5eafcb72...8ed4f9981da1d80badb0b1f65e250b2dbf7a564d) --- updated-dependencies: - dependency-name: addins/vivado-boards dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- addins/vivado-boards | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/vivado-boards b/addins/vivado-boards index e5f0728cd..8ed4f9981 160000 --- a/addins/vivado-boards +++ b/addins/vivado-boards @@ -1 +1 @@ -Subproject commit e5f0728cd284d10080ae8eb03fc86e7b5eafcb72 +Subproject commit 8ed4f9981da1d80badb0b1f65e250b2dbf7a564d